Cédric MARCHAND (PhD student Lab-STICC & NXP)

Cedric.marchand@univ-ubs.fr

Emmanuel BOUTILLON , Laura Conde-Canencia (Lab-STICC)

Conflict Resolution by Matrix

reordering for DVB-S2,-T2,-C2

LDPC Decoders

2/06/08

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 2

Context

Cédric Marchand – PhD student (December 2007 to December 2010), NXP and LABSTIC

– Subject: LDPC decoder for DVB-T2, Dual stream aspect

NXP semiconductor (Caen, FRANCE) – Channel group, Physical Layer

Lab-STICC research center (Lorient, FRANCE) – Emmanuel BOUTILLON (professor at UBS, thesis director)

– Digital communication, architecture, algorithm

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 3

Context: DVB-S2,T2,C2 standards

DVB-S2 ( Satellite ) (2003)

DVB-T2 ( Terrestrial ) (2009)

DVB-C2 (cable) (2009)(draft)

DVB standards

DVB-S2,T2,C2 standards use the same LDPC codes

DVB-S2,T2,C2 codes are structured codes

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 4

Structured code example

1010

0111H

100000100000

010000010000

001000001000

000100100100

000010010010

000001001001

1H

001000100000

100000010000

010000001000

000010100100

000001010010

000100001001

2H

Code Structure

Prototype matrix

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 5

Context: Layered decoder

Efficient Layered Decoder for Wi-Fi, WiMAX...and DVB-S2,-T2,-C2

Memory Conflicts if layered decoder is used on DVB-S2,-T2,-C2.

Existing solution based on delta architecture use heavy patch and two barrel shifters

Goal: solve these memory conflicts without changing the layered decoder

Layered decoder

Horizontal

schedule

Faster

convergence

Check-node

centric

architecture

Memory

saving

Structured

code

High

parallelism

Layered decoder

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 6

Matrix expending

Splitting process

Memory conflicts

Outline

Outline

Layered decoder

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 7

Semi-parallel architecture principle

001000100000

100000010000

010000001000

000010100100

000001010010

000100001001

2 H

Read VN

Write VN CNP

CNP

CNP

VGi

-1

3 messages

Architecture

CG1 CG2

VG1 VG2 VG3 VG4

VG1 VG2 VG3 VG4

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 8

CNPs RAM SO Barrel

shifter

shift

generator

VG

generator

P

P P

Simplified layered decoder architecture

shift VGread VGwrite

shift = shiftnew - shiftold

Architecture

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 9

Matrix expending

Splitting process

Memory conflicts

Outline

Outline

Layered decoder

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 10

Matrix Structure of a short frame, 2/3 rate

Matrix structure

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 11

Zoom on the matrix structure

Matrix structure

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 12

Zoom on the matrix structure

Shifted identity

matrix

Double Diagonal

Sub Matrix (DDSM)

Matrix structure

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 13

Memory overwrite example

VG1 VG2 VG3 VG3’

3 21

0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 0 1

VG1 VG2 VG3

0

Barrel shifter 1Overwrite!

=

Memory conflict

CG0

CG0

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 14

Matrix Structure of a short frame, 2/3 rate

Prototype matrix

There are 14 DDSMs in the matrix!

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 15

Matrix expending

Splitting process

Memory conflicts

Outline

Outline

Layered decoder

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 16

Splitting sub-matrix process

Cutting edge

12 cutting edge 0 cutting edge Split by 3

Splitting process

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 17

Problem of splitting

SS modmod 21 - The split process isn’t efficient if

- Splitting Reduce parallelism reduce throughput

S=3

82 21

Splitting process

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 18

Split factor two for rate 2/3 short frame

Number of conflicts:

Before split:14 x 360 =5040 After split two:8 x 180=1440

Splitting process

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 19

Results

Minimum parallelism for a 330MHZ decoder

Splitting process

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 20

Matrix expending

Splitting process

Memory conflicts

Outline

Outline

Layered decoder

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 21

+ No more double identity matrices

- Cost: one layer of 2 identity matrices

Matrix expending principle: parity check split

Split-extend

the layer

3 21

0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 0 1

VG1 VG2 VG3

0

0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1

VG1 VG2 VG3

0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1

DG

CG0 CG1

CG2

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 22

Principle: parity check split

VG1 VG2 VG3 VG3’

Dummy bits

Init with LLR=0

CG0

VG1 VG2 VG3 VG3’ DG

CG1 CG2

3 21

0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 0 1

VG1 VG2 VG3

0

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 23

Principle: parity check split

VG1 VG2 VG3 VG3’

CG0

MCG2VG3’=MCG0VG3’

Updating CG1 then CG2

VG1 VG2 VG3 VG3’ DG

CG1 CG2

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 24

Principle: parity check split

VG1 VG2 VG3 VG3’

CG0

VG1 VG2 VG3 VG3’ DG

CG1 CG2

MDGCG1it =MVG3’CG0

it-1

Updating CG1 then CG2

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 25

Simulation results

Long frame, parallelism of 40, normalized min-sum algorithm,

bit true, without BCH

1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.210

-10

10-8

10-6

10-4

10-2

100

Eb/N

o(dB)

BE

R

reference

extended

2/3 3/4 4/5 5/6

Simulation results

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 26

Error floor correction

VG1 VG2 VG3 VG3’

CG0

VG1 VG2 VG3 VG3’ DG

CG1 CG2

Problem:

MdC1it =MV3’C2

it-1

can lead to error floor

Solution:

read VG3’ instead of DG

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 27

1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.210

-10

10-8

10-6

10-4

10-2

100

Eb/N

o(dB)

BE

R

reference

extended

Simulation results

Long frame, parallelism of 40, normalized min-sum algorithm,

bit true, without BCH

2/3 3/4 4/5 5/6

Simulation results

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 28

Conclusion

- DDSMs in DVB-S2,-T2,-C2 codes spoil layered decoder efficiency.

+ A matrix reordering function of the parallelism reduces the number of

DDSMs.

+ Using parity check split solves the last DDSMs

+ We achieve an efficient Decoder architecture with one Barrel shifter

and dual port ram

Conclusion

Thanks for your attention

Any questions?

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 29

Annexes

Architecture

Base matrix construction

Delta based node processor

Matrix after parity check split

References

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 30

Architecture

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 31

Extended matrix rate 2/3, short frame, split of 3

20 40 60 80 100 120 140

5

10

15

20

25

30

35

40

45

50

Dummy bits

Extended 1

Extended 2

Extended 3

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 32

New base matrix construction

211

121

012'DDSM

baseH

Sold

i

new

i /

First diagonal: Second diagonal:

Svg old

ii mod

.23mod2

;03/2

1

1

vg

new .03mod6

;23/6

2

2

vg

new

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 33

Delta based node processor

Instead of computing the new SO, the node processor could deliver its

variation.

CNP

MCV

S0 -1

Shift Register

-

+ +

-

+

July 22, 2015

LDPC decoder for DVB-S2,T2,C2\ 34

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[4] “Air interface for fixed and mobile broadband wireless access systems,” in P802.16e/D12 Draft, (Washington, DC, USA), pp. 100–105, IEEE, 2005.

[5] M. M. Mansour and N. R. Shanbhag, “High-throughput LDPC decoders,” IEEE Transactions on Very Large Scale Integration VLSI Systems, vol. 11, pp. 976–996, Dec. 2003.

[6] Y. Sun, M. Karkooti, and J. Cavallaro, “High throughput, parallel, scalable LDPC encoder/decoder architecture for OFDM systems,” in Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on, (Richarson, USA), pp. 39–42, Oct. 2006.

[7] F. Kienle, T. Brack, and N. Wehn, “A synthesizable IP core for DVB-S2 LDPC code decoding,” in DATE ’05: Proceedings of the conference on Design, Automation and Test in Europe, (Munich, Germany), pp. 100– 105, IEEE Computer Society, Mar. 2005.

[8] M. Gomes, G. Falcao, V. Silva, V. Ferreira, A. Sengo, and M. Falcao, “Flexible parallel architecture for DVB-S2 LDPC decoders,” in Global Telecommunications Conference, 2007. GLOBECOM ’07. IEEE, (Washington, USA), pp. 3265–3269, Nov. 2007.

[9] J. Dielissen, A. Hekstra, and V. Berg, “Low cost LDPC decoder for DVB-S2,” in Design, Automation and Test in Europe, 2006. DATE ’06. Proceedings, vol. 2, (Munich, Germany), pp. 1–6, Mar. 2006.

[10] M. Rovini, G. Gentile, F. Rossi, and L. Fanucci, “A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes,” in Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on, (Atlanta, USA), pp. 236–241, Oct. 2007.

[11] T. Bhatt, V. Sundaramurthy, V. Stolpman, and D. McCain, “Pipelined block-serial decoder architecture for structured LDPC codes,” in Acous- tics, Speech and Signal Processing, 2006. ICASSP 2006 Proceedings. 2006 IEEE International Conference on, vol. 4, (Toulouse, France), p. IV, May 2006.

[12] T. Brack, M. Alles, F. Kienle, and N. Wehn, “A synthesizable IP core for WIMAX 802.16e LDPC code decoding,” in Personal, Indoor and Mobile Radio Communications, 2006 IEEE 17th International Symposium on, (Helsinki, Finland), pp. 1–5, Sept. 2006.

[13] M. Rovini, F. Rossi, P. Ciao, N. L’Insalata, and L. Fanucci, “Layered decoding of non-layered LDPC codes,” in Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on, (Dubrovnick, Croatia), pp. 537–544, Sept. 2006.

[14] D. Hocevar, “A reduced complexity decoder architecture via layered decoding of LDPC codes,” in Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on, (Austin, USA), pp. 107–112, Oct. 2004.

[15] M. Mansour and N. Shanbhag, “Low-power VLSI decoder architectures for LDPC codes,” in Low Power Electronics and Design, 2002. ISLPED ’02. Proceedings of the 2002 International Symposium on, (Monterey, USA), pp. 284–289, Aug. 2002.

[16] E. Boutillon and F. Guilloud, “LDPC decoder, corresponding method, system and computer program,” US patent 7,174,495 B2, Feb. 2007.

[17] M. Fossorier, M. Mihaljevic, and H. Imai, “Reduced complexity iterative decoding of low-density parity check codes based on belief propagation,” IEEE Transactions on communications, vol. 47, pp. 673–680, May 1999.

[18] F. Guilloud, E. Boutillon, and J.-L. Danger, “lambda-min decoding algorithm of regular and irregular LDPC codes,” Proceedings of the 3rd International Symposium on Turbo Codes and Related Topics, Sept. 2003.

[19] D. Divsalar, S. Dolinar, and C. Jones, “Construction of protrograph LDPC codes with linear minimum distance,” in Information Theory, 2006 IEEE International Symposium on, (Washington, USA), pp. 664– 668, July. 2006.