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PAVAI COLLEGE OF TECHNOLOGY,NAMAKKAL 637018

DEPARTMENT OF

ELECTRONICS AND COMMUNICATION ENGINEERING

III SEMESTER – B.E. (ECE)EC6311 ANALOG AND DIGITAL CIRCUITS

LABORATORY

1

CONTENTS

S.NO.

DATE NAME OF THE EXPERIMENT PAGENO.

MARKS SIGN

1. Design and implementation of code converters using

2. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder3. Design and implementation

4. Design and implementation of encoder and decoder

5. Construction and verification of 4 bit

6. Design and implementation of 3-bit synchronous up/down counter7. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops8. Frequency Response of CE / CB / CC amplifier

9. Frequency response of CS Amplifiers 10. Darlington Amplifier

11. Differential Amplifiers- Transfer characteristic.

12. CMRR Measurement 13. Cascode / Cascade amplifier14. Determination of bandwidth

of single stage and

2

15. Spice Simulation of Common Emitter and Common Source

AVERAGE MARKS

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EC6311 ANALOG AND DIGITAL CIRCUITSLABORATORY

LIST OF EXPERIMENTS

LIST OF ANALOG EXPERIMENTS:

1. Frequency Response of CE / CB / CC amplifier

2. Frequency response of CS Amplifiers

3. Darlington Amplifier

4. Differential Amplifiers- Transfer characteristic.

5. CMRR Measurment

6. Cascode / Cascade amplifier

7. Determination of bandwidth of single stage and multistage

amplifiers

4

8. Spice Simulation of Common Emitter and Common Source amplifiers

LIST OF DIGITAL EXPERIMENTS

9. Design and implementation of code converters using logic gates

(i) BCD to excess-3 code and vice versa (ii) Binary to gray and

vice-versa

10. Design and implementation of 4 bit binary Adder/ Subtractor

and BCD adder using IC 7483

11. Design and implementation of Multiplexer and De-multiplexer

using logic gates

12. Design and implementation of encoder and decoder using logic

gates

13. Construction and verification of 4 bit ripple counter and Mod-

10 / Mod-12 Ripple counters

14. Design and implementation of 3-bit synchronous up/down counter

15. Implementation of SISO, SIPO, PISO and PIPO shift registers

using Flip- flops

LOGIC DIAGRAM:BINARY TO GRAY CODE CONVERTOR

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TRUTH TABLE:

| Binary input | Gray code output |

B3 B2 B1 B0 G3 G2 G1 G0

0000000011111111

0000111100001111

0011001100110011

0101010101010101

0000000011111111

0000111111110000

0011110000111100

0110011001100110

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EXP NO: 9 DESIGN & IMPLEMENTATION OF CODE CONVERTERSDATE:AIM:

To design and implement 4-bit(i) Binary to gray code converter(ii) Gray to binary code converter(iii) BCD to excess-3 code converter(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:S.No. COMPONENT SPECIFICATIO

N QUANTITY

1. AND GATE 7408 12. OR GATE 7432 13. NOT GATE 7404 14. XOR GATE 7486 15. IC TRAINER KIT - 16. PATCH CORD - As Required

THEORY:The availability of large variety of codes for the same

discrete elements of information results in the use of different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different codes for same information. Thus, code converter isa circuit that makes the two systems compatible even though each uses different binary code.

The bit combination assigned to binary code to gray code.Since each code uses four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0 and the output variables are designated as C3, C2, C1,

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Co. from the truth table, combinational circuit is designed. The Boolean functions are obtained from K-Map for each outputvariable.

A code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code to Excess-3 code, the input lines must supply the bit combination of elements as specified by code and the output lines generate the corresponding bit combination of code. Each one of the four maps represents oneof the four outputs of the circuit as a function of the four input variables.

A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is C+D has been used to implement partially each of three outputs.

LOGIC DIAGRAM:GRAY CODE TO BINARY CONVERTOR

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TRUTH TABLE:

| Gray Code | Binary

Code |

G3 G2 G1 G0 B3 B2 B1 B0

0000000011111111

0000111111110000

0011110000111100

0110011001100110

0000000011111111

0000111100001111

0011001100110011

0101010101010101

PROCEDURE:(i) Connections were given as per circuit diagram.(ii) Logical inputs were given as per truth table(iii) Observe the logical output and verify with the

truth tables.

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LOGIC DIAGRAM:

BCD TO EXCESS-3 CONVERTOR

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TRUTH TABLE:| BCD input | Excess – 3 output |

B3 B2 B1 B0 G3 G2 G1 G0

0000000011111111

0000111100001111

0011001100110011

0101010101010101

0000011111xxxxxx

0111100001xxxxxx

1001100110xxxxxx

1010101010xxxxxx

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LOGIC DIAGRAM:

EXCESS-3 TO BCD CONVERTOR

TRUTH TABLE:

Excess – 3 Input BCD Output B3 B2 B1 B0 G3 G2 G1 G0

000001111

011110000

100110011

101010101

000000001

000011110

001100110

010101010

13

1 1 0 0 1 0 0 1

14

RESULT:

Thus the code converters were designed and verifiedusing the corresponding truth table.PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:4-BIT BINARY ADDER

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EXP NO: 10 DESIGN OF 4-BIT ADDER AND SUBTRACTORDATE:AIM:

To design and implement 4-bit adder and subtractor using IC 7483.APPARATUS REQUIRED:

S.No. COMPONENT SPECIFICATIO

N QUANTITY

1. IC 7483 12. NOT GATE 7404 13. XOR GATE 7486 1

16

4. IC TRAINER KIT - 15. PATCH CORD - As Required

THEORY:4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of next full adder in chain. The augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right toleft, with subscript 0 denoting the least significant bits. The carries are connected in chain through the full adder. The input carry to the adder is C0 and it ripples through the full adder to the output carry C4.4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder withinverters, placed between each data input ‘B’ and the corresponding input of full adder. The input carry C0 must beequal to 1 when performing subtraction.4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one common binary adder. The mode inputM controls the operation. When M=0, the circuit is adder circuit. When M=1, it becomes subtractor.PROCEDURE:

(i) Connections were given as per circuit diagram.(ii) Logical inputs were given as per truth table(iii) Observe the logical output and verify with the truth tables.

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LOGIC DIAGRAM:4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:4-BIT BINARY ADDER/SUBTRACTOR

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TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4

B3

B2

B1

C S4

S3

S2

S1

B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

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RESULT:Thus the 4-bit adder and Subtractor were designed and

implemented using the logic gates.LOGIC DIAGRAM FOR MULTIPLEXER:

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

TRUTH TABLE:

S1 S0 Y = OUTPUT0 0 D00 1 D11 0 D21 1 D3

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EXP NO: 11 DESIGN AND IMPLEMENTATION OF

MULTIPLEXER AND

DEMULTIPLEXER

AIM:To design and implement multiplexer and demultiplexer

using logic gates and study of IC 74150 and IC 74154.


N QUANTITY

1. 3 INPUT AND GATE 7411 22. NOT GATE 7404 13. XOR GATE 7486 14. IC TRAINER KIT - 15. PATCH CORD - As Required

THEORY:MULTIPLEXER:

Multiplexer means transmitting a large number of information units over a smaller number of channels or lines.A digital multiplexer is a combinational circuit that selectsbinary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input line and n selection lines whose bit combination determine which input is selected.DEMULTIPLEXER:The function of Demultiplexer is in contrast to multiplexer function. It takes information from one line and distributes

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it to a given number of output lines. For this reason, the demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines enable only one gate at a time and the data on the data input line will pass through the selected gate to the associated data output linePROCEDURE:

(i) Connections are given as per circuit diagram.(ii) Logical inputs are given as per circuit diagram.(iii) Observe the output and verify the truth table.

LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE:

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INPUT OUTPUTS1 S0 I/P D0 D1 D2 D30 0 0 0 0 0 00 0 1 1 0 0 00 1 0 0 0 0 00 1 1 0 1 0 01 0 0 0 0 0 01 0 1 0 0 1 01 1 0 0 0 0 01 1 1 0 0 0 1

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PIN DIAGRAM FOR IC 74150:

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RESULT:Thus the multiplexer and demultiplexer was studied and

verified.

LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE:

INPUT OUTPUTY1 Y2 Y3 Y4 Y5 Y6 Y7 A B C1 0 0 0 0 0 0 0 0 10 1 0 0 0 0 0 0 1 00 0 1 0 0 0 0 0 1 10 0 0 1 0 0 0 1 0 00 0 0 0 1 0 0 1 0 10 0 0 0 0 1 0 1 1 0

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0 0 0 0 0 0 1 1 1 1

EXP NO: 12 DESIGN AND IMPLEMENTATION OF ENCODER AND

DECODER

AIM: To design and implement encoder and decoder using

logic gates and study of IC 7445 and IC 74147.

APPARATUS REQUIRED:

Sl.No.

COMPONENT SPECIFICATION

QTY.

1. 3 I/P NAND GATE

IC 7410 2

2. OR GATE IC 7432 33. NOT GATE IC 7404 12. IC TRAINER KIT - 13. PATCH CORDS - 27

THEORY:

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ENCODER:An encoder is a digital circuit that perform inverse

operation of a decoder. An encoder has 2n input lines and

n output lines. In encoder the output lines generates the

binary code corresponding to the input value. In octal to

binary encoder it has eight inputs, one for each octal

digit and three output that generate the corresponding

binary code. In encoder it is assumed that only one input

has a value of one at any given time otherwise the

circuit is meaningless. It has an ambiguila that when all

inputs are zero the outputs are zero. The zero outputs

can also be generated when D0 = 1.

LOGIC DIAGRAM FOR DECODER:

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TRUTH TABLE:

INPUT OUTPUTE A B D0 D1 D2 D31 0 0 1 1 1 10 0 0 0 1 1 10 0 1 1 0 1 10 1 0 1 1 0 10 1 1 1 1 1 0

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DECODER:

A decoder is a multiple input multiple output logic

circuit which converts coded input into coded output

where input and output codes are different. The input

code generally has fewer bits than the output code. Each

input code word produces a different output code word i.e

there is one to one mapping can be expressed in truth

table. In the block diagram of decoder circuit the

encoded information is present as n input producing 2n

possible outputs. 2n output values are from 0 through out

2n – 1.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii)Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth

table.

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BCD TO DECIMAL DECODER:


36

RESULT: Thus the encoder and decoder was studied and verified.PIN DIAGRAM FOR IC 7476:

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CHARACTERISTICS TABLE:

Q Qt+1 J K0 0 0 X0 1 1 X1 0 X 11 1 X 0

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EXPT NO: 13 CONSTRUCTION &VERIFICATION OF 4 BIT RIPPLE COUNTER & MOD 10/MOD 12 RIPPLE COUNTERDATE:AIM:

To design and verify 4 bit ripple counter mod 10/ mod 12 ripplecounter.APPARATUS REQUIRED:

S.No. COMPONENT SPECIFICATIO

N QUANTITY

1. JK FLIP FLOP 7476 22. NAND GATE 7400 23. IC TRAINER KIT - 14. PATCH CORD - As Required

THEORY:A counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents the number of clock pulses arrived. A specified sequence of states appears as counter output. This is the main differencebetween a register and a counter. There are two types of counter, synchronous and asynchronous. In synchronous common clock is given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then each successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second stage is triggered by output of first stage. Because of inherent propagation delay time all flip flops are not activated at same time which results in asynchronous operation.PROCEDURE:


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LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

TRUTH TABLE:

CLK QA QB QC QD0 0 0 0 01 1 0 0 0

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2 0 1 0 03 1 1 0 04 0 0 1 05 1 0 1 06 0 1 1 07 1 1 1 08 0 0 0 19 1 0 0 110 0 1 0 111 1 1 0 112 0 0 1 113 1 0 1 114 0 1 1 115 1 1 1 1

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LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

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TRUTH TABLE:

CLK QA QB QC QD0 0 0 0 01 1 0 0 02 0 1 0 03 1 1 0 04 0 0 1 05 1 0 1 06 0 1 1 07 1 1 1 08 0 0 0 19 1 0 0 110 0 0 0 0

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LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

TRUTH TABLE:

CLK QA QB QC QD0 0 0 0 0

1 1 0 0 02 0 1 0 03 1 1 0 04 0 0 1 05 1 0 1 06 0 1 1 0

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7 1 1 1 08 0 0 0 19 1 0 0 110 0 1 0 111 1 1 0 112 0 0 0 0

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RESULT:Thus the 4-bit counter, Mod-10 and Mod-12 ripple

counters wasdesigned and implementedLOGIC DIAGRAM:

48

TRUTH TABLE:

EXP NO: 14 DESIGN AND IMPLEMENTATION OF 3 BIT

SYNCHRONOUS UP/DOWN

COUNTER

DATE:

AIM:

To design and implement 3 bit synchronous up/down

counter.

APPARATUS REQUIRED:

S.N COMPONENT SPECIFICATIO QUANTITY

49

o. N1. JK FLIP FLOP 7476 22. 3 INPUT AND GATE 7411 13. OR GATE 7432 14. XOR GATE 7486 15. NOT GATE 7404 16. IC TRAINER KIT - 17. PATCH CORD - As Required

THEORY:A counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of progressing in increasing order or decreasing order through a certain sequence. An up/down counter is also called bidirectional counter. Usually up/downoperation of the counter is controlled by up/down signal. When this signal is high counter goes through up sequence andwhen up/down signal is low counter follows reverse sequence.PROCEDURE:


RESULT: Thus the 3-bit synchronous up/down counters was

implemented successfully.

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PIN DIAGRAM:

LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK

Serial

in

Serial

out1 1 02 0 03 0 04 1 15 X 06 X 0

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7 X 1

EXP NO: 15 DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

DATE:

AIM:

To design and implement

(i) Serial in serial out

(ii) Serial in parallel out

(iii) Parallel in serial out

(iv) Parallel in parallel out


N QUANTITY

1. D FLIP FLOP 7474 22. OR GATE 7432 13. IC TRAINER KIT - 14. PATCH CORD - As Required

THEORY:A register is capable of shifting its binary information

in one or both directions is known as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with output of one flip flop connected to inputof next flip flop. All flip flops receive common clock pulseswhich causes the shift in the output of the flip flop. The simplest possible shift register is one that uses only flip flop. The output of a given flip flop is connected to the

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input of next flip flop of the register. Each clock pulse shifts the content of register one bit position to right.PROCEDURE:


LOGIC DIAGRAM:

SERIAL IN PARALLEL OUT:

TRUTH TABLE:

53

CLK DATA

OUTPUTQA QB QC QD

1 1 1 0 0 02 0 0 1 0 03 0 0 0 1 14 1 1 0 0 1

54

LOGIC DIAGRAM:

PARALLEL IN SERIAL OUT:

55

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P0 1 0 0 1 11 0 0 0 0 02 0 0 0 0 03 0 0 0 0 1

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LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

CLK

DATA INPUT OUTPUTDA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 12 1 0 1 0 1 0 1 0

58

RESULT:

Thus the implementation of shift registers using flip

flops was completed successfully.

CIRCUIT DIAGRAM FOR COMMON EMITTER AMPLIFIER

60

MODEL GRAPH

f 1 f2 f (Hz)

EXP. No : FREQUENCY RESPONSE OF CE / CB / CC AMPLIFIER DATE :

AIM:To construct common emitter, common collector and common base

amplifier and to plot the frequency response characteristics.

APPARATUS REQUIRED:

S.No

.

Name Range Quanti

ty

61

1. Transistor BC 107 12. Resistor 56kΩ,12kΩ,2.2kΩ,4

70Ω

1,1,1,

13. Capacitor 0.1µF, 47µF 2, 14. Function

Generator

(0-3)MHz 1

5. CRO 30MHz 16. Regulated power

supply

(0-30)V 1

7. Bread Board 1

PROCEDURE:

1. Connect the circuit as per the circuit diagram.2. Set Vi =2V, using the signal generator.3. Keeping the input voltage constant, vary the frequency from 0

Hz to 1M Hz in regular steps and note down the corresponding output voltage.

4. Plot the graph; Gain (dB) Vs Frequency (Hz).

TABULATION FOR FREQUENCY RESPONSE OF COMMON EMITTER AMPLIFIER

62

Keep the input voltage constant, Vin =

S.No

Frequency (inHz)

Output Voltage(in volts)

Gain= 20 log(Vo/Vin)(in dB)

63

THEORY:Common Emitter

This type of biasing is otherwise called Emitter Biasing. The

necessary biasing is provided using 3 resistors: R1, R2 and Re.

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The resistors R1 and R2 act as a potential divider and give a

fixed voltage to the base. If the collector current increases due

to change in temperature or change in β, the emitter current Ie

also increases and the voltage drop across Re increases, reducing

the voltage difference between the base and the emitter. Due to

reduction in Vbe, base current Ib and hence collector current Ic

also reduces. This reduction in Vbe, base current Ib and hence

collector current Ic also reduces. This reduction in the collector

current compensates for the original change in Ic.

The stability factor S= (1+β) * ((1/ (1+β)). To have better

stability, we must keep Rb/Re as small as possible. Hence the value

of R1 R2 must be small. If the ratio Rb/Re is kept fixed, S

increases with β.

65

CIRCUIT DIAGRAM FOR BJT COMMON COLLECTOR AMPLIFIER

MODEL GRAPH FOR FREQUENCY RESPONSE OF BJT COMMON COLLECTORAMPLIFIER

66

f 1 FIG..2 f2 f(Hz)

Common Collector: The d.c biasing in common collector is provided byR1, R2 and RE .The load resistance is capacitor coupled to the emitter terminal of the transistor.

When a signal is applied to the base of thetransistor ,VB is increased and decreased as the signal goespositive and negative, respectively. Considering VBE is constantthe variation in the VB appears at the emitter and emitter voltageVE will vary same as base voltage VB . Since the emitter is outputterminal, it can be noted that the output voltage from a commoncollector circuit is the same as its input voltage. Hence thecommon collector circuit is also known as an emitter follower.

67

TABULATION FOR FREQUENCY RESPONSE OF COMMON COLLECTOR AMPLIFIER


Frequency (in Hz) Output Voltage (involts)


68

CIRCUIT DIAGRAM FOR COMMON BASE AMPLIFIER

MODEL GRAPH FOR FREQUENCY RESPONSE OF BJT COMMON COLLECTORAMPLIFIER

f 1 FIG..2 f2 f(Hz)

71

TABULATION FOR FREQUENCY RESPONSE OF COMMON COLLECTOR AMPLIFIER


Frequency (in Hz) Output Voltage (involts)


73

RESULT:Thus, the Common Emitter, Common Base and Common

collector amplifier was constructed and the frequency responsecurve is plotted Common Emitter

The upper cutoff frequency is found to be= The lower cutoff frequency is found to be=

The bandwidth is found to be=Common Collector

The upper cutoff frequency is found to be= The lower cutoff frequency is found to be=

The bandwidth is found to be=

Common Base

The upper cutoff frequency is found to be=The lower cutoff frequency is found to be= The bandwidth is found to be=

S.No.

Name Range Quantity

1. Transistor BC 107 12. Resistor 15kΩ,10kΩ,680Ω,6k

Ω1,1,1,


Generator(0-3)MHz 1


supply(0-30)V 1

7. Bread Board 1

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CIRCUIT DIAGRAM FOR SOURCE FOLLOWER WITH BOOTSTRAPPED GATERESISTANCE

MODEL GRAPH FOR FREQUENCY RESPONSE OF FOR SOURCE FOLLOWER WITHBOOTSTRAPPED GATE RESISTANCE

76

f 1 f2 f(Hz)

EXP. No : SOURCE FOLLOWER WITH BOOTSTRAPPED GATERESISTANCE DATE :

AIM:To construct a source follower with bootstrapped gate

resistance amplifier and plot its frequency responsecharacteristics.

APPARATUS REQUIRED:

S.No. Name Range Quanti

ty1. Transistor BC107 22. Resistor 1kΩ,11 kΩ,1M kΩ 1,1,1

3. Regulated power supply (0-30)V 1

4. Signal Generator (0-3)MHz 15. CRO 30 MHz 16. Bread Board 17. Capacitor 0.01µF 2

THEORY:

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Source follower is similar to the emitter follower( the output source voltage follow the gate input voltage),the circuit has a voltage gain of less than unity, no phase reversal, high input impedance, low output impedance. Here the Bootstrapping is used to increase the input resistance by connecting a resistance in between gate and source terminals. The resister RA is required to develop the necessary bias for the gate.

TABULATION FOR FREQUENCY RESPONSE OF FOR SOURCE FOLLOWER WITHBOOTSTRAPPED GATE RESISTANCE

Keep the input voltage constant (Vin) =

Frequency (inHz)

Output Voltage (involts)

Gain = 20 log (Vo / Vin)(in dB)

78

PROCEDURE:

1. Connections are made as per the circuit diagram.2. The waveforms at the input and output are observed forcascode operations by varyingthe input frequency.

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3. The biasing resistances needed to locate the Q-pointare determined.

4. Set the input voltage as 1V and by varying the frequency,note the output voltage.

5. Calculate gain=20 log (Vo / Vin.)6. A graph is plotted between frequency and gain.

RESULT:

Thus, the Source follower with Bootstrapped gate resistancewas constructed and the gain was determined. The upper cutoff frequency is found to be= The lower cutoff frequency is found to be=


80

CIRCUIT DIAGRAM OF DARLINGTON AMPLIFIER USING BJT

MODEL GRAPH FOR FREQUENCY RESPONSE OF DARLINGTON AMPLIFIER USINGBJT

81

f 1 FIG..2 f2 f(Hz)

EXP. No :3 DARLINGTON AMPLIFIER USING BJTDATE :

AIM:To construct a Darlington current amplifier circuit and to

plot the frequency response characteristics.

APPARATUS REQUIRED:

S.No.

Name Range Quantity

1. Transistor BC 107 12. Resistor 15kΩ,10kΩ,680Ω,6k

Ω1,1,1,


Generator(0-3)MHz 1


supply(0-30)V 1

7. Bread Board 1

THEORY:

82

In Darlington connection of transistors, emitter

of the first transistor is directly connected to the base of the

second transistor .Because of direct coupling dc output current

of the first stage is (1+hfe )Ib1.

If Darlington connection for n transitor is considered, then

due to direct coupling the dc output current foe last stage is

(1+hfe ) n times Ib1 .Due to very large amplification factor even

two stage Darlington connection has large output current and

output stage may have to be a power stage. As the power amplifiers

are not used in the amplifier circuits it is not possible to use

more than two transistors in the Darlington connection.

In Darlington transistor connection, the leakage

current of the first transistor is amplified by the second

transistor and overall leakage current may be high, Which is not

desired.

TABULATION FOR FREQUENCY RESPONSEOF DARLINGTON AMPLIFIER


Frequency (in Output Voltage (in Gain= 20 log(Vo/Vin)

83

Hz) volts) (in dB)

PROCEDURE:

1. Connect the circuit as per the circuit diagram.2. Set Vi = 2 v, using the signal generator.

84

3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1M Hz in regular steps and note down the corresponding output voltage.4. Plot the graph; Gain (dB) vs. Frequency (Hz).5. Calculate the bandwidth from the graph.

RESULT:Thus, the Darlington current amplifier was constructed and

the frequency response curve is plotted. The upper cutoff frequency is found to be= The lower cutoff frequency is found to be=


85

CIRCUIT DIAGRAM FOR DIFFERENTIAL AMPLIFIER FOR DETERMININGTRANSFER CHARACTERISTICS

86

S.NoVg1 (involts) Vg2 (in volts) Id1(in mA) Id2(in mA)

EXP. No : DETERMINATION TRANSFER CHARACTERISTICS OFDIFFERENTIAL AMPLIFIERDATE :

AIM:To construct a differential amplifier using CMOS transistors

and to determine the dc drain current of individual transistors.

APPARATUS REQUIRED:

S.No. Name Range Quantit

y1. Transistor BC107 22. Resistor 4.7kΩ, 10kΩ 2,1


4. Function Generator (0-3) MHz 25. CRO 30 MHz 16. Bread Board 1

THEORY:The differential amplifier is a basic stage of an integrated

operational amplifier. It is used to amplify the difference

between 2 signals. It has excellent stability, high versatility

and immunity to noise. In a practical differential amplifier, the

87

output depends not only upon the difference of the 2 signals.

Transistor Q1 and Q2 have matched characteristics.

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. To determine the common mode gain, we set input signal with

voltage Vin=2V

and determine Vo at the collector terminals. Calculate

common mode gain, Ac=Vo/Vin.

3. To determine the differential mode gain, we set input

signals with voltages V1 and V2. Compute Vin=V1-V2 and find Vo

at the collector terminals. Calculate differential mode

gain, Ad=Vo/Vin.

4. Calculate the CMRR=Ad/Ac.

5. Measure the dc collector current for the individual

transistors.

RESULT:

Thus, the Differential amplifier was constructed and dc drain

current for the individual transistors is determined and the

transfer characteristics was drawn

CIRCUIT DIAGRAM FOR DIFFERENTIAL AMPLIFIER USING CMOSCOMMON MODE OPERATION

88

DIFFERENTIAL MODE OPERATION

89

EXP. No : CALCULATION OF CMMRR OF DIFFERENTIAL AMPLIFIER DATE :

AIM: To construct a differential amplifier using CMOS and to

calculate the CMRR.

APPARATUS REQUIRED:S.No. Name Range Quantit

y1. Transistor BC107 22. Resistor 4.7kΩ, 10kΩ 2,1


4. Function Generator (0-3) MHz 25. CRO 30 MHz 16. Bread Board 1

FORMULA:Common mode Gain (Ac) = VO / VIN

Differential mode Gain (Ad) = V0 / VIN

Where VIN = V1 – V2

Common Mode Rejection Ratio (CMRR) = Ad/Ac

Where, Ad is the differential mode gain

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Ac is the common mode gain.THEORY:

The differential amplifier is a basic stage of an integrated

operational amplifier. It is used to amplify the difference

between 2 signals. It has excellent stability, high versatility

and immunity to noise. In a practical differential amplifier, the

output depends not only upon the difference of the 2 signals but

also depends upon the common mode signal. Transistor Q1 and Q2

have matched characteristics.

For the differential mode operation the input is taken from

two different sources and the common mode operation the applied

signals are taken from the same source

Common Mode Rejection Ratio (CMRR) is an important parameter

of the differential amplifier. CMRR is defined as the ratio of the

differential mode gain, Ad to the common mode gain, Ac.

CMRR = Ad / Ac

In ideal cases, the value of CMRR is very high.

TABULATION FOR COMMON MODE GAIN OF DIFFERENTIAL AMPLIFIER

S.No V1 (in volts) V2 (in volts) V0 =V01-V02(involts)

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TABULATION FOR DIFFERENTIAL MODE GAIN OF DIFFERENTIAL AMPLIFIER

S.No V1 (in volts) V2 (in volts) V0 =V01-V02(involts)

CALCULATION:

PROCEDURE:

6. Connections are given as per the circuit diagram.

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7. To determine the common mode gain, we set input signal with

voltage Vin=2V and determine Vo at the drain terminals.

Calculate common mode gain, Ac=Vo/Vin.

8. To determine the differential mode gain, we set input signals

with voltages Vg1 and Vg2. Compute Vin=V1-V2 and find Vo at the

drain terminals. Calculate differential mode gain, Ad=Vo/Vin.

9. Calculate the CMRR=Ad/Ac.

10. Measure the dc collector current for the individual

transistors.

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RESULT:

Thus, the Differential amplifier was constructed and the CMRR

is calculated.

Commom Mode Rejection Ratio : =

CS

Differential Amplifiers

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model graph-Transfer characteristic.

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Differential Amplifiers- differential mode of operation

DifferentialAmplifiers-common modeof operation

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Cascode amplifier

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Cascade amplifier

Determination of bandwidth of single stage amplifiers

99

Determination of bandwidth of multistage amplifiers

100

common base

101

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