Www.advancedmsinc.com EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrow’s Technology Today

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<ul><li>Slide 1</li></ul> <p>www.advancedmsinc.com EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrows Technology Today Slide 2 www.advancedmsinc.com Slide 3 80486 and Pentium Slide 4 www.advancedmsinc.com 80486 Microprocessor Family 80486 Microprocessor Introduced in 1989 High Integration On-chip 8K Code and Data cache Floating Point Unit Paged, Virtual Memory Management 168-pin PGA package Multiprocessor Support Multiprocessor Instructions Cache Consistency Protocols Slide 5 www.advancedmsinc.com Internal Architecture of the 80486 Complex Reduced-Instruction-Set Computer (CRISC) RISC integer core Slide 6 www.advancedmsinc.com Real-Mode Software Model the same as that shown for the 80386 Slide 7 www.advancedmsinc.com Protected-Mode Software Architecture AC: Alignment-Check flag When this bit is set, an alignment check is performed during all memory accesses at privilege level 3. If an unaligned access takes place, exception 17 occurs. Slide 8 www.advancedmsinc.com Control Registers AM : alignment mask -- If this is switched to 0, the alignment check is masked out. NE : Numeric Error CD : cache disable NW : not write-through WP : write protect PCD : page-level cache disable PWT : page-level write transparent Slide 9 www.advancedmsinc.com System-Control Instruction Set + a flush bus cycle + a write-back bus cycle Slide 10 www.advancedmsinc.com Page Directory and Page Table Entries Slide 11 www.advancedmsinc.com Hardware Architecture of the 80486 Slide 12 www.advancedmsinc.com Signal Interfaces Pseudo-lock Slide 13 www.advancedmsinc.com On-Chip Cache of the 80486SX Slide 14 www.advancedmsinc.com Pentium Processor 32-bit Microprocessor 32-bit addressing 64-bit Data Bus Superscalar architecture Two pipelined integer units Capable of under one clock per instruction Pipelined Floating Point Unit Separate Code and Data Caches 8K Code, 8K Write Back Data 2-way 32-byte line size MESI cache consistency protocol Advance Design Features Branch Prediction 237-pin PGA Slide 15 www.advancedmsinc.com Internal Architecture of the Pentium Processors Slide 16 www.advancedmsinc.com Pentium Processor Pipeline and Instruction Flow 5 stage pipeline PF : prefetch D1 : Instruction decode D2 : Address Generation EX : Execute -ALU and Cache Access WB : Write Back Intel 486Pentium I1I1 I3I3 I2I2 I4I4 I1I1 I3I3 I2I2 I4I4 I1I1 I3I3 I2I2 I4I4 I1I1 I3I3 I2I2 I4I4 I1I1 I3I3 I2I2 I4I4 PF D1 D2 EX WB I1I1 I2I2 I5I5 I6I6 I7I7 I8I8 I3I3 I4I4 I1I1 I2I2 I5I5 I6I6 I7I7 I8I8 I3I3 I4I4 I1I1 I2I2 I5I5 I6I6 I7I7 I8I8 I3I3 I4I4 I1I1 I2I2 I5I5 I6I6 I7I7 I8I8 I3I3 I4I4 I1I1 I2I2 I5I5 I6I6 I7I7 I8I8 I3I3 I4I4 PF D1 D2 EX WB Slide 17 www.advancedmsinc.com Pentium Processor U, V pipes - pairing U : any instruction V : simple instructions as defined in the Pairing rules PF : instructions on chip cache or memory -&gt; prefetch buffers prefetch buffers - two independent pairs of line size(32 bytes) D1 : two parallel decoders D2 : address generation for operand fetch EX : ALU operations and data cache access WB : modify processor state ; complete execution Slide 18 www.advancedmsinc.com Branch Prediction Branch Target Buffer The processor accesses the BTB with the address of the instruction in the D1 stage example) inner_loop : mov byte ptr flag[edx], al PF D1 D2 EX WB add edx, ecx PF D1 D2 EX WB cmp edx, FALSE PF D1 D2 EX WB jle inner_loop PF 486 : 6 clocks Pentium : 2 clocks with branch prediction Slide 19 www.advancedmsinc.com EFLAGS Slide 20 www.advancedmsinc.com Control Registers of the Pentium Processor Slide 21 www.advancedmsinc.com Enhancements to the Instruction Set Slide 22 www.advancedmsinc.com Hardware Architecture Slide 23 www.advancedmsinc.com Memory Subsystem Slide 24 www.advancedmsinc.com Organization of the DRAM Array Slide 25 www.advancedmsinc.com RAS/CAS address MUX Slide 26 www.advancedmsinc.com Data Bus Transceiver Circuitry Slide 27 www.advancedmsinc.com On-Chip Cache Slide 28 www.advancedmsinc.com On-chip cache operating mode Slide 29 www.advancedmsinc.com </p>