PUBLIC

SENIOR VP & GENERAL MANAGER

MICROCONTROLLERS

GEOFF LEES

TECHNOLOGY APPLICATION IN

EMBEDDED PROCESSING

13 APRIL 2017

PUBLIC 1

Scaling & Diversification

Scalin

g

SensorsPrecision

AnalogHVNVM RFBiochips

Sense / Acquisition &

Connectivity

Functionality

Computational &

Graphics

Functionality

Leading-edge

process nodes (16/14, 10/7….)

enable digital / SoC

compute and performance

Long-lasting

shrink nodes (90, 40, 28…)

enable mixed-signal

integration for IoT

Diversification

PUBLIC 2

Embedded Processing – Yesterday’s Paradigm

MPU

MCU

40/28nm 16/14/10/7nmHigh Performance, High-level OS,

Graphics/Video/Display Processing

Low Power, Real-time OS, RF/NVM/Mixed-signal integration130/90nm 40/shrink

PUBLIC 3

Embedded Processing – Future16 / 14 / 10 / 7

High Performance, Power EfficiencyMixed-Signal, Broad Scalability

Operations-led ‘sustaining’Reuse existing foundry tooling

Computation & Machine Learning

FD-SOI

Shrink

Next-gen

back-end

memories

Manufacturable

Flash Processes

Em

be

dd

ed

Pro

ce

sso

rs

90 / 40

28/28shrink

PUBLIC 4

The New Normal – Scalability of Embedded Processing

Ultra-low PowerDynamic & Static

ARM v8/v8m + GPU/DSPARM v7/v7m + 2D/3D

ARM v7m + Audio

i.MX 6UL/ULL

i.MX RT

i.MX 6DQ+

i.MX 8

i.MX 7ULP

i.MX 8M

i.MX 8X

PUBLIC 5

i.MX 8QMA53 A53

A53 A53

A72

A72 M4 M4

4K Video 2x GPU (8 shaders)

MIPI-DSI MIPI-DSI MIPI-CSI

MIPI-CSI HDMI 2.0 Audio

1GbE

1GbE

PCIe PCIe

USB 3.0 x64 LPDDR4/DDR4

i.MX 7ULPA7 M4

2D/3D Graphics

SPIx4

MIPI-DSI

2x UART x4

I2C x8

USB x32 LPDDR2/3

i.MX 8QXP

A35 M4

4K Video 2x GPU (4 shaders)

MIPI-DSI MIPI-DSI

MIPI-CSI Audio

1GbE

1GbE PCIe

DSP

USB 3.0 & 2.0

x32 LPDDR4/DDR3L

A35

A35 A35

Only few representative features shown here

Not final - subject to change

i.MX 8DX

A35 M4

1080p Video 2x GPU (2 shaders)

MIPI-DSI MIPI-DSI

MIPI-CSI Audio

1GbE

PCIe

DSP

USB 2.0

x16 LPDDR4/DDR3L

A35

i.MX 8QA53 A53

A53 A53 M4 M4

4K Video

MIPI-DSI MIPI-DSI MIPI-CSI

MIPI-CSI HDMI 2.0 Audio

1GbE

1GbE

PCIe PCIe

USB 3.0x64 LPDDR4/DDR4

2x GPU (4 shaders)

DSP

PUBLIC 6

i.MX 8QM

i.MX 8QXP

i.MX 7ULP

1x

5x

12x

PUBLIC 7

i.MX 7ULP – 28nm FD-SOI Low-Power Application Processor

Application Domain

Real Time Domain

• High-level OS

• 3D/2D graphics

• Camera & Display

processing

• High-bandwidth

peripherals

• Real-time OS

• Monitor & Response

• Sensor fusion

• Signal processing

• Low-bandwidth

connectivity

Timers ARM Cortex® - A7with TrustZone

Instruction & Data Cache, L2 Cache

A7 connectivity(UART, I2C, USB, SPI, GPIO, etc.)

Internal SRAM

SecurityLow-power 2D/3D Graphics

Display Interface Camera InterfaceExternal Memory Support

ARM Cortex® - M4with DSP extensions

Cache, MPU, FPU

TCM

Analog Converters, Comparators

M4 connectivity(UART, I2C, I2S, SPI, GPIO, etc.)

Timers

RDC & Secure Access

Security External Memory Support

PUBLIC 8

Lower Leakage

same perf.

FD-SOI Enabling Wide Dynamic Operating Range

• Outstanding Power-Perf demonstrated

− Active mode @ 300MHz < 10mW

− Deep-sleep with SRAM retained: < 2.5mW

− Extremely low-leakage SRAM: ~ 0.5pA/bit

• Forward Body Bias (FBB) Expanded performance

• Reverse Body Bias (RBB) Lower leakage floor

• Dynamic biasing tunability - SoC & part-by-part

Leakage P

ow

er

Performance (Operating Frequency)

Bulk (HVt)

Bulk (LVt)

FD-SOI

no body bias

FD-SOI

with FBB

FD-SOI

with RBB

Higher perf. same leakage

Lower Leakage

> 100x

> 10x

PUBLIC 9

FD-SOI Enabling High-Precision Analog and High-Perf. RF

• 3x lower variation in

RON

• Dramatically improved

analog switch designs

RO

N(o

hm

s)

Input Voltage

FD-SOI

Bulk

VT

H(v

olts)

Gate Length

Pow

er

per

convers

ion

ADC Sampling Freq.

Bulk

SlowTypicalFast

FD-SOI

• Significantly tighter process

and less mismatch

• Tighter designs with less

trimming of analog designs

Bulk (market ADCs)

Source: Conceptualized from Prof. Boris Murmann’s presentation @ SOI Consortium, April 2016

FD-SOI

• Lowest power & high

sampling frequencies

• ADCs for fast data

sampling

Best-in-classSlowTypicalFast

CMOS

pass-gateLVt NMOS

PUBLIC 10

FD-SOI Enabling High-Precision Analog and High-Perf. RF

• 3x lower variation in

RON

• Dramatically improved

analog switch designs

RO

N(o

hm

s)

Input Voltage

FD-SOI

Bulk

VT

H(v

olts)

Gate Length

Pow

er

per

convers

ion

ADC Sampling Freq.

Bulk

SlowTypicalFast

FD-SOI

• Significantly tighter process

and less mismatch

• Tighter designs with less

trimming of analog designs

Bulk (market ADCs)

Source: Conceptualized from Prof. Boris Murmann’s presentation @ SOI Consortium, April 2016

FD-SOI

• Lowest power & high

sampling frequencies

• ADCs for fast data

sampling

Best-in-classSlowTypicalFast

CMOS

pass-gateLVt NMOS

“If you believe the future is about mobility, about more communications and low power consumption and cost sensitive IoT chips where analog and RF is about 50% of the chip, then FD-SOI has a good future.” - Bich-Yen Nguyen, Senior Fellow, Soitec

PUBLIC 11

FD-SOI: Process Technology for the Next-Generation IoT

Optimized Cost

High

Performance Low-power

Efficient RF

Integration

High-precision

Mixed-signal

Integration

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