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    An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

    SN65DSI84SLLSEC2G SEPTEMBER 2012REVISED JUNE 2018

    SN65DSI84 MIPI DSI Bridge To FLATLINK LVDSSingle Channel DSI to Dual-Link LVDS Bridge

    1

    1 Features1 Implements MIPI D-PHY Version 1.00.00

    Physical Layer Front-End and Display SerialInterface (DSI) Version 1.02.00

    Single Channel DSI Receiver Configurable forOne, Two, Three, or Four D-PHY Data Lanes PerChannel Operating up to 1 Gbps Per Lane

    Supports 18 bpp and 24-bpp DSI Video Packetswith RGB666 and RGB888 Formats

    Suitable for 60-fps WUXGA 1920 1200Resolution at 18-bpp and 24-bpp Color, 60 fps1366 768 at 18 bpp and 24 bpp

    FlatLink Output Configurable for Single-Link orDual-Link LVDS

    Supports Single Channel DSI to Dual-Link LVDSOperating Mode

    LVDS Output Clock Range of 25 MHz to 154 MHzin Dual-Link or Single-Link Modes

    LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or ExternalReference Clock (REFCLK)

    1.8-V Main VCC Power Supply Low Power Features Include SHUTDOWN Mode,

    Reduced LVDS Output Voltage Swing, CommonMode, and MIPI Ultra-Low Power State (ULPS)Support

    LVDS Channel SWAP, LVDS PIN Order ReverseFeature for Ease of PCB Routing

    ESD Rating 2 kV (HBM) Packaged in 64-pin 5-mm 5-mm BGA (ZQE) Temperature Range: 40C to 85C

    2 Applications Tablet PC, Notebook PC, Netbooks Mobile Internet Devices

    3 DescriptionThe SN65DSI84 DSI to FlatLink bridge features asingle-channel MIPI D-PHY receiver front-endconfiguration with 4 lanes per channel operating at 1Gbps per lane; a maximum input bandwidth of 4Gbps. The bridge decodes MIPI DSI 18bppRGB666 and 24 bpp RGB888 packets and convertsthe formatted video data stream to a FlatLinkcompatible LVDS output operating at pixel clocksoperating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS interface with four datalanes per link.

    The SN65DSI84 is well suited for WUXGA 1920 x1200 at 60 frames per second, with up to 24 bits-per-pixel. Partial line buffering is implemented toaccommodate the data stream mismatch between theDSI and LVDS interfaces.

    Designed with industry compliant interfacetechnology, the SN65DSI84 is compatible with a widerange of micro-processors, and is designed with arange of power management features including low-swing LVDS outputs, and the MIPI defined ultra-lowpower state (ULPS) support.

    The SN65DSI84 is implemented in a small outline5x5mm BGA at 0.5 mm pitch package, and operatesacross a temperature range from -40C to 85C.

    Device Information(1)PART NUMBER PACKAGE BODY SIZE (NOM)

    SN65DSI84 BGA MICROSTARJUNIOR (64) 5.00 mm 5.00 mm

    (1) For all available packages, see the orderable addendum atthe end of the datasheet.

    Typical Application

    http://www.ti.com/product/sn65dsi84?qgpn=sn65dsi84http://www.ti.com/product/SN65DSI84?dcmp=dsproject&hqs=pfhttp://www.ti.com/product/SN65DSI84?dcmp=dsproject&hqs=sandbuysamplebuyhttp://www.ti.com/product/SN65DSI84?dcmp=dsproject&hqs=tddoctype2http://www.ti.com/product/SN65DSI84?dcmp=dsproject&hqs=swdesKithttp://www.ti.com/product/SN65DSI84?dcmp=dsproject&hqs=supportcommunity

  • 2

    SN65DSI84SLLSEC2G SEPTEMBER 2012REVISED JUNE 2018 www.ti.com

    Product Folder Links: SN65DSI84

    Submit Documentation Feedback Copyright 20122018, Texas Instruments Incorporated

    Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 46 Specifications......................................................... 7

    6.1 Absolute Maximum Ratings ...................................... 76.2 EDS Ratings ............................................................ 76.3 Recommended Operating Conditions....................... 76.4 Thermal Information .................................................. 76.5 Electrical Characteristics........................................... 86.6 Switching Characteristics ........................................ 10

    7 Detailed Description ............................................ 137.1 Overview ................................................................. 137.2 Functional Block Diagram ....................................... 137.3 Feature Description................................................. 147.4 Device Functional Modes........................................ 157.5 Programming........................................................... 23

    7.6 Register Maps ......................................................... 248 Application and Implementation ........................ 33

    8.1 Application Information............................................ 338.2 Typical Application ................................................. 33

    9 Power Supply Recommendations ...................... 409.1 VCC Power Supply................................................... 409.2 VCORE Power Supply ........................................... 40

    10 Layout................................................................... 4010.1 Layout Guidelines ................................................. 4010.2 Layout Example .................................................... 41

    11 Device and Documentation Support ................. 4211.1 Receiving Notification of Documentation Updates 4211.2 Community Resources.......................................... 4211.3 Trademarks ........................................................... 4211.4 Electrostatic Discharge Caution............................ 4211.5 Glossary ................................................................ 42

    12 Mechanical, Packaging, and OrderableInformation ........................................................... 42

    4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

    Changes from Revision F (August 2015) to Revision G Page

    Deleted figure Shutdown and Reset Timing Definition While VCC Is High ........................................................................... 12 Changed the paragraph following Figure 8 ......................................................................................................................... 15 Changed Recommended Initialization Sequence To: Initialization Sequence ..................................................................... 15 Changed Table 2 .................................................................................................................................................................. 15 Changed item 3 in Video Stop and Restart Sequence From: Drive all DSI input lanes including DSI CLK lane to

    LP11. To: Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS. ............................................................... 33

    Changes from Revision E (October 2013) to Revision F Page

    Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device FunctionalModes, Application and Implementation section, Power Supply Recommendations section, Layout section, Deviceand Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

    Changed ULPS Itemized List, item 3 from "Wait for the PLL_LOCK bit (CSR 0x0A.7) to be set" to "Wait for aminimum of 3 ms." ................................................................................................................................................................ 14

    Changed Initialization Sequence Description for Init seq7 from "Wait for the PLL_LOCK bit to be set (CSR 0x0A.7)"to "Wait for a minimum of 3 ms." ......................................................................................................................................... 15

    Changed Table 6 Address 0x0A, Bit 7 description from "PLL_LOCK" to "PLL_EN_STAT" ................................................ 24 Changed Address 0x18, Bits 3, 2, 1, and 0 Descriptions in Table 8 for clarification. .......................................................... 26 Changed Item 1 of the Video STOP and Restart sequence from "Clear the PLL_EN bit to 0(CSR 0x0A.7)" to "Clear

    the PLL_EN bit to 0 (CSR 0x0D.0)" .................................................................................................................................... 33

    Changes from Revision D (August 2013) to Revision E Page

    Added rows for Bits 7, and 6:5 to CSR Bit Field Definition DSI Registers........................................................................ 25

    http://www.ti.com/product/sn65dsi84?qgpn=sn65dsi84http://www.ti.comhttp://www.ti.com/product/sn65dsi84?qgpn=sn65dsi84http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLLSEC2G&partnum=SN65DSI84

  • 3

    SN65DSI84www.ti.com SLLSEC2G SEPTEMBER 2012REVISED JUNE 2018

    Product Folder Links: SN65DSI84

    Submit Documentation FeedbackCopyright 20122018, Texas Instruments Incorporated

    Changes from Revision C (December 2012) to Revision D Page

    Aligned package description throughout datasheet................................................................................................................ 1

    Changes from Revision A (December 2012) to Revision B

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