UNDER EMBARGO UNTIL 21 JUNE 2017

DIRECTOR OF ENGINEERING (恩智浦微处理器事业部研发总监, 恩智浦强芯总经理）NXP SEMICONDUCTORS

MAGGIE QIU (仇雨菁)

Design of Advanced Applications

Processors in FD-SOI

高端应用处理器设计中的FDSOI使用

SEP 21ST , 2017

i.MX – Application Processor for

Automotive, Industrial and Consumer

i.MX – Applications Processor for

Automotive, Industrial and Consumer

Over 400M i.MX SOCs shipped to date

Over 113M vehicles enabled with i.MX since 2007

#1 in eReaders, #1 in Auto Infotainment Applications Processors

2007 2008 2009 2010 2011 2012 2013 2014 2015

i.MX i.MX Auto

Source: IHS Technology, - Q2 2015

i.MX Driving Explosive Growth in Automotive and Smart Devices

SONY HAP-S1

HDD, Lenbrook Bluesound

Node, Aether cone

HSAE: Car

InfotainmentForyou: Car

InfotainmentBMW: i series remote

key

Home Automation & Building

Control: AMX, Lennox,

Honeywell, Leviton, Electrolux

OrCam: Eyeglasses

for visually impaired

Benesse:

Educational Tablet

Recent IoT Systems Powered by i.MX Processors

Pioneer Nex In-Dash

NavigationTransportation: Dreamliner Inflight Entertainment,

Austin B-Cycles, John Deere Tractor

SONY, Amazon, Kobo eReaders

8 of top 10

Automotive OEMs

Infotainment Systems

6 Top Luxury Brands

Reconfigurable LCD

Instrument Clusters

Hertz Neverlost

POS

Medical: Masimo, Philips, Withings, etc.

PPA Requirements for Different Applications

Performance

Power

Area

Performance

Power

Area

Performance

PowerArea

Embedded Processing – Yesterday’s Paradigm

Diversification

MPU

MCU

40/28nm 16/14/10/7nmHigh Performance, High-level OS,

Graphics/Video/Display

Processing

Low Power, Real-time OS,

RF/NVM/Mixed Signal

Integration130/90nm 40/shrink

Embedded Processing – Future

High Performance, Power

Efficiency

Mixed-Signal, Broad Scalability

Operations-led ‘sustaining’

Reuse existing foundry tooling

Computation & Machine Learning

FD-SOI

FD-SOI Shrink

Next-Gen

Back-End

Memories

Manufacturable

Flash Processes

Em

bed

de

d P

rocesso

rs

90 / 40

28

FD-SOI Technology

FD-SOI Transistors vs. Bulk Transistors

(SOIconsortium_FDSOI_QA.pdf, April 2010)

Intrinsic Advantages of FD-SOI

SaferImmunity to latch-up and soft errors

Reliable Shorter channel length, reduced variability

Low LeakageLeading low power capability

Most Scalable Solution Perfect for high performance & low power design

1

2

3

4

FD-SOI In i.MX

• RVT and LVT available

• Within same VT, different

gate length modulates

power/performance

• Nominal 1.0V

• Overdrive 1.1V

• Underdrive 0.9V

• Low Voltage

0.8V and below

• RVT theoretically supports

0.3v FBB to ~2.5V RBB.

• LVT theoretically supports

0.3v RBB to ~3.0v FBB

• Power gating

• Retention

1 2 3 4

Wide Range of Design Options to Choose From

Wide Range of

Voltage Range

Forward Biasing &

Reverse Biasing

Other 2 VTs & 4 Gate Lengths

Existing Physical Implementation Flow Applies

Place and Route

Timing

constraints

developmentSynthesis

Floorplanning

Physical design

signoff checks

Tape out (PG)

Timing

Signoff

STA

IR drop analysis

GLS

DV / DFTPackage

co-design

Placement

CTS

Detail route

Timing Closure

RTL

Static

checks

Electrical

analysis

Timing

Optimization

Local Library

Physical design database

Physical

Design

STA

Place & Route

Synthesis

External

Dependency

Different VTs cannot be mixed

Special guardring required to isolate different VTs

Special biasing generation logic required for body biasing

FBB/RBB difficult to mix

There are More to Consider …

More PVT corners , more complexity for physical design

Early Architecture Tradeoffs

• FBB, RBB or none?

• RVT or LVT ?

• Overdrive, Underdrive or Nominal?

• DVFS or not ?

• How to ease timing across different power domains?

• Always-ON or Switch-OFF?

Example of Power Architecture for FD-SOI Design

Performance VT Voltage Body Biasing Power Switch

High LVT Overdrive FBB Yes

Med RVT+LVT Nominal NA Yes

Low RVT Underdrive RBB Always-ON

NA RVT Ultra-low RBB Always-ON or Retention Mode

Physical Implementation Challenges

• Decide corner for synthesis

• Decide corner(s) to run P&R

• CTS strategy

• Guardring methodology

• Sign-off criteria

The New Normal – Scalable Embedded Processing

i.MX 8

i.MX 7ULP

i.MX 8X

PUBLIC

i.MX 8QM

A53 A53

A53 A53

A72

A72 M4 M4

4K Video 2x GPU (8 shaders)

MIPI-DSI MIPI-DSI MIPI-CSI

MIPI-CSI HDMI 2.0 Audio

1GbE

1GbE

PCIe PCIe

USB 3.0

x64 LPDDR4/DDR4

i.MX 7ULP

A7 M42D/3D Graphics

SPIx4

MIPI-DSI

2x UART x4

I2C x8

USB x32 LPDDR2/3

Low Power

High Performance

FD-SOI - Process Technology for the Next-Gen

IoT

Optimized Cost

High

Performance Low Power

Easy to

Implement

Faster Cycle

Time

PUBLIC

THANK YOU