novel 3 level bidirectional buck converter with wide
TRANSCRIPT
Novel 3 Level Bidirectional Buck Converter with wide Operating Range
for Hardware-in-the-Loop Test Systems
Christoph Carstensen, J¨urgen Biela Laboratory for High Power Electronic Systems (HPE), ETH Zurich
Physikstrasse 3, 8092 Zurich, Switzerland [email protected]
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15th International Power Electronics and Motion Control Conference, EPE-PEMC 2012 ECCE Europe, Novi Sad, Serbia
Novel 3 Level Bidirectional Buck Converterwith wide Operating Range
for Hardware-in-the-Loop Test SystemsChristoph Carstensen, Jurgen Biela
Laboratory for High Power Electronic Systems (HPE), ETH ZurichPhysikstrasse 3, 8092 Zurich, Switzerland
Abstract—For Hardware-in-the-Loop tests of components forthe distribution grid, for example circuit breakers, convertersystems are required, which can generate a high power outputwith fast transients of the output signal. In this paper, a novel3 level buck converter is presented, which is using 3 differentsupply voltages to enable a wide voltage operation range. Themodulation of the converter is presented and the design of aprototype system is performed and optimized for pulsed poweroperation. The prototype is compared to a hard-switched NPC-design.
Index Terms—arbitrary current source, Hardware-in-the-loop,3 level converter, buck converter
I. INTRODUCTION
For Hardware-in-the-Loop (HIL) tests of equipment usedin the distribution grid it is necessary to emulate the gridincluding disturbances like harmonics, spikes, distorted wave-
L1
Cout
IoutC1
High-FrequencySubmodules
Low-FrequencySubmodules
C2VC2
VC3
VC1
C3
VC
S1
S2
S3
S4
Fig. 1: Topology of the proposed Hardware-in-the-Loop System, consistingof a 6 times interleaved 3 level buck converter system and a Modular MultiLevel Marx Type Converter (M3TC), which is generating step voltages.
High-Frequency Submodule
Low-Frequency Submodule
Fig. 2: CAD model of the 6 times interleaved 3 level buck converter system,consisting of 6 modules, with an H-bridge IGBT module plus inductor (HFSubmodule), and one module with 2 paralleled high current H-bridge IGBTmodules (LF Submodule).
forms and short circuits. For this purpose converter systems arerequired, that are able to generate frequencies from DC up toseveral kHz. Furthermore, the operation range has to cover onthe one hand the full current and voltage range and on the otherhand the converter has to produce low parasitic ripple currentsand has to comply with different EMC standards. Typicalapplications of such arbitrary current and voltage sources forcontinuous operation are discussed in [1]–[3].
Due to the rising importance of HVDC for the transmissiongrid, HIL systems are required, which can emulate failureconditions of HVDC grids. To investigate the behavior ofHVDC circuit breakers, in [4] a HIL system for pulsedoperation is presented, which uses a combination of a MultiLevel Marx Type Converter (M3TC) as step voltage sourceand a continuous voltage source having an output voltage equalto half of a step voltage. By combining both sources it ispossible to generate arbitrary continuous voltage waveformswith a wide voltage and current range for a duration of up to100 ms.
For the continuous voltage source a high power arbitrarycurrent source is required, meeting the specifications listed
TABLE I: Specifications of 3 level buck converter system.
3 level converter moduleOutput voltage Vout 550 VOutput current Iout 1.4 kAMax. current gradient di/dt|max 10 A/µsOperation period TPeriod 100 ms
in Table I. A possibility for realizing the source could be aneutral point clamped 3-level converter (NPC). This kind ofconverters are mainly controlled by using PWM modulationstrategies under hard switching conditions. The drawback ofthe NPC topology is the unequally distributed losses betweenthe switches. To distribute these losses equally the activeneutral point clamped topology (ANPC) has been investigatedfor example in [5].
To reduce these switching losses, Zero Voltage Switchingcould be utilized, reducing the switching losses by approx-imately 30 % to 40 % for IGBTs ([6], [7]). But due to thenegative current within the inductor to enable ZVS, the RMScurrent of the IGBTs is increased resulting in a higher con-duction losses. For the proposed application of the convertersystem, the switching losses reduction is as large as theincrease of the conduction losses with the drawback of a higheroutput current ripple because of using a triangle current mode(TCM).
To reduce the number of required semiconductors andthus minimize the conduction losses, in this paper, a 3 levelbuck converter is presented, which is able to operate at awide voltage range from 0 V to 550 V at an arbitrary outputcurrent between 0 A and 1.4 kA. To enable the high requiredoutput current, the converter, depicted in Fig. 1, consists of 6paralleled and interleaved IGBT submodules.
In section II the proposed multi level buck topology is pre-sented and the operation principle is explained. In section IIIthe control and the modulation of the system is explained andvalidated by simulations of a prototype system with an outputvoltage range of 0..550 V and a maximal output current of1.4 kA in section IV. The design of this system, which isdepicted in Fig. 2, and the thermal losses in comparison toa NPC system are described in section V. Furthermore, theoptimization of the system for pulsed operation is performed.In section VI the charging and voltage balancing circuit for
S1
C1
Cout
L1
ILVC1
VC2
VC
C2
S2
S3
S4
Vcon
Fig. 3: 3 level buck converter system to generate converter output voltagesVcon = 0 V, Vcon = VC1 and Vcon = VC1 + VC2.
VC
L1
C1
C2
C3
S1
S2S3
S4
Vcon
VC1
VC2
VC3
Cout
Fig. 4: Proposed 3 level buck converter topology, enabling negative converteroutput voltages Vcon ≤ 0 V and consequently current shaping at VC closeto 0 V.
the pulsed operation is introduced.
II. MULTI-LEVEL BUCK CONVERTER TOPOLOGY
In Fig. 3, a 3 level buck converter [8] is depicted. Theswitches S3 and S4 are utilized to change the output voltagerange Vcon by adding VC2. Thus, the buck converter, consistingof S1, S2, C1, Lout and Cout can be used to generate arbitraryoutput voltages within the range of VC ≈ 0 V...VC1 + VC2.For VC < VC1 switch S3 is conducting and thus S1 and S2
are using Vcon = 0 V and Vcon = VC1 to control the currentIL. For VC ≥ VC1 switch S4 is turned on, allowing voltagesVcon = VC2 and Vcon = VC2 + VC1.
But as soon as the converter is operating at VC ≈ VC1
it is necessary to use the full dc link voltage VC1 + VC2 tocontrol the inductor current IL, i.e. switches S3 and S4 haveto be switched synchronously to S1 and S2, which results inincreased switching losses. To avoid these additional switching
VC1 + VC2 + VC3
VC,max
VC
VCon
Time t
Time t
0.5 · VC,max
VC3
VC1
-VC2
0
State S1
State S2
State S3
State S4
offon
offon
offon
offon
Fig. 5: Operation principle of the 3 level buck converter, showing the 4different output voltages −VC2, VC3, VC1, VC1 + VC2 + VC3 and theswitching signals to generate these voltages.
TABLE II: Converter output voltages Vcon at different switching states forthe 3 level buck converter and the proposed converter.
Nominal Output Current IN 5.6 kA
losses it is possible to choose VC2 < VC1. This results in anoverlap of the two operation voltage ranges for S1 and S2.
The remaining problem is, that the described convertercan not apply Vcon < 0 V, and thus no dynamic controlof the inductor current is possible. For this purpose, theproposed converter system, which is depicted in Fig. 4, usesan additional capacitor, which is generating an additionalnegative output voltage level. The detailed operation principleis depicted in Fig. 5 and Table II, where the operation for alinear rising output voltage is shown. At VC = 0 V switchS3 is conducting, allowing S1 and S2 to switch betweenvoltage levels Vcon = −VC2 and Vcon = VC1. As soon asVC =
VC,max
2 = VC1+VC3
2 switch S4 is turned on. At thisoperation point, it is still possible to apply VL = VC1−VC3
2and thus to control the current IL. For VC > VC2 switches S1
and S2 can generate Vcon = VC3 and Vcon = VC1+VC2+VC3
By using this topology it is possible to optimize the switchesS1 and S2 to low switching losses and the S3 and S4 to lowconduction losses.
A. Paralleling and Interleaving
Because the nominal current ICE,N of available IGBTmodules is limited to less than the required output currentdefined in Table I, it is necessary to parallel the convertersystem. This enables the additional benefit of interleaving thesystem, which could be used to cancel the ripple of the outputcurrent and use a smaller output inductance, which enablesfaster transients of the system.
To increase the maximal output current IL,total of the sys-tem, additional buck converters, consisting of one half bridgemodule for S1 and S2 and an inductor Li (HF submodule),have to be added in parallel to the buck converter. Theseconverters can be modulated interleaved to the existing ones.Switches S3 and S4 (LF submodule) can be paralleled butmust not be interleaved, thus the use of high current IGBTs is
0 50 100 150 200 250 300 350 400 450 500 5500
1
2
3
4
5
6
7
Output Voltage VC [V]
Cur
rent
Rip
ple
[%]
Idealinductor
(Li const)
Real inductor (Li not const)
Fig. 6: Current ripple of the sum of the inductor currents IL,i in relation tothe reference output current Iref for 6 interleaved converters.
a) b)
Ires, PP
IL1,PP
IL2,PP
IL3,PP
IL4,PP
IL5,PP
IL6,PP
Isum, PP
αsum, PP
IL5,PP
IL6,PP
γsum, PP
βsum, PP
Fig. 7: Vectorial addition of the ripple currents of the submodules: a) noadjustment of the phase-shift angles resulting in a remaining ripple vectorand b) addition of 4 submodule peak currents and cancelation of the resultingripple by adjusting the phase-shift angles φ5 and φ6.
possible to reduce the number of devices. The paralleled andinterleaved 3 level converter system is depicted in Fig. 1.
B. Ripple Minimization
The effect of the ripple cancelation is depicted in Fig. 6,showing the remaining output current ripple at different outputvoltages. Each HF submodule has a relative output ripple of25 % in relation to the reference output current IL,total. Byinterleaving, this ripple can be reduced to 0.5 % to 6 % independency of VC , assuming that all inductors have the sameinductance Li.
For repetitive tests with constant reference currents Iref andoutput voltages VC , the output current ripple can be minimizedby changing the ratio of the capacitor voltages VC,1, VC,2 andVC,3. With this it is possible to move the curves in Fig. 6 inthat way, that the operation point is at a minimum ripple andgenerate a very flat top of the current pulse with 0.5 % ripple.
An additional ripple on the output current is caused bymanufacturing tolerances of the inductors resulting in differentinductance values. In [9] a sorting algorithm is introduced,which measures the current ripple of each submodule. Sub-modules with similar ripples are controlled with a phase shiftof 180 ◦ to cancel the resulting ripple. Beside the fact, that thisalgorithm is only applicable to odd numbers of submodulesthe ripple cancelation is not optimal. In [10] an enhancedalgorithm is proposed, which uses the sorting algorithm of[9] for N − 2 modules and cancels the remaining ripple byvectorial addition of the last two submodule current ripplevectors.
Isum =
4∑i=1
|IPP,i|ejφi (1)
This concept has been adapted to the proposed convertersystem by calculating the resulting ripple of 4 submodules(c.f. Fig. 7). Therefore the peak-to-peak currents IPP,i, whichare identified by measuring the currents at the switchingtransitions, are added by using the amplitude |IPP,i| andphase-shift angle φi (1). The resulting ripple vector Isum iscompensated by adjusting the phase-shift angles φ5 and φ6 ofby using (2).
φ5 = αsum + π − βsum,PPφ6 = αsum + π + γsum,PP (2)
VCon VL
IL,1
IL,total
IL,total
Inductor L1
PI ControllerControlled
System
ControlledSystem
PI Controller
DT1 Controller
VL*
VL,pre*
IL,i*Iref IoutIL,total*IL,diff
IL,1
1N VCon*
VC VCState S3
PWM-
+-
- -
VCon VL
IL,2
Inductor L2
VL*IL,diff
IL,2
VCon*
VC VCState S3
PWM-
-
-
+
PI Controller
Fig. 8: Control circuit for the 3 level converter system, consisting of 6 independent control circuits, each with its own PI controller. Only the PWM modulationof all controllers are coupled and phase-shifted by φi.
The angles βsum,PP and γsum,PP can be calculated byusing (3) ([10]).
βsum,PP = 2 arctan
(r
s− |IPP,6|
)γsum,PP = 2 arctan
(r
s− |IPP,5|
)r =
√(s− |Isum|)(s− |IPP,5|)(s− |IPP,6|)
s
s =|Isum|+ |IPP,5|+ |IPP,6|
2(3)
A further improvement can be achieved by calculating thecomplex fourier coefficients IL,i(f) of the inductor currentsIL,i and minimize the vectorial sum of them. Therefore in(4) the inner part calculates the absolute sum for the k-thharmonics. By using the outer sum this is done for the firstN harmonics and the resulting function f could be minimized
0 50 100 150 200 250 300 350 400 450 500 5500
0.2
0.4
0.6
0.8
1
Voltage VC [V]
Cur
rent
Rip
ple
[%]
No Adjustment
Peak1st Harmonic
1st and 2nd Harmonic
1st, 2nd and 3rd Harmonic
Fig. 9: Remaining output current ripple with L1 = 17µH and L2, ..., L6 =20µH and an output filter with fg = 60 kHz. The peak compensation methodis proposed in [10] while the harmonics cancelation is done by minimizing(4) for N = 1, N = 2 and N = 3.
by numerical calculation methods to find the optimal ϕi.
f (ϕ2, ..., ϕ6) =
N∑k=1
∣∣∣∣∣IL,1(kω) +
6∑i=2
IL,i(kω) · ejk(φi+ϕi)
∣∣∣∣∣(4)
In Fig. 9 the remaining ripple is depicted for one inductorwith a lower inductance of L1 = 17µH and the other onesat the nominal value of 20µH and a low pass filter at fg =60 kHz. While the cancelation of the 1st harmonic and the in[10] proposed method is nearly the same, the cancelation ofthe 2nd and 3rd harmonics reduces the ripple by app. 20 %.
III. CONVERTER CONTROL
In [11] a comparative evaluation of a cascaded PI con-trol and two different model predictive control algorithmshas been performed with the result, that the PI controllerhas got the largest bandwidth, the smallest Total HarmonicDistortion (THD) and the smallest demand on calculationpower. Thus the control of the 6 times interleaved convertersystem is realized by using a cascaded controller as depictedin Fig. 8. Each of the 6 interleaved HF submodules has anseparate inner loop to adjust the same average of the inductorcurrent IL,i in all subsystems and a common outer loop tocontrol the value of the absolute output current. The PWMmodulation of the single control circuits are initialy phase-shifted by φi = (i+ 1) · 60◦ and afterwards adjusted by the insection II-B described algorithm. The use of only one controlloop, which is generating the same modulation signal di forall converters, would generate different average currents IL,iin each converter system due to tolerances of the inductorsand parasitic effects. This results in unequal thermal stressof the IGBT submodules. Thus the feedback loop of thecontrol is measuring the inductor currents IL,i and not the totaloutput current IL,total. To enable a high dynamic behavior ofthe converter system, the control circuit is calculated with ahigher frequency fcon than the switching frequency fs. Sothe controller, especially the integrator part, can react faster tochanges of the output parameters caused by other submodules.
The current IL,i has to be filtered by a second order low passfilter to avoid large controller interactions due to the switchingripple current.
A. Modulation
The generation of the converter output voltage Vcon,i is re-alized by a PWM modulation for S1 and S2 and a comparisonto generate the switching signals for S3 and S4.
As soon as VC = VC1+VC3
2 the state of S3 and S4 is changed(5). To avoid oscillations of the low frequency half bridgesubmodule a hysteresis has been inserted.
StateS3 =
1 for VC < VC1+VC3
2
0 for VC ≥ VC1+VC3
2
(5)
The modulation value d for the PWM is calculated by using(6). The first part of the equation is generating a value between0 and 2 and the switching state of S3 is subtracted.
d = 2VC + VC2
VC1 + 2VC2 + VC3− StateS3 (6)
By combining both (5) and (6) the modulation index d couldbe described with (7).
d =
VC+VC2
VC1+VC2for VC < VC1+VC3
2
VC−VC3
VC1+VC2for VC ≥ VC1+VC3
2
(7)
IV. SIMULATION RESULTS
The proposed converter has been simulated by usingGeckoCircuitsTM and controlled as an arbitrary currentsource. The chosen simulation parameters, which are listedin Table III, results in a maximal blocking voltage of theIGBTs of VCE,off = 420 V, which enables the use of600 V-IGBTs. The inductance value of the output inductorLi is chosen relatively small, resulting in a ripple current ofIpp ≈ 250 A , 25 %, but enabling high dynamics, which aremandatory for the proposed HIL setup.
In Fig. 10 the simulation result for two different currentwaveforms are shown, which represents typical test condi-tions [12]. At t = 3 ms . . . 4.5 ms a sinusoidal current withf = 3 kHz, peak-to-peak current Ipp = 1.8 kA and an offsetof Ioffset = 900 A, for t > 4.5 ms a rectangular pulse withf = 500 Hz, Ipp = 1.8 kA and Ioffset = 900 A, is generatedfor an output voltage VC , which is independent from the outputcurrent. In Fig. 10a) the reference output current Iref andthe total output current IL,total is depicted. The difference
TABLE III: Boundary conditions of the simulated 3 level buck converter.
Component ValueOutput Capacitor Cout 100µF
Output Inductor L 20µH
Output Voltage Range Vout 0 V...550 V
Switching Frequency fS 12 kHz
Supply Voltage VC1 295 V
VC2 125 V
VC3 255 V
3 3.5 4 4.5 5 5.5 6 6.5 7 7.5−0.5
0
0.5
1
1.5
2
Time t [ms]
Cur
rent
I L,g
es [k
A]
3 3.5 4 4.5 5 5.5 6 6.5 7 7.5−400
−200
0
200
400
600
Time t [ms]
Vol
tage
[V]
3 3.5 4 4.5 5 5.5 6 6.5 7 7.5
−200
0
200
400
Time t [ms]
Cur
rent
s [A
]
3 3.5 4 4.5 5 5.5 6 6.5 7 7.5
0
0.5
1
Time t [ms]
Dut
y C
ycle
3 3.5 4 4.5 5 5.5 6 6.5 7 7.50
1
Time t [ms]
Stat
e S 3
a)
b)
c)
d)
e)
Iref
+15 %
-15 %
VC
Vcon,1
VL,1
VL1,ref
IL,i
di
IL,total
Fig. 10: Simulation results of the proposed prototype system, generatingbetween t = 3 ms and t = 4.5 ms a sinusoidal output current withf = 3 kHz and afterwards a rectangular pulses with an amplitude ofImax = 1.8 kA: a) reference current value Iref and total output currentIL,total, b) output voltage VC , converter output voltage Vcon,1, real inductorvoltage VL and by the controller calculated average inductor current VL1,ref ,c) inductor currents IL,i, i = 1..6, d) duty cycle d1 and e) switching stateof switch S3.
between both is caused by the limited bandwith, which has tocompensate the PT2 behavior of the current measurement filterwith time constants of Tp,1 = 20µs and Tp,2 = 25µs. Thecontroller parameters are a trade off between the sinusoidaland rectangular output waveform, allowing a large signalstep response time of 70µs within a range of ±15 %. In b)the output voltage VC , the converter voltage Vcon,1, the realinductor voltage VL and reference average inductor voltageVL1,ref , which is calculated, are depicted, resulting in themodulation d1, which is depicted in d). In c) the outputcurrents IL,i of each converter are depicted and in e) the stateof switch S3 related to the voltage VC .
The simulation results are validating that the resultingoutput current ripple is less than 6 % of the total output currentdue to interleaving. Furthermore, the current IL,total is equallydistributed to all 6 converter systems.
V. DESIGN PROCESS OF THE PROTOTYPE SYSTEM
For optimizing the prototype design for pulsed operation, aloss model of the converter system has been developed (c.f.Fig. 11). Due to arbitrary output currents and waveforms themodel calculates the losses for every operating point withinthe operation range. In doing so in a first step the currentwaveform for a switching period and its fourier transformationis calculated. There the nonlinear behavior of the outputinductor has been taken into account by using the characteristiccurve to describe the inductance in dependency of the currentL(i). Based on the description of a switching period, theconduction and switching losses of the IGBTs are calculated.The core losses of the output inductor are calculated byusing the iGES method [13]. To identify the losses withinthe windings, the skin and proximity effect have been takeninto account and the thermal losses for a round wire, a definedhigh frequency litz wire (HF litz wire) and the optimal HF litzwire have been calculated. Based on these equations the lossesfor different output voltages VC = 0..500 V and differentaverage output currents Iavg = 0..400 A of a submodulehave been calculated and the litz wire could be optimized fordifferent operation areas. This calculation has been performedwith different IGBT modules to minimize the semiconductorlosses. Furthermore the system has been optimized for the bestratio between interleaved HF submodules for S1 and S2 andparalleled LF submodules for S3 and S4. The output inductor
Calculation of the Current
Waveform
Calculation of a Switching Periode
Calculation of a Converter Setup
Set Initial Valuesfor Voltage VC
and Current Iavg
Perform Sweepover Voltage VC and Current Iavg
Change Converter
Setup
Start
Fourier Transformation
Optimization ofLitz Wire
Calculation of Conduction Losses
Calculation of Switching Losses
Calculation of Total Losses, Efficiency and Thermal Boundaries
Optimization forPulsed Power Operation
Optimal Converter Design
Calculation of Winding Losses
Calculation of Core Losses
Fig. 11: Schematic illustration of the the calculation and optimization al-gorithm. The degrees of freedom for optimization are the ratio betweeninterleaved modules S1 / S2 and parallel modules S3 / S4, the HF litz wireparameters and the specific types of semiconductors.
Average Output Current Iavg [A]
Out
put V
olta
ge V C
[V]
50 100 150 200 250 300 350 400
50
100
150
200
250
300
350
400
450
500
550
Limit for Tp = 100 ms1 ms
100 µs10 ms
Continuous Operation
Fig. 12: Operation Area of the 3 level buck converter in dependency of thepulse length Tp for a maximal temperature difference between junction andcase of ∆T = 40 K enabling 106 pulses of the source.
has been optimized for minimal core losses. that convectiveair cooling is sufficient, resulting in minimized core losses.All components are listed in Table IV.
Because the system will be used for HIL-tests of circuitbreakers to simulate a distribution grid failure, the operationtime of the system is limited to less than 100 ms [12]. Thisresults in high pulsed losses in the devices. Due to the thermalcapacitances of the different materials the temperatures donot reach critical values. On the other hand the life timeof semiconductors is reduced because of the temperatureripple [14]. The FIT curve (Failure in Time) describes thisdependency between temperature difference and number ofpulse repetitions. Based on this curve the maximal temper-ature difference within the pulse duration must not exceed∆Tmax = 40 K to enable 106 pulses assuming at the endof each pulse a junction temperature of Tj = 125 ◦ and thusconsidering the worst case.
Rth,max =∆TmaxPLoss
(8)
The identification of the boundaries of the operation isdone by using the calculated losses of the IGBTs respectivelyof the antiparallel diodes to estimate the maximal thermal
0 100 200 300 400 500 600−2000
−1500
−1000
−500
0
500
1000
1500
2000
Output Voltage VC [V]
Cap
acito
r Cur
rent
s IC
[A]
IC1,mean
IC1,RMS
IC2,RMS
IC3,RMS
IC2,mean
IC3,mean
Fig. 13: Mean value of the currents of the energy supply capacitors C1, C2
and C3 in dependency of the output voltage VC .
TABLE IV: Components of the prototype system of the 3 level buck converter system.
Component Type DescriptionUpper half-bridge IGBT module 6 MicroSemi APTGT 300 A 60 D3G VCE,max = 600 V, ICE,N = 300 A
Lower half-bridge IGBT module 2 Infineon FF600 R06 ME3 VCE,max = 600 V, ICE,N = 600 A
Inductor core 12 Magnetics Kool Mu 0077337A7 ∅ = 134 mm, Ae = 678 mm2 and µr = 26
HF litz wire Pack Feindrahte Classic AWG 44 ca. 25.000× 50µm and da = 11 mm
Current measurement core 12 Magnetics Ferrite P-type ZP46113TC ∅ = 62 mm, Ae = 157 mm2
IGBT heat sink 6 Fischer Electronic SK92 150 mm Rth = 0.3 KW
IGBT heat sink 1 Fischer Electronic SK047 150 mm Rth = 0.15 KW
Inductor
Current Measurement
Heat SinkSnubber Capcitors
Busbar Connection
IGBT
Fig. 14: CAD model of the high frequency submodule, including the outputinductor, snubber capacitors to avoid over voltages, wide copper busbars toreduce the parasitic inductance and an inductive current measurement.
impedance (8). By comparing this maximal allowed possibleimpedance with the values in the data sheet of the module, themaximal pulse duration Tp can be identified. In Fig. 12 themaximal operation time of the converter system is depicted.For continuous operation the heat sink temperature cannotbe assumed as constant and the design has to consider themaximal junction temperature of the IGBT module.
For designing the energy supply capacitors C1, C2 and C3
the mean capacitor currents and the root mean square of thecurrents are important (c.f. Fig. 13). The ripple reduction of
Vol
tage
V C [V
]
Average Output Current Iavg [A]50 100 150 200 250 300 350 400
50
100
150
200
250
300
350
400
450
500
550
91
92
93
94
95
96
97
98
99
Fig. 15: Efficiency of the 3 level buck converter in dependency of the outputvoltage VC and the average output current Iavg .
the output current by interleaving is also affecting the capacitorcurrent and thus the RMS value of the current is almost equalto the mean current. Nevertheless the use of film capacitors isnecessary to handle the high currents.
The proposed design of one converter module is depicted inFig. 14. It is based on an integrated half-bridge module and isusing copper sheets to connect the busbar to the IGBT moduleto minimize the parasitic inductances between the switches.
A. Comparison with NPC topology
To evaluate the proposed 3 level buck converter topology,in Fig. 15 the efficiency of the system for different outputvoltages VC and output currents of Iout is shown. As referencesystem a NPC converter (c.f. Fig. 17) has been modeled,using an integrated NPC IGBT module of MicroSemi (APTGT300 TL 60G) with similar switching and conducting proper-ties. This topology allows the same output voltages like theproposed converter and the chip area of the semiconductorsis comparable. The calculated efficiency of the NPC system(Fig. 16) is in the same range, but with the difference thatthe losses at VC <
VC,max
2 are higher due to 3 conductingsemiconductors.
For interleaving the NPC System 4 additional IGBTs and 2diodes are necessary, including driver circuits for each switchresulting in a more complex system.
VI. CHARGING AND VOLTAGE BALANCING PRINCIPLE
Due to arbitrary output current and output voltage wave-forms of the converter system, the supply capacitor currents
Vol
tage
V C [V
]
Average Output Current Iavg [A]50 100 150 200 250 300 350 400
50
100
150
200
250
300
350
400
450
500
550
91
92
93
94
95
96
97
98
99
Fig. 16: Efficiency of a reference NPC converter in dependency of the outputvoltage VC and the average output current Iavg .
VCCout
L1
VMP
Vneg
S1
S2
S3
D5
D6
S4
Vpos
Vcon
Fig. 17: Neutral point clamped 3-level converter (NPC) with asymmetricsupply voltages Vpos = 675 V, VMP = 275 V and Vneg = 125 V.
are varying. In Fig. 13 the capacitor currents for different out-put voltages are shown. For high output voltages all capacitorsare discharged, while at small output voltages capacitor C2 ischarged. Thus the remaining energy and the capacitor voltagesafter each pulse are different and have to be balanced to enablethe next pulse.
To reduce the complexity of the charging system, only twosupply voltages for C1, C2, and C3 are used. The voltagebalancing between the capcitor C1 and C2 is done by usingan additional IGBT, which short-circuits the output capacitorCout (c.f. Fig. 18). By using this switch, positive inductorcurrents will transfer energy from C1 to C2. Negative currentsare working vice versa.
To charge the capacitors a Triple-Active-Bridge Converter(TAB) is utilized, having two DC-Ports with VDC,1 = VC1 +VC2 and VDC,2 = VC3 and an AC-Port to use a singlephase grid connection. This converter (c.f. Fig. 18) is basedon a novel transformer design, enabling independent powertransfer between arbitrary ports without influencing the thirdport. This enables the integration of Power Factor Correction(PFC), galvanic isolation and multiple output voltages in oneconverter system with the benefit of a reduced complexity. Thebasic idea of this converter is presented in [15], [16].
VII. CONCLUSION
In this paper, a novel multi level buck converter systemfor hardware-in-the-loop test setups for generating arbitrarycurrent waveforms is presented. The use of a small outputinductance and a high switching frequency enables high dy-namics up to di/dt = 10 A/µs. The resulting current ripple couldbe minimized by using a 6 times interleaved converter system.The new converter topology is using 2 diodes less than a NPCdesign but also provides 3 output levels. Furthermore, it ispossible to optimize 2 IGBTs for low switching losses and2 for low conduction losses. A prototype system is presentedwith an output current of Iout,max = 1.4 kA and an operatingrange of VC = 0 V..550 V.
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VDC,1
VDC,2
C2
C1
SBal
DBal
C3
Cout
L1
S1
S2
S3
S4
VC
Fig. 18: Charging and balancing circuit for the 3 level buck converter basedon a multi-port active bridge converter [15], [16].
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