multiplexers section 3-7 mano & kime. multiplexers & demultiplexers multiplexers (selectors)...
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Multiplexers
Section 3-7 Mano & Kime
Multiplexers & Demultiplexers
• Multiplexers (Selectors)
• Lab 1 – Behavioral VHDL -- Multiplexers
• MUX as a Universal Element
4– to– 1- Line Multiplexer
4–to–1-Line Multiplexer with Transmission Gates
Quadruple 2–to–1-Line Multiplexer
Typical uses
Multiplexers
• Multiplexers (Selectors)
• Lab 1 – Behavioral VHDL -- Multiplexers
• MUX as a Universal Element
Combinational Circuit Example
n-line 2-to-1 Multiplexer
n-line
2 x 1 MUX
a(n-1:0)
b(n-1:0)y(n-1:0)
sel
sel y
0 a
1 b
library IEEE;use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) );end mux2g;
An n-line 2 x 1 MUX
a(n-1:0)
b(n-1:0)
y(n-1:0)
sel
n-line2 x 1MUX
library IEEE;use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) );end mux2g;
Entity Each entity must begin with these library and use
statements
port statement defines inputs and outputs
generic statement defineswidth of bus
library IEEE;use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) );end mux2g;
Entity
Mode: in or out
Data type: STD_LOGIC,STD_LOGIC_VECTOR(width-1 downto 0);
Standard Logic
type std_ulogic is ( ‘U’, -- Uninitialized‘X’ -- Forcing unknown‘0’ -- Forcing zero‘1’ -- Forcing one‘Z’ -- High impedance‘W’ -- Weak unknown‘L’ -- Weak zero‘H’ -- Weak one‘-’); -- Don’t care
library IEEE;use IEEE.std_logic_1164.all;
Standard Logic
Type std_ulogic is unresolved.
Resolved signals provide a mechanismfor handling the problem of multipleoutput signals connected to one signal.
subtype std_logic is resolved std_ulogic;
architecture mux2g_arch of mux2g isbegin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1;end mux2g_arch;
Architecture
a(n-1:0)
b(n-1:0)
y(n-1:0)
sel
n-line2 x 1MUX
Note: <= is signal assignment
architecture mux2g_arch of mux2g isbegin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1;end mux2g_arch;
Architecture entity name
process sensitivity list
Sequential statements (if…then…else) must
be in a process
Note begin…end
in processNote begin…end
in architecture
Digilab2 – DIO1 Boards
Spartan IIFPGA
8 LEDsLD
8 SwitchesSW4 Pushbuttons
BTN
Four 7-segmentdisplays
Pushbuttonbn
74HC373 latch ldg <= ‘1’
Top-level Design – Lab 1
a(3:0)
b(3:0)
mux2g
Lab1
sel
ySW(1:4)
SW(5:8)
LD(1:4)
BTN4
ldg‘1’
library IEEE;use IEEE.std_logic_1164.all; entity lab1 is port ( SW: in STD_LOGIC_VECTOR (1 to 8); BTN4: in STD_LOGIC;
ldg: out STD_LOGIC; LD: out STD_LOGIC_VECTOR (1 to 4) );end lab1;
a(3:0)
b(3:0)
mux2g
Lab1
sel
ySW(1:4)
SW(5:8)
LD(1:4)
BTN4
ldg‘1’
architecture lab1_arch of lab1 is component mux2g generic(width:positive); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR (width-1 downto 0) );end component; constant bus_width: positive := 4; begin ldg <= '1'; -- enable 74HC373 latch SWmux: mux2g generic map(width => bus_width) port map (a => SW(1 to 4), b => SW(5 to 8), sel => BTN4, y => LD); end lab1_arch;
a(3:0)
b(3:0)
mux2g
Lab1
sel
ySW(1:4)
SW(5:8)
LD(1:4)
BTN4
ldg‘1’
An n-line 4 x 1 multiplexer
a(n-1:0)
b(n-1 :0)y(n-1 :0)
sel(1:0)
8-line4 x 1MUXc(n-1 :0)
d(n-1 :0)
Sel y
“00” a
“01” b
“10” c
“11” d
An 8-line 4 x 1 multiplexer
library IEEE;use IEEE.std_logic_1164.all; entity mux4g is
generic(width:positive); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); c: in STD_LOGIC_VECTOR (width-1 downto 0); d: in STD_LOGIC_VECTOR (width-1 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (width-1 downto 0) );end mux4g;
Example of case statement
architecture mux4g_arch of mux4g isbegin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case; end process;end mux4g_arch; Must include ALL posibilities
in case statement
Note implies operator =>
Sel y
“00” a
“01” b
“10” c
“11” d
VHDL Architecture Structurearchitecture name_arch of name is
begin
end name_arch;
Signal assignments
Concurrent statements
Concurrent statements
Process 1
Process 2
Concurrent statements
Processes contain sequential
statements, but execute
concurrently within the
architecture body
VHDL Process
P1: process (<sensitivity list)<variable declarations>begin <sequential statements>end process P1;
Optional process label
Within a process:
Variables are assigned using :=
and are updated immediately.
Signals are assigned using <=
and are updated at the end of
the process.
Multiplexers
• Multiplexers (Selectors)
• Lab 1 – Behavioral VHDL -- Multiplexers
• MUX as a Universal Element
Multiplexer as universal combinational module
• connect input variables x to select inputs of multiplexer s
• set data inputs to multiplexer equal to values of function for corresponding assignment of select variables
• using a variable at data inputs reduces size of the multiplexer
Implementing a Boolean Function with a Multiplexer
Implementing a Four- Input Function with a Multiplexer
Networks with 2-input multiplexers
Implementation of SFs with network of MUXes
Design of networks with MUXes
Example
Ordering of variables in subtrees affects the number of MUXes
Example of Shannon’s Decomposition
F = x3(x1 + x2x0)
Implemented using a multiplexer network
F = x3(x1 + x2x0)
Start with any variable - x0 for example
x0 = 0
x0 = 1
F = x3x1
F = x3(x1 + x2)
F = x3(x1 + x2x0)
Then x! for example
x0 = 0
x0 = 1
F = x3x1
F = x3(x1 + x2)
x1 = 0
x1 = 1
F = 0
F = x3
x1 = 0
x1 = 1
F = x3x2
F = x3
F = x3(x1 + x2x0)
Then x2 for example
x0 = 0
x0 = 1
F = x3x1
F = x3(x1 + x2)
x1 = 0
x1 = 1
F = 0
F = x3
x1 = 0
x1 = 1
F = x3x2
F = x3
x2 = 0
x2 = 1
F = 0
F = x3
F = x3(x1 + x2x0)
x0 = 0
x0 = 1
F = x3x1
F = x3(x1 + x2)
x1 = 0
x1 = 1
F = 0
F = x3
x1 = 0
x1 = 1
F = x3x2
F = x3
x2 = 0
x2 = 1
F = 0
F = x3
Inputs
F = x3(x1 + x2x0)
x0 = 0
x0 = 1
F = x3x1
F = x3(x1 + x2)
x1 = 0
x1 = 1
F = 0
F = x3
x1 = 0
x1 = 1
F = x3x2
F = x3
x2 = 0
x2 = 1
F = 0
F = x3
MUX Select Lines
x1 = 0x0 = 0
x0 = 1
F = x3x1
F = x3(x1 + x2)
x1 = 1
F = 0
F = x3
x1 = 0
x1 = 1
F = x3x2
F = x3
x2 = 0
x2 = 1
F = 0
F = x3
1
0
sel
x3x1
x3(x1 + x2) x0
F
x1 = 0x0 = 0
x0 = 1
F = x3x1
F = x3(x1 + x2)
x1 = 1
F = 0
F = x3
x1 = 0
x1 = 1
F = x3x2
F = x3
x2 = 0
x2 = 1
F = 0
F = x3
x3x1
1
0
sel
x3(x1 + x2)
1
0
sel
x0
x1
0
x3
The branch for x0 = 0F
x1 = 0x0 = 0
x0 = 1
F = x3x1
F = x3(x1 + x2)
x1 = 1
F = 0
F = x3
x1 = 0
x1 = 1
F = x3x2
F = x3
x2 = 0
x2 = 1
F = 0
F = x3
x3x1
1
0
sel
x3(x1 + x2)
1
0
sel
x0
x1
0
x3
1
0
sel
x1
x3x2
x3
The branch for x0 = 1
F
x1 = 0x0 = 0
x0 = 1
F = x3x1
F = x3(x1 + x2)
x1 = 1
F = 0
F = x3
x1 = 0
x1 = 1
F = x3x2
F = x3
x2 = 0
x2 = 1
F = 0
F = x3
x3x1
1
0
sel
x3(x1 + x2)
1
0
sel
x0
x1
0
x3
1
0
sel
x1
x3x2
x3
The branch for x1 = 0
1
0
sel
x2
x3
0F
F = x3(x1 + x2x0)
• Starting with x0• Shannon’s Decomposition
• 4 Multiplexers
1
0
sel
1
0
sel
x0
x1
0
x3
1
0
sel
x1
x3
1
0
sel
x2
x3
0F
F = x3(x1 + x2x0)
• Starting with x1• Shannon’s Decomposition
• 3 Multiplexers
1
0
sel
1
0
sel
x1
x0
0
1
0
sel
x2
x3F
x3
0
16-input tree multiplexer