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Lecture 8 Transistors and CMOS Topics Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. Readings 3. September 25, 2003 CSCE 211 Digital Design

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Page 1: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

Lecture 8Transistors and CMOS

Lecture 8Transistors and CMOS

TopicsTopics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers

Readings 3.Readings 3.

September 25, 2003

CSCE 211 Digital Design

Page 2: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 2 – CSCE 211H Fall 2003

OverviewOverview

Last TimeLast Time Lab 3 – VHDL Lab 3 Deliverables:

NewNew Encoders/Priority Encoders Transistors CMOS gates Review for test

HistoryHistory Invention of transistor

Page 3: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 3 – CSCE 211H Fall 2003

Honors College: Advisement Honors College: Advisement

Appointment Sign-up begins Appointment Sign-up begins Wednesday October 1 8:00AM Outside main office 2nd floor Harper

Advisement begins Monday October 6Advisement begins Monday October 6

CSCE Classes (lower level)CSCE Classes (lower level) CSCE 145 MW 2:30-3:45 Fuchs CSCE 146 TTH 9:30-10:45 Bowles CSCE 212H TTH 12:30-1:45 Matthews CSCE 240 MWF 9:05-9:55 Fuchs CSCE 245 MW 4:00-5:15

Page 4: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 4 – CSCE 211H Fall 2003

Lab 3 DeliverablesLab 3 Deliverables

1.1. VHDL for 74LS47’ where the ’ means don’t care for VHDL for 74LS47’ where the ’ means don’t care for 10 … 15 using functions given in class (slide )10 … 15 using functions given in class (slide )

2.2. Schematic using components (symbols) made for Schematic using components (symbols) made for 74LS47 and 74LS153 (Mux). Add output ports to 74LS47 and 74LS153 (Mux). Add output ports to outputs of 74LS47 and label them with the pin outputs of 74LS47 and label them with the pin numbers for your seven segment display digit. The numbers for your seven segment display digit. The input ports should also be labeled. input ports should also be labeled.

3.3. Circuit for selecting one base-4 number with a mux Circuit for selecting one base-4 number with a mux and displaying it on the even segment display.and displaying it on the even segment display. You must use the DIP switch to set the input of four base-4

numbers. The select line inputs will be just wires.

Page 5: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 5 – CSCE 211H Fall 2003

Hot BatteriesHot Batteries

You should regularly check your batteries “slightly You should regularly check your batteries “slightly warm” is OK but hot indicates that your circuit has a warm” is OK but hot indicates that your circuit has a short circuit.short circuit.

Unplug quickly and check.Unplug quickly and check.1. Look for direct lines Vcc to GND.

2. Remember you need 330 ohm resistors in series with LEDs and that includes segments of the seven segment display.

3. Recheck sections of the breadboard.

Page 6: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 6 – CSCE 211H Fall 2003

Functions for 74LS47 with don’t caresFunctions for 74LS47 with don’t caresa(D,C,B,A) = D + Aa(D,C,B,A) = D + A..C + AC + A..B + A’B + A’..C’ C’

b(D,C,B,A) = D + (D'*C') + (A'*B') + (A*B) (aj)b(D,C,B,A) = D + (D'*C') + (A'*B') + (A*B) (aj)

c <= a or not b or d c <= a or not b or d (david)(david)

d = d =

e = A(bar) and (B or C(bar)) e = A(bar) and (B or C(bar)) (jeremy/patrick) (jeremy/patrick)

f = D + A'B' + B'C + A'BC f = D + A'B' + B'C + A'BC (jon)(jon)

g=D + B'C + C'B + A'B g=D + B'C + C'B + A'B (msbell)(msbell)

Page 7: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 7 – CSCE 211H Fall 2003

Karnaugh Map SimplificationKarnaugh Map SimplificationOn a real 74LS47 the outputs for 10, …15 are not don’t cares.On a real 74LS47 the outputs for 10, …15 are not don’t cares.

They would indicate errors in BCD input. We could use the period for that. They would indicate errors in BCD input. We could use the period for that.

period(D,C,B,A)=SUM( )period(D,C,B,A)=SUM( )

dc(D,C,B,A) = SUM( )dc(D,C,B,A) = SUM( )

BADC 00 01 11 10

00

01

11

10

A

D

C

B

period(D,C,B,A) =period(D,C,B,A) =

Page 8: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 8 – CSCE 211H Fall 2003

TransistorsTransistors

HistoryHistory

1790s Ben Franklin “assigns” negative charge to 1790s Ben Franklin “assigns” negative charge to electronselectrons

1898 Thompson discovers the electron1898 Thompson discovers the electron

1947 Shockley, Bardeen and Brattain “invent” 1947 Shockley, Bardeen and Brattain “invent” transistortransistor

1958 first Integrated Circuit, Texas Instruments1958 first Integrated Circuit, Texas Instruments

1971 Intel 4004, microprocessor, Ted Hoff1971 Intel 4004, microprocessor, Ted Hoff

TimelineTimeline

http://www.pbs.org/transistor/http://www.pbs.org/transistor/

Page 9: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 9 – CSCE 211H Fall 2003

Transistor: Water Flow ModelTransistor: Water Flow ModelWater flow in B raises the plunger so that water can flow from C to E.

Small flow turns on and off bigger flow.

Put signal on B, transfer signal C to E

Reference: http://www.satcure-focus.com/tutor/page4.htm

Page 10: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 10 – CSCE 211H Fall 2003

Transistor TerminologyTransistor Terminology

Conductor – electrons easily passed from one atom to Conductor – electrons easily passed from one atom to next (copper every atom has loose electron)next (copper every atom has loose electron)

Insulator – electrons tightly tied down to atoms, no flowInsulator – electrons tightly tied down to atoms, no flow

Semiconductor – by adding impurities (doping) can be Semiconductor – by adding impurities (doping) can be changed to increase conductivitychanged to increase conductivity

Silicon wafer – used for IC circuitsSilicon wafer – used for IC circuits

N-type - silicon doped with boron (excess electrons)N-type - silicon doped with boron (excess electrons)

P-ype - silicon doped with phosphorous (excess P-ype - silicon doped with phosphorous (excess “holes” lack of electrons)“holes” lack of electrons)

Page 11: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 11 – CSCE 211H Fall 2003

TransistorTransistor

Reference: http://www.intel.com/education/transworks/

Page 12: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 12 – CSCE 211H Fall 2003

TransistorTransistor

Reference: http://www.intel.com/education/transworks/

Page 13: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 13 – CSCE 211H Fall 2003

TransistorTransistor

Reference: http://www.intel.com/education/transworks/

Put Positive charge on gate.

This attracts electrons into gap.

This allows electrons to pass freely through the gap.

Page 14: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 14 – CSCE 211H Fall 2003

TransistorTransistor

Reference: http://www.intel.com/education/transworks/

Page 15: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 15 – CSCE 211H Fall 2003

TransistorTransistor

Reference: http://www.intel.com/education/transworks/

Take positive charge offGate

This stops attractingelectrons.

This shuts off the flow.

Page 16: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 16 – CSCE 211H Fall 2003

N channel transitorN channel transitor

Page 17: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 17 – CSCE 211H Fall 2003

P channel TransistorP channel Transistor

Page 18: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 18 – CSCE 211H Fall 2003

CMOS InverterCMOS Inverter

Page 19: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 19 – CSCE 211H Fall 2003

CMOS NANDCMOS NAND

Page 20: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 20 – CSCE 211H Fall 2003

What’s This?What’s This?

Page 21: Lecture 8 Transistors and CMOS Topics Combinational Circuits Quiz Structural VHDL Lab 2 VHDL: Decoders, Multiplexers Demultiplexers Readings 3. September

– 21 – CSCE 211H Fall 2003

Test / Sample TestTest / Sample Test