cd4051b-q1, cd4052b-q1, cd4053b-q1 cmos ?· cd4051b-q1, cd4052b-q1, cd4053b-q1 cmos analog...

Download CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ?· cd4051b-q1, cd4052b-q1, cd4053b-q1 cmos analog multiplexers/demultiplexers…

Post on 05-Jun-2018

212 views

Category:

Documents

0 download

Embed Size (px)

TRANSCRIPT

  • CD4051B-Q1, CD4052B-Q1, CD4053B-Q1CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS

    WITH LOGICLEVEL CONVERSIONSCHS354A AUGUST 2004 REVISED JANUARY 2008

    1POST OFFICE BOX 655303 DALLAS, TEXAS 75265

    Features

    Qualified for Automotive Applications

    Wide Range of Digital and Analog SignalLevels Digital: 3 V to 20 V Analog: 20 VP-P

    Low ON Resistance, 125 (Typ) Over 15 VP-P Signal Input Range for VDD VEE = 18 V

    High OFF Resistance, Channel Leakage of100 pA (Typ) at VDD VEE = 18 V

    Logic-Level Conversion for DigitalAddressing Signals of 3 V to 20 V (VDD VSS = 3 V to 20 V) to Switch AnalogSignals to 20 VP-P (VDD VEE = 20 V)

    Matched Switching Characteristics, ron = 5 (Typ) for VDD VEE = 15 V

    Very Low Quiescent Power DissipationUnder All Digital-Control Input and SupplyConditions, 0.2 W (Typ) at VDD VSS = VDD VEE = 10 V

    Binary Address Decoding on Chip

    5-V, 10-V, and 15-V Parametric Ratings

    100% Tested for Quiescent Current at 20 V

    Maximum Input Current of 1A at 18 V OverFull Package Temperature Range, 100 nA at18 V and 25C

    Break-Before-Make Switching EliminatesChannel Overlap

    Applications

    Analog and Digital Multiplexing andDemultiplexing

    Analog-to-Digital (A/D) andDigital-to-Analog (D/A) Conversion

    Signal Gating

    description/ordering information

    The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches that havelow ON impedance and very low OFF leakage current. Control of analog signals up to 20 VP-P can be achievedby digital signal amplitudes of 4.5 V to 20 V (If VDD VSS = 3 V, a VDD VEE of up to 13 V can be controlled;for VDD VEE level differences above 13 V, a VDD VSS of at least 4.5 V is required). For example, if VDD = 4.5 V, VSS = 0 V, and VEE = 13.5 V, analog signals from 13.5 V to 4.5 V can be controlled by digitalinputs of 0 V to 5 V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD VSSand VDD VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic high(H) is present at the inhibit (INH) input, all channels are off.

    ORDERING INFORMATION

    TA PACKAGEORDERABLE

    PART NUMBERTOP-SIDEMARKING

    SOIC M Reel of 2500 CD4051BQM96Q1 CD4051Q

    TSSOP PW Reel of 2000 CD4051BQPWRQ1 CM051BQ

    40C to 125CSOIC M Reel of 2500 CD4052BQM96Q1 CD4052Q

    40C to 125CTSSOP PW Reel of 2000 CD4052BQPWRQ1 CD4052Q

    SOIC M Reel of 2500 CD4053BQM96Q1 CD4053Q

    TSSOP PW Reel of 2000 CD4053BQPWRQ1 CD4053Q

    For the most current package and ordering information, see the Package Option Addendum at the end of thisdocument, or see the TI web site at http://www.ti.com.

    Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. Product Preview

    Copyright 2008, Texas Instruments IncorporatedUNLESS OTHERWISE NOTED this document contains PRODUCTIONDATA information current as of publication date. Products conform tospecifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of allparameters.

    Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

  • CD4051B-Q1, CD4052B-Q1, CD4053B-Q1CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERSWITH LOGICLEVEL CONVERSIONSCHS354A AUGUST 2004 REVISED JANUARY 2008

    2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

    description/ordering information (continued)

    The CD4051B is a single eight-channel multiplexer that has three binary control inputs (A, B, and C) and aninhibit input. The three binary signals select one of eight channels to be turned on and connect one of the eightinputs to the output.

    The CD4052B is a differential four-channel multiplexer that has two binary control inputs (A and B) and an inhibitinput. The two binary input signals select one of four pairs of channels to be turned on and connect the analoginputs to the outputs.

    The CD4053B is a triple two-channel multiplexer with three separate digital control inputs (A, B, and C) and aninhibit input. Each control input selects one of a pair of channels, which are connected in a single-pole,double-throw configuration.

    When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs, and thecommon (COM OUT/IN) terminals are the inputs.

    CD4053M OR PW PACKAGE

    (TOP VIEW)

    1

    2

    3

    4

    5

    6

    7

    8

    16

    15

    14

    13

    12

    11

    10

    9

    IN/OUT byIN/OUT bxIN/OUT cy

    OUT/IN CX OR CYIN/OUT CX

    INHVEEVSS

    VDDOUT/IN bx or byOUT/IN ax or ayIN/OUT ayIN/OUT axABC

    CD4051M OR PW PACKAGE

    (TOP VIEW)

    1

    2

    3

    4

    5

    6

    7

    8

    16

    15

    14

    13

    12

    11

    10

    9

    CHANNEL I/O 4CHANNEL I/O 6

    COM OUT/INCHANNEL I/O 7CHANNEL I/O 5

    INHVEEVSS

    VDDCHANNEL I/O 2CHANNEL I/O 1CHANNEL I/O 0CHANNEL I/O 3ABC

    CD4052M OR PW PACKAGE

    (TOP VIEW)

    1

    2

    3

    4

    5

    6

    7

    8

    16

    15

    14

    13

    12

    11

    10

    9

    Y CHANNEL I/O 0Y CHANNEL I/O 2

    COM Y OUT/INY CHANNEL I/O 3Y CHANNEL I/O 1

    INHVEEVSS

    VDDX CHANNEL I/O 2X CHANNEL I/O 1COM X OUT/INX CHANNEL I/O 0X CHANNEL I/O 3AB

  • CD4051B-Q1, CD4052B-Q1, CD4053B-Q1CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS

    WITH LOGICLEVEL CONVERSIONSCHS354A AUGUST 2004 REVISED JANUARY 2008

    3POST OFFICE BOX 655303 DALLAS, TEXAS 75265

    Function Tables

    CD4051

    INPUTS ONINH C B A

    ONCHANNEL

    L L L L 0

    L L L H 1

    L L H L 2

    L L H H 3

    L H L L 4

    L H L H 5

    L H H L 6

    L H H H 7

    H X X X None

    X = dont care

    CD4052

    INPUTS ONINH B A

    ONCHANNEL

    L L L 0x, 0y

    L L H 1x, 2y

    L H L 2x, 2y

    L H H 3x, 3y

    H X X None

    X = dont care

    CD4053

    INPUTS ONINH A OR B OR C

    ONCHANNEL

    L L ax or bx or cx

    L H ay or by or cy

    H X None

    X = dont care

  • CD4051B-Q1, CD4052B-Q1, CD4053B-Q1CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERSWITH LOGICLEVEL CONVERSIONSCHS354A AUGUST 2004 REVISED JANUARY 2008

    4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

    logic diagram (positive logic)

    All inputs are protected by CMOS protection network.

    11

    10

    9

    6

    A

    B

    C

    INH

    134 2 5 1 12 15 14

    TG

    TG

    TG

    TG

    TG

    TG

    TG

    TG

    3 COMOUT/IN

    01234567

    8 7

    16

    CHANNEL I/O

    CD4051B

    Logic-LevelConversion

    Binaryto

    1-of-8Decoder

    WithInhibit

    VDD

    VSS VEE

    All inputs are protected by CMOS protection network.

    CD4052B

    1211 15 14

    0123

    3210

    X CHANNEL I/O

    Y CHANNEL I/O

    13

    3

    78

    16

    6

    9

    10A

    B

    INH

    TG

    TG

    TG

    TG

    TG

    TG

    TG

    TG

    4251

    Binaryto

    1-of-4Decoder

    WithInhibit

    COM XOUT/IN

    Logic-LevelConversion

    VDD

    VSS VEE

    COM YOUT/IN

  • CD4051B-Q1, CD4052B-Q1, CD4053B-Q1CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS

    WITH LOGICLEVEL CONVERSIONSCHS354A AUGUST 2004 REVISED JANUARY 2008

    5POST OFFICE BOX 655303 DALLAS, TEXAS 75265

    logic diagrams (positive logic) (continued)

    11

    10

    9

    6

    A

    B

    C

    INH

    123 5 1 2 13

    TG

    TG

    TG

    TG

    TG

    TG

    4

    axaybxbycxcy

    8 7

    16IN/OUT

    15

    14

    VDD

    All inputs are protected by standard CMOS protection network.

    CD4053B

    Logic-LevelConversion

    VDD

    VSS VEE

    Binary to1-of-2

    DecodersWith

    Inhibit

    COM OUT/INac or ay

    COM OUT/INbc or by

    COM OUT/INxc or xy

    absolute maximum ratings over operating free-air temperature (unless otherwise noted)

    Supply voltage range, V+ to V (voltages referenced to VSS terminal) 0.5 to 20 V. . . . . . . . . . . . . . . . . . . . . . DC input voltage range 0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC input current, any one input 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, JA (see Note 1): M package 73C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    PW package 108C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum junction temperature, TJ 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature (during soldering):

    At distance 1/16 1/32 inch (1,59 0,79 mm) from case for 10 s max 265C. . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg 65C to 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

    NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.

  • CD4051B-Q1, C

Recommended

View more >