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ENEE 359a: Digital VLSI Design
—
Midterm Exam (20%)
1
This exam should take you less than an hour: 5 questions, 10 minutes apiece. The exam is closedbook, closed notes.
Note that each question is worth the same number of points; this means you should do those questions you find easy first.
Name: ______________________________________________________
Score:
Problem 1: out of 4
Problem 2: out of 4
Problem 3: out of 4
Problem 4: out of 4
Problem 5: out of 4
Total:
Midterm Exam (20%)
ENEE 359a: Digital VLSI Design, Spring 2007The Ides of Mar ch, Opening Round of the NCAA Tournament
Solutions
Grade Distrib ution:
20 - X X
19 - X X X X
18 - X X X
17 -
16 - X
15 - X X X
14 -
13 - X
12 -
11 -
10 -
9 - X
ENEE 359a: Digital VLSI Design
—
Midterm Exam (20%)
2
1. Consider the f ollo wing stic k dia gram. Draw the electricall y equiv alent transistor -level schematic. What logic equation does the cir cuit implement?
VDD
GND
A B C D
green
red (pol y)
OUT
(active)
E
VDD
E
A
D
B
C
A B
C D
E
OUT
solution:
out = ~(DE + C(A+B))
out = ~(DE + CA + CB)
ENEE 359a: Digital VLSI Design
—
Midterm Exam (20%)
3
2. Consider the logical e xpression
out = ~( ab + cd )
.
Conver t this to a sc hematic dia gram f or static CMOS logic, then con ver t it to a stic k-dia gram la yout (as in question 1).
VDD
DC
OUT
BA
C
D
B
A
VDD
GND
A B C D
OUT
some equivalent solutions (there is more than one correct answer):
VDD
BA
OUT
DC
D
C
A
B
VDD
GND
A B C D
OUT
ENEE 359a: Digital VLSI Design
—
Midterm Exam (20%)
4
3. Provide a side-vie w dia gram f or eac h of the cuts X and Y thr ough the la yout belo w. Be sure to label eac h of the strata. Label y our endpoints f or the X cut, so it is c lear whic h end is whic h.
poly
metal
active
well
via
GND
VDD
a
b
OUT
n-well
X
1
Y
X
2
solution:
X1 X2
M1 M1 M1 M1 M1
poly (a)poly poly(b) (a)
n-well
p+ p+ p+
gate oxide
Y
M1 (out)
n+
(gnd) (out) (a) (out) (vdd)
p-type wafer
n+
poly(a)
poly(b)
p-type wafer
ENEE 359a: Digital VLSI Design
—
Midterm Exam (20%)
5
4. Consider the function
out = ~( (a + bc) • d )
. Draw the cir cuit and siz e the transistor s: size all NMOS and PMOS transistor s so that the PUN and PDN eac h has equiv alent resistance to a minim um-siz ed MOSFET, and then take into account the fact that µ
n
=
r •
µ
p
where
r
= 2.5 (i.e. the resistance of a unit PMOS de vice is 2.5 times
that of a unit NMOS de vice).
Impor tant:
Assume the circuit is implemented in a 60nm technology and that the dimensions of a
minim um-siz ed MOSFET
in this technology are
90nm width x 60nm length
. Express the dimensions of each MOSFET in the optimized circuit in nanometers (W nm x L nm). I.e., what is it that you are scaling?
VDD
CB
OUT
C
B
A
D
D
A
some equivalent solutions (there is more than one correct answer):
VDD
CB
OUT
C
B
AD
D
A
2 • 2.5x (5x)
450nm x 60nm
min. device: WxL = 90nm x 60nm
4x
360nm x 60nm
2x
180nm x 60nm
2.5x
225nm x 60nm
2 • 2.5x (5x)
450nm x 60nm
2.5x
225nm x 60nm
3x
270nm x 60nm
≥
1.5x
≥
135nm x 60nm
ENEE 359a: Digital VLSI Design
—
Midterm Exam (20%)
6
5. You ha ve identifi ed a critical path thr ough a cir cuit, as sho wn belo w. Consider the path up to the ja gged line; the 2-input NAND be yond simpl y represents the load being driven (it can be thought of as the input to a D-latc h, for example). That NAND has been scaled b y a factor of 7
3
÷ 5
3
whic h can be appr oximated b y the v alue 2.8. Thus, the load NAND has C
nand
appr oximatel y equal to 3.5 C
in
. Find the scaling terms s
i
for eac h gate and the optimiz ed path delay. Assume that gamma=1, that r=3, and that the p
i
terms are all equal (lea ve as “p”).
Equations y ou might fi nd useful:
C
in
=1
s
nand
7
3
5
3
------=
C
nand
s
nand
•
g
nand
=
Sizing for gate i
g
1
s
1
g
i
----------
f
j
b
j
-----
j
1=
i
1–
∏
=
Optimal gate effort h
GFB
N
H
N
= = Delay through path
t
p0
p
i
f
i
g
i
γ
---------+
∑
=
Optimal delay
t
p0
p
i
N H
N
γ
---------------+
∑
=
g
nor
1
nr
+1
r
+---------------=
g
nand
n r
+1
r
+-----------=
f
i,opt
hg
i
----=
FC
load
C
in
------------=
G g
ii
∏
=
solution:
#1 #2 #3 #4 #5
g
1
=1 g
2
=5/4 g
3
=7/4 g
4
=7/4 g
5
=5/4
n=2 n=4 n=2 n=2
r=3
g
L
=5/4
C
L
=7
3
/5
3
• 5/4
h GFB
N
154--- 7
4--- 7
4--- 5
4---
⋅ ⋅ ⋅ ⋅
7
3
5
⋅
5
3
4
⋅
------------
⋅
5
7
5
5
3
⋅
5
3
4
5
⋅
---------------
5
74---= = = =
=7/4 =7/5 =1 =1 =7/5
f
1
7 4
⁄
1----------=
f
2
7 4
⁄
5 4
⁄
----------=
f
3
7 4
⁄
7 4
⁄
----------=
f
4
7 4
⁄
7 4
⁄
----------=
f
5
7 4
⁄
5 4
⁄
----------=
f
i
hg
i
----=
s
1
1=
s
2
15 4
⁄
---------- 74---
⋅
=
s
3
17 4
⁄
---------- 74--- 7
5---
⋅ ⋅
=
s
4
17 4
⁄
---------- 74--- 7
5--- 1
⋅ ⋅ ⋅
=
s
5
15 4
⁄
---------- 74--- 7
5--- 1 1
⋅ ⋅ ⋅ ⋅
=
= 7/5 = 7/5 = 7/5 = 49/25
≈≈≈≈
2
Delay
t
p0
p
i
N H
N
γ
---------------+
∑
t
p0
5
p
354------+
= =
n=2