low power system-on-chip design chapter 5:chapter 5 · 1 low power system-on-chip design chapter...

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Low Power System-On-Chip DesignChapter 5:Chapter 5:

Designing Power Gating

Ismo Hänninen

Institute of Digital and Computer Systems / TKT-9636Department of Computer Systems / TKT-9626Department of Computer Systems / TKT-9626 Ch5: Designing Power Gating 11/12/2008

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Chapter 5 : Designing Power Gatingp g g g

Overview

Design Aspects from Front-End Perspective (RTL)g p p ( )Switching FabricSignal IsolationState Retention and RestorationPower Gating Control

Design Verification – RTL LevelDesign For Test – Challenges

Institute of Digital and Computer Systems / TKT-9636Department of Computer Systems / TKT-9626 Ch5: Designing Power Gating 11/12/2008

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Power Gating Overview

Institute of Digital and Computer Systems / TKT-9636Department of Computer Systems / TKT-9626 Ch5: Designing Power Gating 12.11.2008

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Power Gating Overviewg

Turning off functional blocks to save leakage powerInvasive method, affecting inter-block communication⇒ Much design effort needed (no automation exists, yet)g ( , y )


Source: Keating et al., “Low Power Methodology Manual”

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…Power Gating Overviewg

Typically internal power gating (vs. chip external switching)System-on-Chip with power gating:



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Switching Fabric DesignS tc g ab c es gCutting the Power (Aspect 1/4)


Switching Fabric Design7

g g

Cutting the power circuit from either VDD or VSS sideFine-grained (Fig. 4-5, p. 39) or coarse grainedHeader or footer type switch (usually not both)yp ( y )

Depends on the design, which one is better approach



…Switching Fabric Design8

g g

Header-style switch:In power off, internal nodes and outputs collapse to VSS (ground)Recommended for external switches (off chip)Recommended for multiple power rails and voltage scaling

Footer-style switch:I ff i t l d d t t ll t VIn power off, internal nodes and outputs collapse to VDD

Switch electrical characteristics might be better (than in header-style)

C t lli th it hControlling the switchesLimit the in-rush current (use daisy-chaining, trickle switches)Technology specific controller needed


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Signal IsolationS g a so at oSecuring Outputs (Aspect 2/4)


Signal Isolation10

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Protecting next powered block from illegal output signalsCrowbar currents (electrical problem)Spurious behavior (functional problem)

Isolation cell clamps the output of powered-down block to a specified value (‘0’, ‘1’, last)

Gate-type clamp cells (AND, OR)Transistor-type clamp (pull-up, pull-down)



…Signal Isolation11

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Gate-type clamp (= simply logic)Easy/safe to useAdds a gate delayAdds area cost

Transistor-type clamps (= multiple drivers on a net)Glitches possible in power-up, needs careful sequencingFights the output values in power-upMetal migration and reliability problemsNot for portable RTL designNot for portable RTL design


…Signal Isolation12

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Interface and protocolsClamp in source block (recommended) or destination blockClamp to which value, depending on case (can both blocks be off)

Recommendation with header-type switching (cut VDD):Active high signalsActive low resetCl ll i l t ‘0’Clamp all signals to ‘0’



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State Retention and RestorationState ete t o a d esto at oRecovering from Power-Off (Aspect 3/4)


State Retention and Restoration14

Internal state of a block, after power off and back onRestore previous state (stored somewhere in power-off)Or build the state from reset

Three implementation approaches:CPU and software, reading and writing state registersScan chains to store state off chipRetention registers (instead of standard registers)

Software approach is slow and has non-deterministic timing (and the software is not reusable, but tightly coupled to the specific hardware)


…State Retention and Restoration15

S h i b d hScan chain based approachRe-uses manufacturing test hardware, no additional area overheadDedicated set of scan chains assigned for the power gated blockState is stored in memory outside the block, enabling complete power-down of the block

Scan chain approach is challenging to design on RTLFlops are inserted in synthesis stageNumber of registers and length of chains known after synthesisCoding and debugging done on RTL level, before synthesis(Conditional RTL code for emulating the behavior, and afterwards, also gate level netlist simulation to ensure correct wiring and length)




Retention register approachSaving and restoring value of runtime register, using a shadow register to store data in low power modePart of the block has to stay always powered on (shadow register)Part of the block has to stay always powered-on (shadow register)Area overhead typically 20%-50%Control complexity




Retention register controllerExplicit sequencing of save and restoreHandling slow shadow register correctly

Retention register approach is largely transparent to RTLWhen clock and reset are not active, during save and restoreAutomatic tool could replace standard registers, and wire up controls

Partial retention is possible, for example:Storing only shallow state (usually drawn as state machine)Resetting deep state (memories, counters, FIFOs)


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Power Gating Controlo e Gat g Co t oSequencing the Power (Aspect 4/4)


Power Gating Control19

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Controlling the power down and power up sequencing (of switching fabric, signal isolation, and retention)

Sequencing without retention:



g gy

…Power Gating Control20

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Sequencing with retention:



…Power Gating Control21

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Power gating takes timeSwitching fabric designed to limit voltage spikesNeed for control delays, or power-on acknowledge handshake

Sequencing with acknowledge:



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Design Verification – RTL Level


Design Verification – RTL Level23

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Hardware description languages (HDLs) do not directly support describing power connections on RTL level

Unified Power Format (UPF) standard defines language and i l ti ti hi h i l t l d tsimulation semantics, which some simulators already support

Or some scripting/manual power functionality description needed

K i l ti i t f tiKey simulation requirements of power gating:Functional modeling of power gating (forcing X outputs in power-off)Functional modeling of signal isolationFunctional modeling of save and restore internal stateFunctional modeling of save and restore internal stateFunctional modeling of precedence of gating/retention/reset


…Design Verification – RTL Level24

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Example system:UPF declaration:




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Example system:Emulation without UPF:




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Retention with UPF:

Retention without UPF:



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Design For Test - Challenges


Design For Test - Challenges28

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Power gating controlsExternal control/observation of gating, retention, and isolation signalsAll signals must be gated or muxed in test mode

Power limitations during scan testAll flops in a scan chain can toggle each clock cycle ⇒ High

i hi i i d d iswitching activity and dynamic powerPower-off control for unnecessary blocks from external pins

P i hi k l iPower switching network analog testingLacking power-off-on levels, timing failuresIDDQ tests, transition faults testingChecking corruption of retention registers (and other powered up)

Institute of Digital and Computer Systems / TKT-9636Department of Computer Systems / TKT-9626

Checking corruption of retention registers (and other powered-up)

Ch5: Designing Power Gating 12.11.2008

…Design For Test - Issues29

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Correct shutdown, isolation, and retention behaviorFunctional tests, repeated scan tests with varying clampingScan tests alternating ones and zeros for retention

Correct function of power gating controllerFunctional tests or with scanIsolating controller outputsExternal control of clock, reset, and power control signals


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Conclusion


Conclusion31

Power gating implemented with four components:

Switching FabricSwitching FabricSignal IsolationState Retention and RestorationPower Gating Control

Next topics:Architectural Issues for Power GatingA Power Gating Example



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