on-chip ecc for low-power sram design
DESCRIPTION
On-Chip ECC for Low-Power SRAM Design. Hsin-I Liu EE 241 Project 5/9/2005. Outline. Introduction to low-power SRAM Introduction on error correction code Analysis of data retention voltage in SRAM Simulations and results. V 2 (V). Low-Power SRAM. - PowerPoint PPT PresentationTRANSCRIPT
On-Chip ECC for Low-Power SRAM Design
Hsin-I LiuEE 241 Project
5/9/2005
5/9/2005 EE 241 Project
Outline Introduction to low-power SRAM Introduction on error correction
code Analysis of data retention voltage
in SRAM Simulations and results
5/9/2005 EE 241 Project
Low-Power SRAM Concept: Reduce the standby Vdd to data
retention voltage (DRV)
0 0.1 0.2 0.3 0.40
0.1
0.2
0.3
0.4
V1 (V)
V2 (
V)
VTC1
VTC2
VDD
=0.18V
VDD
=0.4V
VTC of SRAM cell inverters
V2
(V)
5/9/2005 EE 241 Project
Modeling DRV
0 40 80 1200
50
100
150
200
250
SRAM row
SR
AM
co
lum
n
100
150
200
250
300
350
100 200 300 4000
1000
2000
3000
4000
5000
6000
DRV (mV)
His
togr
am o
f 32K
SR
AM
cel
ls
SRAM Chip DRV
DRV is modeled as i.i.d. gamma random variable60mV+10mV (5,1)
i iDRV G
5
(5,1)0
1( )
!i x
ig x x e
i
5/9/2005 EE 241 Project
Error Correction Code Adding parity check into information Non-trivial binary code
Easy to encode Parameters fixed Hamming code, Golay code
Linear block code Parameters flexible Reed-Solomon code
Least parity overhead
k information symbols
n-k parity symbols
n symbols
5/9/2005 EE 241 Project
Applying ECC to SRAM Latency
In proportional to block size In this project: Hamming (15,11),
Golay(23,12), and RS(15,11) Implementation characteristics are
well-known
5/9/2005 EE 241 Project
Model Setup
Memory size: M× N
N columns
M ro
ws
ECC block size: ninfo length: i
r redundant rows
Row redundancy: r rowsStandby cycles: T
Metrics: 2 2 2
tan 0( ) /b s dby active
n M r codecE Vdd Vdd DRV
i M iT
b
codecO
i
n symbols
ECC
ECC
ECC
ECC
i info
5/9/2005 EE 241 Project
Model Analysis For certain standby voltage, retention
ability can be modeled as Bernoulli r.v.
For certain pe of a row, pe of a block can be derived
Inside a block, pe of each cell can be found by solving binomial distribution
Row redundancy can also be modeled as binomial r.v.
N columns
M ro
ws
r redundant rows
n symbols
ECC
ECC
ECC
ECCi info
5/9/2005 EE 241 Project
Results
0
50
100
150
200
250
0 200 400 600 800 1000 1200
# of cells in a row
Stan
dby
Volta
ge (m
V)
Hamming
RS
Golay
190
195
200
205
210
215
220
225
0 200 400 600 800 1000 1200 1400 1600
# of cells in a row
Stan
dby
Volta
ge Pe=1%
Pe=2%
Pe=5%
Pe=8%
Pe=10%
Pe=15%
5/9/2005 EE 241 Project
Results (cont.)
0%
5%
10%
15%
20%
25%
30%
0% 2% 4% 6% 8% 10% 12% 14% 16%
Pe in a row
Mem
ory
over
head
256
512
1024
5/9/2005 EE 241 Project
Results (cont.)
Number of columns
Standby Voltage (mV)
Hamming RS Golay
256201.36 194.78 176.36
512206.53 198.59 179.26
1024210.04 201.76 182.12
Hardware overhead (gates/bit)
9.091 22.727 58.333
5/9/2005 EE 241 Project
Conclusion Hamming code introduces the
least overhead For short waiting time, Hamming
code can reduce Eb from 50% to 2x As waiting time goes to infinity,
Reed-Solomon saves the power by 3x