on chip power amplifier design
TRANSCRIPT
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ON CHIPPOWER
AMPLIFIER
DESIGN
November 14
201
1
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CONTENTS
I. Introduction
II. Requirements of on chip power Amplifier
III. Power amplifier fundamentals
IV. On chip power amplifier design challenges
V. Choice of power amplifier
VI. Power amplifier implementation technology
VII. Conclusion
VIII. References
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ON CHIP POWER AMPLIFIER DESIGN
Anindita Dash
Kalinga Institute Of Industrial technology University, Bhubaneswar
School Of Electronics Engineering, 751024, India.
ABSTRACT
The tremendous growth of the wireless device is demanding Very LargeScale Integrated (VLSI) circuits with increasing functionality and performance
at reduced cost. VLSI circuits are being aggressively scaled to meet this
demand.
Hence the long term vision for wireless transceivers is to merge as
many components as possible to a single die in an inexpensive technology.
Therefore there is a growing interest in utilizing CMOS technologies for RF
power amplifiers. Because of supply voltage reduction due to CMOS
technology scaling and on chip passive losses due to the conductive substrateused in the CMOS process, on chip power amplifier is still among the most
difficult challenges for achieving a truly single chip radio system in CMOS. Todate, there has been relatively little research on the design of a CMOS PA
targeting good average efficiency. Linearity, efficiency are the key factors to
achieve cmos power amplifier (On Chip).
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I.INTRODUCTION
As technologies advance, todays savvy consumers demand wireless
systems that are low-cost, power efficient, reliable and have a small form-
factor. High level integration has been proven in practice to be an effective
way to reduce cost and achieve compactness simultaneously for high volume
applications. Hence the long term goal for wireless transceivers is to merge as
many components as possible, if not all, on to a single die using an
inexpensive technology. CMOS was first invented purely for digital integrated
circuits. Gradually CMOS became the predominant technology in digital
integrated circuits since its invention. This trend is essentially because
manufacturing cost, energy efficiency, operating speed and occupied area
have benefited and will continue to benefit from the dimension scaling of
CMOS devices that comes with every new technology generation. All the
features mentioned above have allowed for integration density not possible for
other technologies such as silicon bipolar technology. Besides, radio frequency
(RF) and microwave integrated circuits implemented in CMOS are making a
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strong appearance in the chip industry. It is believed that CMOS technology is
probably the only viable vehicle at present time to fulfill the dream of an
entire system on a single die at the present time.
II.Requirements of on chip power Amplifier
Driven by the demands from customers, continuing efforts have been taken to
look into fully integrated linear CMOS RF power amplifiers. Although there are
some previous publications on fully integrated RF PAs, they were implemented
with LDMOS transistors on a SOI substrate or with SiGe HBT transistors in a
SiGe BiCMOS technology and other exotic technologies. Without using power
combining techniques, reported fully integrated CMOS power amplifier with
55% drain efficiency could only achieve 85-mW power at 900-MHz or could
transmitter 150-mW at -1-dB compression point at 5-GHz but only with 13%
power added efficiency. If we could combine power from several efficient,
small power amplifiers, medium-to-high output power could be achieved with
good power efficiency.
Various methods have been used to split and combine RF signals. Among
them, transformers have been widely used as means for combining RF power.
However, one serious problem associated with conventional on-chip
transformers in CMOS technologies is high insertion loss which directlytranslates into loss in power efficiency. Therefore, this approach has only been
adopted to implement inter-stage matching. Circular geometry distributive
active transformer, known as DAT, was proposed to overcome high insertion
loss problem in on-chip transformers. It functions as an eight-way power
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combiner with good efficiency at peak output power, implemented with 0.35
m CMOS transistors. Despite many advantages of this approach, the circuit
geometry DAT still has some problems inherently from its structure.
Besides integration, there is another serious issue associated with PA design
which is inherent to conventional PA. It is well known that a PA can only
achieve maximum efficiency at peak output power. As output power
decreases, efficiency drops rapidly. However, the need to conserve battery
power and to mitigate interference to other users necessitates the
transmission of power levels well below the peak output power of the
transmitter. Moreover, since spectrum is a scarce commodity, modern
transmitters for wireless communications employ spectrally efficient digital
modulations with time varying envelope. Because of these reasons, the PA
transmits much lower than peak output power under typical operating
conditions.
III. Power amplifier fundamentals
The real world is analog in nature. PAs are used, ideally, to
amplify signals without compromising signal integrity, so that information
could be transmitted into the media and recovered by the recipient. PAs may
be categorized in several ways, depending on different criteria. Usually they
are classified according to their circuit configuration and operation conditions
into different classes, from class A to Class S.
An overview of classifications and specifications of PAs
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1.1 A, AB, B, and C power amplifiers
Figure 1.1: A generic topology for class-A, AB, B, and C power
amplifiers
These four types of power amplifiers have similar circuit configuration,
distinguished primarily by biasing conditions (Figure 2.1). A class-A power
amplifier, in principle, works as a small-signal amplifier. It is probably the only
true linear amplifier, since it amplifies over the entire input cycle such that
the output is an exact 16 scaled-up replica of the input without clipping. This
true linearity is obtained at the expense of wasting power. To improve
efficiency without sacrificing too much linearity, the concept of reduced
conduction angle was proposed. The idea is to bias the active devices5 with
low quiescent current and let the input RF signal to turn on active devices for
part of the cycle. As the conduction angle shrinks, the amplifier is biased from
class-AB, to class-B and eventually class-C. Regardless of conduction angle,
active devices are used as current sources. Therefore, they are often referred
to as transconductance PAs.
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Class-D power amplifiers
Figure 1.2: A voltage switching class-D amplifier
A class D amplifier is composed of a voltage controlled switch and a
filtering tank. Figure 1.2 shows a voltage switching class D amplifier. The
output tuned network is tuned to the fundamental frequency. It will thus
have negligible impedance at fundamental frequency and high impedance at
harmonic frequencies. The analysis of such an amplifier is very
straightforward due to the simple drain voltage waveform. In an ideal
situation, the drain efficiency of a class-D amplifier reaches 100% as other
switching type PAs.
1.3 Class-E power amplifiers
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Figure 1.3: A simple class-E amplifier
Class-E PA stands out from other highly efficient switching PAs
because parasitic capacitances of active devices may be absorbed into wave-
shaping/matching networks. A simplest form of class-E PAs is shown in Figure
1.3. During operation, the waveforms of drain current and voltage are shaped
such that they do not overlap. Furthermore, the voltage will decrease
gradually to zero before the active device turns on. This avoids
charging/discharging capacitors at the drain, thus improve efficiency.
However, the class-E PA has its disadvantage in terms of peak voltage.
1) Eff i c iency of PAs
One of the most important metrics for a power amplifier is its power
efficiency. It is a measure of how well a device converts one energy source
to another. What does not get converted is dissipated into heat which is
almost universally a bad product of energy conversion. In RF circuit design,
power amplifier efficiency is calculated in three ways with wide acceptance.
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The first one is drain efficiency, usually denoted as D. This is defined as the
ratio of output power POUT to DC power consumed from supply PSUPPLY.
Power added efficiency (PAE), denoted as PAE, is the most common used
measure which takes input power into account. It is calculated as the ratio of
the difference between output power POUT and input power PIN to DC power
consumed from supply PSUPPLY.
Total efficiency, denoted as TOTAL. It is calculated as the ratio of output
power POUT to the sum of input power PIN and DC power consumed from
supply PSUPPLY.
2) Linear ity of PAs
Besides efficiency, another inherent problem of power amplifiers is
linearity. All radio systems are required to induce the minimum possible
interference to other users. Hence, they must keep their transmissions within
the bandwidth allocated and maintain negligible energy leakage outside of the
band. If signals are distorted due to nonlinearities, unwanted distortion
products present to other users as interference. Furthermore, good linearity is
mandated in order to preserve the integrity of the information in transmitted
signals. Therefore, modulated signals could be recovered at the receiver end.
Because of the stringent requirement on linearity and the
desire to increase battery time, several linearization techniques have been
developed to enable linear systems with more efficient, but nonlinear or less
linear power amplifiers. As wireless communication evolve, it seems that a
standalone linear power amplifier cannot meet linearity requirements posed
by the next generation wireless systems. Therefore, some degree of
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linearization around the amplifier is necessary even if the amplifier itself is
linear. Feedback is probably the most obvious method to reduce distortion of
power amplifiers. The improvement on linearity is dependent on the loop gain
which could be quite expensive to obtain at RF frequencies. And stability is
also a concern because time-delay is not negligible at RF frequencies.
Cartesian loop and polar loop are two most popular feedback techniques.
To avoid problems with feedback at RF frequencies, feed forward
techniques have been proposed for linear power amplifiers. The input signal is
split into two paths, and then combined after amplification, such that wanted
signal are in-phase and distortions cancel out.
Predistortion is conceivably the simplest linearization technique, since it
is open-loop in nature. Nonlinearities of power amplifiers can be corrected at
the input of the amplifier by predistortion. The predistortion, in theory, will be
cancelled out by distortions of power amplifiers. An overall linear transfer
characteristic can thus be obtained. This technique was mainly used for base-
station because it was power hungry. With the scaling of CMOS, it becomes
practical to implement this technique on portable devices.
IV.On chip power amplifier design challenges
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A generic Power Amplifier MODEL
RF input signal drives the active device and causes it to modulate the load
network with periodic excitation.
This process draws energy from the power supply and delivers it to the load in
the form of an RF signal.
One of the most critical concerns in power amplifier delivers most of the
energy drawn from the supply to the load, where as an inefficient one
dissipates much energy as heat in the active device or in the lossy component
within the matching network.
Matching Network
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i. Impedance Transformation
To understand the significance of the impedance matching network, lets
consider a hypothetical but realistic situation in which a PA has to deliver a 1-
W sinusoidal signal into a 50W load. The peak voltage swing across the load in
this case will be 15
vout= Pout 2RL =10V
If the load were connected directly to the drain of the active device, then the
device drain would need to be biased at 10V supply. Since the transistor
output is inductively load and swings above supply, the device in this case will
have to withstand a peak voltage of 20V. This arrangement presents two
problems first, 10V supply voltage is rarely available in battery powered
consumer wireless devices; second and more importantly, the active device
may not even survive the high voltage without catastrophic breakdown
the breakdown limit for 0.35um CMOS, for example, is less than 6V, and it
gets even lower with more advanced CMOS technologies. The matching
network is therefore an essential component to deliver high output power
with limited voltage swing. Consisting of only reactive components, a
matching network is ideally lossless, and it transforms the load impedance to
a level manageable by the active device. This matching circuit is formed by a
simple L-C network and can match the load impedance RL down to an
impedance level equals to RL/ M, where M= (1 +RL2/X2 ) , Mis the matching
ratio.
With a lossless matching network, the input power equals to the power
delivered to the actual load impedance. However, the voltage swing at the
input port is now reduced by a factor of M due to the lowered input
impedance. In our previous example, if we choose M=16 , then the maximum
voltage appearing at the drain of the active device is reduced from 20V to 5V.
Notice that the maximum current conducted by the active
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device is also increased by a factor ofM, but this increased current handling
requirement can be easily overcome by using M devices in parallel. In
essence,impedance transformation allows us to trade off the voltage handling
capability of the device (which does not scale with device size) with its current
handling capability, and therefore extends the power delivering capacity of the
given device technology. However, the amount of extension will be eventually
limited by parasitic effects. Returning to the prior example where the
impedance presented to the active device is reduced from 50W to
50/16=3.125W. Such low impedance allows high power to be delivered with
low voltage swing, but it also increases the amplifiers sensitivity to parasitics.
Consider if a parasitic resistance ofRp is present at the amplifier output due
to on-chip metal routing and wire-bonding contact resistance, then the
amplifier efficiency will be reduced by a factor Rp/(Rp+Ri). In this case, ifRp=
0.5W ( a realistic value in practice), the loss due to Rp will increase 140-folds
from 0.1% to 14% when Riis transformed from 50W to 3.125W.
ii. Waveform Shaping and Filtering
Besides the primary function of impedance transformation, matching
networking can also enhance PA efficiency by properly shaping the current
and voltage waveforms at the drain of the active device. This is the key-
concept embraced in all switch-mode power amplifiers when the active
device is hard-driven, strong harmonics are present at multiples of the
fundamental frequency. Since the impedance looking into the matching
network is frequency dependent, it can be designed to provide proper
terminations at the various harmonic frequencies so as to achieve a desirable
voltage/current waveform at the drain. The usual goal is to minimize the
conduction of transistor current when the drain voltage is high, as minimizing
such overlap can greatly enhance the PA efficiency. Although harmonics can
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be exploited at the drain node to optimize PA efficiency, they are generally
undesirable at the output of the PA where they may interfere with other
wireless systems. When properly designed, the matching
network can attenuate most of the harmonic components at the PA output and
in some cases even eliminate the need of additional band-pass filter between
the PA and the antenna.
V.Choice of power amplifier
Table 1.Comparison of different class of power amplifiers
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Table 2.Comparison of different class of power amplifiers
VI. Power amplifier implementation technology
Fig-6. Summary of comparison of different technology
VII .CONCLUSION
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Explosive growth in wireless communication market has led to consumer
demand for low-cost, small form factor, low power terminals. It has been
proven in practice that high level of integration is the most effective way to
provide such a solution. The VLSI capabilities of CMOS make itself a well-
suited vehicle for high integration. Although it was certainly a non-trivial task
to realize system-on-chip (SoC), engineers from industry together with
researches from universities have figured out ways to integrate almost an
entire system on a single chip. Yet there is still one piece missing on the
integration chart, the power amplifiers. Two major hurdles associated with the
design of fully integrated CMOS power amplifiers are low transistor breakdown
voltage/high threshold voltage, and high loss impedance transformation
network consisting of lossy on-chip passives. To overcome those two hurdles,
highly efficient power combining can be used to generate enough power with
good overall efficiency. Besides integration, there is another serious issue
associated with PA design which is inherent to conventional PA. It is well
known that a PA can only achieve maximum efficiency at peak output power.
As output power decreases, efficiency drops rapidly. Till today on chip power
amplifier is the center of research of engineers and researchers.
VII.References
1. Fully Integrated CMOS Power Amplifier Design Using the
Distributed Active Transformer Architecture-Ichiro Aoki,student
Member,IEEE,Scott D.Kee,David B.Rutledge,Fellow,IEEE,and AliHajimiri,Member,IEEE
2. Fully Integrated CMOS Power Amplifier With Efficiency
Enhancement at Power Back-Off-Gang Liu,Peter Haldi,Tsu-Jae King
Liu,Fellow,IEEE,and Ali M.Niknejad,Member,IEEE
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3. A 1.9-GHz,1-W CMOS Class-E Power Amplifier for Wireless
Communications-King-Chun Tsai,Student Member,IEEE,and Paul
R.Gray,Fellow,IEEE
4. A900-MHz Fully Integrated SOI Power Amplifier for Single-
Chip Wireless Transceiver Applications-Yue Tan,Mahendra
Kumar,Member,IEEE,Johnny K.O. Sin,Senior
Member,IEEE,Longxing Shi,and Jack Lau,Member,IEEE.
5. A Monolithic 2.5V,1W Silicon Bipolar Power Amplifier With
55% PAE At 1.9GHZ.-Werner Simburger,Alexander Heinz,Hans-
Dieter Wohlmuth,Josef Bock,Klaus Aufinger,Mirjana Rest.