lab for the buck converters

8/22/2019 Lab for the buck converters

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Buck Converter - Lab 2

1.0 Objectives:In this lab, the student will design, construct, test, and demonstrate a buck converter. Thisconverter is interfaced to the PV panels and battery to operate the panels at their maximumpower point (MPP).

2.0 Equipment:

MSP430F261x Development Board and MSP-FET430OUIF JTAG Programmer

Lab Computer

Battery Charger and battery

Power Converter Parts Kit (Appendix C)

Perf Board and Standoffs

Multimeter

Oscilloscope with Current Probe

Bench Power Supplies

RLC Meter

3.0 Background: If one directly connects the PV panels to the battery, the current andvoltage are determined by the batterys charging characteristics (state-of-charge, SOC).The resulting operating point may not be at the PV panels maximum power point. Toaddress this problem, we can introduce a DC-DC converter that adjusts the voltage overthe battery so the PV panels set point is at the MPP. This lab realizes the first part of thateffort, but having the student design and build a buck converter whose input is the PVpanel and whose output is the battery we wish to charge.

A buck converter is a direct DC-DC converter whose input is a voltage source and whoseoutput is a current source. Figure 1 shows the common ground configuration for thisconverter when the ground terminals of both sources are tied together. In our system, theinput is the PV panel, which behaves more like a current source than a voltage source. Wetherefore need to connect a capacitor over the PV panel in parallel to provide a voltage-current characteristic which is more like that of a voltage source. In a similar way theoutput load needs to be connected in parallel with an inductor to make it behave morelike a current source. Figure 1 (left) shows the conceptual interconnections of the commonground buck converter. The right side of the figure draws the schematic for the buckconverter topology you will be working with.

In designing a buck converter, there are at a minimum two or three components that mustbe specified. The inputs to the design process are 1) the input voltage, Vin, the desired

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Vin

+

-

Liin

+

-

iout

#1#2

Vout

Vin

+

-

Iout

C2

C1

1

Figure 1: Buck Converter Concept (left), Schematic diagram of a buck converter (right)

nominal output voltage, Vout, and the power consumption, which fixes the input/outputcurrents. The designer selects the inductors L and capacitors C to limit the amount ofripple in various currents within the circuit. The inductor is chosen to limit the currentripple in the diode and capacitor C is chosen to limit the output voltage ripple. Both the

inductor and the capacitor influence the output characteristic of the buck converter. Sinceyou are using a PV panel as an input, you will also need to select an input capacitor Cin tolimit the ripple over the panels terminals.

With the selection of these components, it then becomes possible to bound the maximumand rms currents and voltages that the components must carry. This is important, forthe designer must select components whose current/voltage ratings are consistent withthe conditions within the circuit. If the components ratings are too high, then the circuitcosts more than necessary. If the component ratings are too low, the components may fail(spectacularly) under load.

Component values cannot be chosen freely. There are standard values for inductors and

capacitors. These standard values may not always meet your requirements and when thisis the case, the designer may need to adjust their components to achieve the desired com-ponent values. In general, the capacitor components cannot be easily adjusted. Inductors,on the other hand are easily built and in this lab, the students will design and build a filterinductor for their buck converter. Appendix A describes a design procedure for the filterinductor used in this lab.

Another issue in the construction of switching converters is electro-magnetic interferenceor EMI. Direct DC-DC converters are switched at high frequencies 80 200 kHz and this ishigh so that parasitic inductances in the circuit will begin to radiate EMI. This interferencecan be picked up by other loops within the circuit with the end result being that what thedesigner thought would be nice square waves will actually have a great deal of distor-

tion. Reducing the impact of EMI in converter circuits is a matter of careful circuit layout.The basic principles involve the usual circuit construction principles of keeping wires shortand flat, reducing the area over which a pulsating current loops, avoiding the use of largelooping interconnections. In some cases, we can also use bypass capacitors to confinepulsating currents to small loops within the circuit with very small cross-sectional area.Appendix B discusses some of the layout issues that are relevant to the construction ofyour buck converter.

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4.0 Pre-Lab Tasks: Step 1: Determine the capacitor C1, C2, and inductor L1 for the con-verter schematic in Figure 1. This converter takes the PV panel as the input and the batteryas the output source.

Step 2: Sketch the current waveforms through each of the following power stage compo-nents,

Input filter capacitor, C1

Output filter capacitor C2

Inductor L1

MOSFET drain current iin

diode current id

Compute the maximum, minimum, rms values of each current waveform.

Step 3: Design the inductor to realize the L1 inductor in your design. Specify the wiregauge, number of turns, and air gap length.

Step 4: Select the components from your parts kit to be used for the MOSFET, diode,capacitors C1 and C2. Compare the voltage and current ratings of these parts with theexpected full power voltage and currents for your design.

5.0 Tasks:

Step 1 - Inductor design and construction: The lab kit contains two ferrite cores. Datasheetsfor these cores are linked to the course website. Copper magnet wire of various gauges areavailable in the lab. Construct the inductor you designed in your prelab. Select the wiregauge, wind the required number of turns on the bobbin and assemble the core. Check theinductance value L on the RLC meter and iterate if necessary.

Step 2 - Buck power stage construction: Mount the power MOSFET and Schottky diodeon the heat-sinks from your lab kit. Use the insulators in your kit to insulate the MOSFETand diode cases from the heatsinks: a very thin layer of thermal paste (provided by TA) isneeded on both sides of the insulator to ensure good thermal conduction. A drill will beprovided for drilling holes in your kets perf board to mount standoffs.

Construct the power stage as shown in Figure 2 on the perf board. use # 1 AWG wire tomake the interconnections in the power stage. For the MOSFET and diode, leave loopsof wire long enough to insert a clip-on AC current probe to measure iL, iT, iC and iD.Otherwise, keep the wiring short for connections having pulsating currents. use twistedpairs to make the signal and return connections between boards.

Step 3 - Gate Driver Circuit Construction: Connect a logic output of your MSP430 throughthe gate driver IC as shown in Figure 3. The schematic of the TC4428 is found on the coursewebpage. Be sure to include a 1 F capacitor to bypass the power supply of the TC4428.Program the table duty cycle. Before connecting the gate driver output to the MOSFET,

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Vg

+

-R

Liin

+

-

iout

VC1

0 - 35 V

+

iC1

iT

iD

+

-

vD

iL

C2

+

iC2

Figure 2: Buck Converter Schematic - power stage only

measure the voltage level at the output to make sure it is generating a square wave that islarge enough to drive the MOSFET.

Vg

+

-R

Liin

+

-

iout

VC1

0 - 35 V

+

iC1

iT

iD

+

-

vD

iL

C2

+

iC2

+12 V

supply

MSP430TC4428

gate driver`

+

12 V

zener

1n4148

1n4148

10 k

1/4 W

1 uF 1 uF

Figure 3: Buck Converter with Gate Driver

Step 4 - Buck Power Stage Testing: Connect a load resistor capable of consuming thepower produced by the PV panel to the converters output. Connect the gate driver outputto the MOSFET gate. Be sure to put in the 10k pull-down resistor shown in Figure 3.Program the MSP430 to produce a suitable duty cycle. Apply power to the gate driver ICand verify that the correct drive signal is present at the MOSFET.

With all of the power supplies turned off, connect the power stage to the laboratory bench0-35 VDC power supply (Vg). Use a voltage probe to measure vD(t), and a current probe tomeasure the transistor current iT(t). Use multimeters to measure the load resistor voltageand current. Set the load resistor to its maximum value, set Vg to zero, then turn on allpower supplies. Increase Vg to a few volts and verify that vD(t) and iT(t) waveformsare correct. Be sure not to exceed the 25 V rating of your output capacitor C2. Slowlyincrease Vg to the rated full-power voltage of the PV panels. Adjust the duty cycle to

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obtain an output of13 V, and slowly decrease the load resistance until the output power is100W. Record the DC voltage and current of the source Vg and the load, and calculate theefficiency. Show your results to the TA and if they make sense you can continue to the nextstep.

Step 5: Bench Testing of Buck Converter: Measure the following waveforms and recordfor your report.

Diode voltage vD(t),

Transistor current iT(t)

Diode current, iD(t)

Inductor current iL(t)

Capacitor C1 current iC1(t)

Capacitor C1 voltage vC1(t)

label the waveform names and scales. Label important features.

Mesaure the inductor current ripple iL and compare with the value you designed for inyour prelab assignment.

Measure the capacitor ripple voltage, vC1 and note the waveform ofvC1(t). A practicalcapacitor model includes an equivalent series resistance (ESR) in series with an ideal capaci-tor. In many capacitors, including the aluminum electrolytics used in this experiment, the

ESR induces a major portion of the AC voltage ripple. Based on your measured capacitorvoltage and current waveforms, estimate the value of the ESR. Also estimate the powerloss induced in the ESR, PC = I

2rms(ESR). This power loss limits the maximum AC current

that can be handled by the capacitor. Be sure to include in your report, your estimate ofthe ESR, your estimate of the power loss and the data sheet rms current rating for thiscapacitor.

Step 6: Load Test Adjust or change the load resistor, to obtain a converter output powerof about 15 W, with the duty cycle adjusted as needed to obtain an output voltage of 13V. Record the input and output voltages, the output current, and the duty cycle. Measureand record the waveforms ofiT(t) and vD(t); label the waveform names, scales, and salientfeatures. Was it necessary to significantly change the duty cycle? Why or why not? Repeat

for an output power of approximately 1 W.

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Appendix A - Filter Inductor Design:

A number of factors must be considered in the design of a magnetic device. The peak fluxdensity must not saturate the core. The peak AC flux density should be small enough sothat core losses are low. The wire size should be small enough to fit the required numberof turns in the core window. Subject to this constraint, the wire cross-sectional area shouldbe as large as possible, to minimize winding DC resistance and copper loss. An air gap isneeded when the device stores significant energy.

A.1 Filter Inductor: A filter inductor used in a buck converter is shown in Figure ??. In thisapplication, the value of the inductance, L, is chosen to limit the inductor current ripplepeak magnitude i to a small fraction of the full-load inductor current DC component,I. The structure and magnetic circuit model for the inductor is shown in Figure 4. In thisdevice an air gap is used to prevent saturation of the core by the peak current I+ i.

)b)a

air gapreluctance

g

nturns

i(t)

core reluctance c

+

v(t)

+

ni(t) (t)

c

g

c+

R

RR

R

H

Figure 4: Filter inductor: (a) structure, (b) magnetic circuit model

The cores magnetic filed strength, Hc(t), is related to the winding current i(t) accordingto

Hc(t) =ni(t)

c

RcRc + Rg

where c is the magnetic path length of the core, n is the number of turns, Rc is the corereluctance, and Rg is the air gaps reluctance. Since Hc(t) is proportional to the current

i(t), Hc(t) can be expressed as a large DC component Hc0 that is proportional to the DCcurrent I and an AC ripple Hc that is proportional to the current ripple i.

B

Hc0

Hc

Hc

Bsat

minor B-H loop,filter inductor

B-H loop,large excitation

Figure 5: Filter Inductor: minor B-H loop

A sketch ofB(t) versus Hc(t) for this appli-cation is found in Figure 5. This device op-erates with the minor B-H loop illustrated.The size of the minor loop and hence thecore loss depends on the magnitude of theinductor current ripple i. The copper loss

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depends on the rms inductor current rip-ple, essentially equal to the DC componentI. Typically, the core loss can be ignoredand the design is driven by the copper loss.The maximum flux density is limited bysaturation of the core.

A.2 Filter Design Constraints: Let us consider the design of the filter inductor shownin Figure 4. We assume that the core and proximity losses are negligible, so the induc-tor losses are dominated by low frequency copper losses. The inductor, therefore can bemodeled as a series connection with an inductor L and resistance R. The resistance Rrepresents the resistance of the windings. We want to obtain a given inductance L and agiven winding resistance. The inductor should not saturate when a given worst-case peakcurrent Imax is applied. Note that the specification ofR is equivalent to specification of the

copper loss Pcu

, sincePcu = I

2

rmsR

The inductor winding resistance influences both converter efficiency and output voltage.Hence in design of a converter it is necessary to construct an inductor whose winding resis-tance is sufficiently small.

core window

area WA

wire bare area

AW

core

Figure 6: The winding must fit in the corewindow area

It is assume that the inductor geometry istopologically equivalent to that in Figure 4.An equivalent magnetic circuit is shown inthis figure also. The core reluctance Rc andthe air gap reluctance Rg are

Rc =c

cAc, Rg =

g0Ac

where c is the core magnetic path length,Ac is the core cross sectional area, c is thecore permeability, and g is the air gap length. It is assume that the core and air gap havethe same cross-sectional areas. Application of a magnetic type of KVL relation yields,

ni = (Rc + Rg)

Usually Rc Rg, and so we can approximate the above equation as

ni Rg (1)

so that the air gap dominates the inductor properties. From these considerations we iden-tify four design constraints.

1. Maximum flux density: Given a peak winding current Imax, we want to operator thecore flux density at a peak value Bmax. The value ofBmax is chosen to be less than the

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worst-case saturatuation flux density of the core material. Substitution of = BAcinto equation (1) yields,

ni = BAcRg (2)

We then let I = Imax and B = Bmax to obtain

nImax = BmaxAcRg = Bmaxg0

(3)

This is the first design constraint where the turns ratio n and the air gap length g arethe unknowns.

2. Inductance: The given inductance of the device is

L =n2

Rg =0Acn

2

g (4)

This is the second design constraint where the turns ratio n, the core area Ac, andgap length g are unknown.

3. Winding Area: As shown in Figure 6, the winding must fit through the window (i.e.,the hole in the center of the core. The cross-sectional area of the conductor, or basearea, is AW. If the winding has n turns, then the area of copper conductor in thewindow is nAW. If the core has a window area WA, then we can express the areaavailable for the winding conductors as WAKu where Ju is the window utilizationfactor or fill factor. Hence the third design constraint can be expressed as

WAKu nAW (5)

The fill factor 0 < Ku < 1 is the fraction of the core window area that is filled withcopper. Round wire does not pack perfectly; this reduces Ku by a factor of 0.7 to0.55 depending on the winding technique. The wire has insulation; the ratio of wireconductor area to total wire area varies from 0.95 to 0.65. The bobbin uses some ofthe window area. Typical values for Ku for cores with winding bobbins are 0.5 fora simple low-voltage inductor, 0.25 0.3 for an off-line transformer, 0.05 0.2 for ahigh-voltage transformer at the kV level and 0.65 for a low-voltage foil transformeror inductor.

4. Winding Resistance: The resistance of the winding is

R = WAW

(6)

where is the resistivity of the conductor material, W is the length of wire, and AWis the wire base area. The resistivity of copper at room temperature is 1.724 106

-cm. The length of the wire comprising an n-turn winding can be expressed as

W = n(MLT) (7)

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where (MLT) is the mean-length-per-turn of the winding. This is a function of thecore geometry. The fourth constraint on the resistance R is therefore,

R = n(MLT)AW

(8)

5. Core Geometrical Constant Kg: The four constraints in equations (3), (4), (5), and (8)involve the quantities Ac, WA, and MLT which are functions of the core geometry.The quantities Imax, Bmax, 0, L, Ku, R, and are given specifications and knownahead of time. The variables n g, and AW are unknowns that need to be solved for.Eliminations of the unknowns n g, and AW leads to the following equation

A2cWA(MLT)

L2I2max

B2maxRKu(9)

The quantities on the right side of equation (9) are specifications or other knownquantities. The left side of the equation is a function of the core geometry alone. Acore must be chosen whose geometry satisfies equation (9).

The quantity

Kg =A2cWA(MLT)

(10)

is called the core geometrical constraint. It is a figure-of-merit that describes the effec-tive electrical size of magnetic cores.

3.0 Filter Inductor Design Procedure: Equation (9) shows how specifications impact coresize. Increasing the inductance or peak current requires an increase in core size. Increasingthe peak flux density allows a decrease in core size and hence it is advantageous to usea core material which exhibits a high saturation flux density. Allowing a larger windingresistance, R and hence larger copper loss, leads to a smaller core. Of course, the increasecopper loss and smaller core size will lead to a higher temperature rise, which may beunacceptable.

Equation (10) shows how core geometry affects core capabilities. An inductor capable ofmeeting increased electrical requirements can be obtained by either increasing the corearea Ac or the window area, WA. Increase of the core area requires additional iron orematerial. Increase of the window area implies that additional copper winding material

is used. We may trade off iron for copper by changing the core geometry in a way thatmaintains the Kg in equation (10).

The design procedure outlined above can now be summarized as a more systematic designprocedure. This filter design procedure should only be regarded as a first-pass approach.One usually has to iterate about this design to achieve the specified performance.

The following quantities are specified using the units noted:

The following procedure is used to design the filter inductor

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Table 1: Filter Inductor Variablesname symbol units

Wire resistivity (-cm)Peak winding current Imax (A)Inductance L (H)

Winding resistance R ()Winding fill factor Ku

Core maximum flux density Bmax (T)core cross-sectional area Ac (cm

2)core window area WA (cm

2)mean length per turn MLT (cm)

1. Determine core size:

Kg L2I2max

B2maxRKu 108 (cm5) (11)

Choose a core which is large enough to satisfy this inequality.

2. Determine air gap length:

g =0LI

2max

B2maxAc 104 (m) (12)

with Ac expressed in cm2 and 0 = 4 10

7 H/m. The air gap length is given inmeters. The value is approximate since it neglects certain non ideal effects.

Core manufacturers sell gapped cores. Rather than specifying the air gap length, theequivalent quantity AL is used. AL equal the inductance, in mH, obtained with awinding of 1000 turns. When AL is specified, it is the designers responsibility toobtain the correct gap length. Equation (12) can be modified to yield the required ALas follows,

AL =10B2maxA

2c

LI2max(mH per 1000 turns) (13)

where Ac is given in cm2, L is in Henries, and Bmax is in Tesla.

3.Determine the number of turns:

This is given by the equation

n =LImax

BmaxAc 104 (14)

4. Evaluate wire size: The bare wire area, AW, must satisfy

AW KuWA

n(15)

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Select wire with bare copper area less than are equal this value. You will need to usean AWG (American Wire Gauge) table to do this. As a check, the winding resistancecan be computed as

R =n(MLT)

AW(16)

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Appendix B - Buck Converter Layout Issues:

Building the converter circuit requires some care about the layout. Figure 7 shows one ofthe issues we find in such circuits. This figure shows the two major loop currents within theconverter. One of these current loops, i2(t), is relatively constant in value. The other loopcurrent, however, i1(t), pulsates at a frequency determined by the converters switchingfrequency. To keep the current constant in the second loop, we have two switch fast, 80kHz, which is fast enough to cause problems if the circuit is not laid out with some care.

Vin

+

-

Rload

Liin

+

-

iout

#1#2

VoutCi

1(t) i

2(t)

i1(t)

Iload

0i2(t)

Iload

Figure 7: Pulsating Currents in Buck Converter

If we layout the circuit as shown in the original schematic, the pulsating current goesaround a large loop and the parasitic inductances in the wire will cause a great deal oftrouble. This will be seen in the non-ideal nature of the switching signals at the gate of

the MOSFET as the pulsating currents will couple into the gate driver signals. What oneoften does is reduce the area over which the pulsating current moves by adding a bypasscapacitor as shown in Figure 8. The capacitor shunts the pulsating AC current to a smallerloop that just includes the diode and the MOSFET. Moreover, by arranging the wires inthis loop so they are close and move opposite directions, one is able to reduce the impactof the parasitic inductances in the network.

Vin

+

-

Rload

Liiniout

Ci1(t)

Rload

Liin

+

-

iout

VoutC

pulsating current around large loop interacts

with parasitic inductances in a way that can

severely distort the square wave signals

driving the MOSFETs gate

i1(t)

reduce area of loop with bypass capacitor

and rearrangement of return wiring

Figure 8: Reducing EMI effects in the buck converter

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Another issue one sees in these converters is a loss in power efficiency due to power con-sumption in the gate driver circuit. The gate driver does not switch on instantaneouslyand during this turn-on interval, the current leaving the gate driver can be very large.This current flow has an impact on overall converter efficiency, but also due to its highfrequency content, it will again interact with parasitic inductances to generate additionalEMI. We again use a bypass capacitor as shown in Figure 9 to limit the area over whichthis pulsating current flows.

+-

+-

ucon

gate

driver

converter

power stage

power

MOSFET

+15 Supply

+-

+-

ucon

gate

driver

converter

power stage

power

MOSFET

+15 Supply

Figure 9: Reducing interference from the gate driver

The students should think about how to improve their original design. To optimize thelayout, they may need to reconnect components with shorter length of wires.

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Appendix C - Power Converter Parts Kit:

Integrated CircuitTC4428A Gate Driver IC;

MSP430F2617 Microcontroller;

Power Semiconductor

HUF75321 Power MOSFET, 55V 35A;MBR1645 Schottky Diode, 45V 16A;

Small Discretes

1N4148 Signal Diode, 100V 0.3A 4ns;1N5242B 12V Zener Diode;

Capacitors

330 F 25V Electrolytic Capacitor;3300 F 35V Electrolytic Capacitor;2200 F 63V Electrolytic Capacitor;

22 F 200V Electrolytic Capacitor;10 F 25V Multilayer Ceramic Capacitor;1 F 25V Multilayer Ceramic Capacitor;

0.1 F 50V Multilayer Ceramic Capacitor;0.47 F 100V Multilayer Ceramic Capacitor;

Resistor

10 k 14

W Resistor;1 30 W Power Resistor;4 30 W Power Resistor;

22 Variable Power Resistor;

Transformer and Magnetics

78604/9c 2:1 Micro Transformer;PQ 32/20 Ferrite Core;PQ 26/25 Ferrite Core.

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Appendix D - Selecting Parameter for Buck Converter:

Vin

+

-

Liin

+

-

iout

#1#2 V

out

C2

C1

1

Figure 10: Circuit Diagram of Buck Converter

This appendix shows an example of choosing inductor and capacitor parameters for thebuck converter. As shown in Figure 10, the circuit demonstrates the structure of the con-verter, as well as component parameters that need to be determined. Consider the inputvoltage Vin = 15V 25V and the output voltage being fixed as Vout = 12V. The maxi-mum output power level of the circuit should be 100W, which corresponds to a chargingcurrent of8.33A. The switching frequency is 80kH z with a period of12.5s. The deriva-tion is as following:First set the output capacitor to be C = 0. When the input voltage is 25V, the duty ratio

of the MOSFET is D1 =12V25V = 48% and the corresponding conduction ratio of diode is

D2 = 1 D1 = 52%. Assuming the inductor current is within 1%, which is iL =1

6A.

When the power MOSFET is off, the voltage over the inductor is VL = 13V and theinterval is t = D2T = 6.5s. Then there is:

|VL| Ldi

dt L

i

t.

Then the inductor must satisfy:

13 6.5 106

L

1

6

,

L 507H.

The inductor should be at least 507H to meet the requirement when C2 = 0. This isalso too large to be constructed in our lab, so that we may have C = 0 to have a smallerinductor. Now choosing the inductor to be L = 50H, the capacitor can be determined asfollowing:

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The inductor current varies by

i = 13D2T

L,

=13 6.5 106

50H,

= 1.69A.

The inductor can be treated as a triangular equivalent source, while the output is a fixedsource. Since the capacitor is parallelled to the inductor, while iC is positive, the voltagevC increases by an amount of

V =1

CVC0

iCdt,

12V 2%.

As a result, the capacitor should satisfy

C 6.25 106 1.69/2

0.24V= 22F.

The introduction of output capacitor reduces the required inductor value, but still satisfiesthe ripple requirement.

In another case, the input voltage is 15V, then the duty ratio of the MOSFET is D1 =12V15V

=80% and D2 = 1 D1 = 20%. Still assuming the inductor current is within 1%, whichis iL =

1

6A. When the power MOSFET is off, the voltage over the inductor is VL = 3V

and the interval is t = D2T = 2.5s. Then there is:

|VL| Ldi

dt L

i

t.

Then the inductor must satisfy:

3 2.5 106

L

1

6 ,L 45H.

Since the inductor value is much smaller than the selected value above, the previous pa-rameter selection can be kept for this case.

As a result, considering the standard values of capacitors, the combination of fswitch =80kH z, L = 50H, C = 47F, and 48% D1 80% meets all the requirements.

16

lab for the buck converters

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