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Chapter

4Buck Topology Converters

Many power converters in use today are based on buck topologies. Thebuck topology includes all converters that produce an output voltagewhich is proportional to a controlled duty cycle. The switched voltageis averaged by an L-C filter, which results in a DC voltage. Examples ofbuck topologies include buck regulators, forward converters, and push-pull converters.

Hysteretic Switching Regulator

The circuit shown in Fig. 4.1 is the simplest form of a buck regulator. Thecircuit was popular in the 1970s because of its simplicity and extremelylow parts count. The 723 regulator IC operates as a comparator thathas a driver and a voltage reference. The circuit has many drawbacks,such as variable frequency and poor dynamic control, because it is basi-cally an uncompensated oscillator. The advent of high-technology pulsewidth modulator control ICs has almost replaced this form of regulator.Circuits such as this can still be found in many linear data books andlow-cost commercial products. The circuit does, however, demonstratethe principles of switching regulators.

The input voltage is switched by Q1. The switched voltage is averagedby L1 and C2. During the switch-off time, a current circulates throughD1. The averaged output is fed to the load resistor R6. Resistor R8introduces the hysteresis (positive feedback) and causes the circuit tooscillate. The switch voltage and output voltage waveforms are shownin the graphs in Fig. 4.1.

HYSTREG: BUCK REGULATOR.TRAN .1U 2500U 2400U UIC.PROBE

91



92 Chapter Four

∗ V(10)=VOUT∗ V(7)=VSWITCHR1 2 10 10R3 1 11 2.2KR4 11 0 5.1KC1 11 0 .1U IC=5Q1 7 8 6 QSB1071AR5 6 8 100V1 6 0 PULSE 0 12D1 0 7 DN5811L1 7 10 500U IC=1C2 10 16 10U IC=5R6 10 0 5R7 4 11 1KR8 7 4 220KR9 16 0 .1X1 10 10 4 1 0 2 8 6 5 2 UA723.END

Average (State Space) versus SwitchingLevel Transient Models

Switching circuit models typically fall into two major categories: aver-age models and nonlinear transient switching models. Average models,also known as state space models, represent the operation of switchingcircuits via linear techniques, as opposed to switching techniques. Alllinear circuits fall into the category of average models. There are a

CL

CS

IN-

IN+

VREF

VCC-

FRCO

VCC+

VC

VOUT

NC

NC

NC

NC

X1 UA723

R110R3

2.2K

R45.1K

C1.1U

Q1 QSB1071A

R5 100

D1DN5811

L1500U C2

10U R65

V(10)VOUT

V(7) VSWITCH

R71K

R8220K

V(4)

R9.1

VOUTTran

5.19

4.892.50M2.40M time

V(4)Tran

5.02

4.952.50M2.40M time

VSWITCHTran

12.6

-1.332.50M2.40M time

10

4

1

2

8

6

5

11

7

16

Figure 4.1 The simplest form of a buck regulator circuit.



Buck Topology Converters 93

number of citations in the References section that discuss the usage ofaverage models in detail.

Transient models represent switching circuits in the time domain, ina manner as close to actual functionality as possible. It may seem desir-able to simulate all circuits using transient models; however, transientmodels simulate much more slowly than their averaged model coun-terparts. Many characteristics, such as open-loop gain, are difficult tosimulate using transient models. Both types of models are included inthis book and both may be used in the transient analyses for differentpurposes. You will quickly learn to determine which modeling techniqueyou should apply to a specific problem.

The previous example uses transient simulation, which simulatesthe actual time-dependent functions of the circuit, such as the turn-on and turn-off of the semiconductor switch. There are many benefitsof using this modeling approach. The model is very accurate; it dis-plays phenomena such as switching spikes, propagation delays, andripple and sampling effects; and it allows testing of different control ICs.There are also disadvantages of the nonlinear approach. Simulationstend to take much longer, although with the ever-increasing computerpower available on the desktop, simulations that were impractical onlya few years ago can now be run in a matter of minutes. There are sometechniques that are available to speed up the simulation. They are listedin Chap. 9. More importantly, however, AC analysis is not possible be-cause switching devices are either in their on or off state. To simulatesuch a circuit, the switching action must be averaged so that a smallsignal model can be generated.

Average modeling is reasonably accurate and extremely fast and sup-ports AC as well as some transient analyses. The average models aretherefore useful for simulations such as conducted susceptibility, open-loop phase gain, output impedance, and input impedance. The majordrawback is that time domain information, such as ripple, spikes, gatecharge, and instantaneous switching loss, is not available.

The generalized solution is to use the correct model depending on thebehavior you want to investigate. Table 4.1 provides some assistance.Both models may be used during the development of a product andthe ensuing worst-case tolerance analysis. Examples of both methodsare shown in this chapter.

Average Modeling Example

As an example of average modeling, let us consider a simple buck reg-ulator circuit. In order to keep the example simple, we will assumethat we are using voltage mode control. Voltage mode control was pop-ular when pulse width modulator ICs, such as the SG1524, were first



94 Chapter Four

TABLE 4.1 Simulation Strategies for Some Typical Power Supply Analysis [8]

Type of analysis Strategy

Power stage semiconductorstress analysis at startup

Transient Models – Accelerate startup by reducingsoft-start time constant, if applicable. Use averagemodel transient results as a road map.

Power stage semiconductorstress analysis at steadystate

Transient Models – Initialize close to steady stateaverage DC results. Only initialize largest timeconstants like output filter L and C, or compensationcapacitors.

Power stage stress analysiswith short-circuitedoutput

Transient Models – Initialize circuit, then dynamicallyshort output with voltage-controlled switch.

Line or load transientresponse

Average Models – Disable UVLO for correct DC results.Do not initialize circuit. Allow natural DC solution,then run transient analysis using source or switch tocause line or load transient.

Magnetic saturation, shortcircuit condition

Transient Models – Initialize circuit for steady state,then short output with a switch.

AC loop stability analysis Average Models – Allow natural DC solution. Do notuse initial conditions. Split feedback loop using alarge inductor (blocks AC), then couple AC sourcesignal to input side with a large capacitor.

Input noise filterdesign – Ripple currentmeasurement

Average or Transient Models – Drive the power stageusing a voltage source with a fixed duty cycle.Controller with feedback is not necessary.

introduced. Most of the newer pulse width modulators utilize currentmode control (which we will cover later in this chapter). The pulse widthmodulator compares the output of an error amplifier (VC) to a fixed saw-tooth waveform that has a lower voltage (VL) and has an upper voltage(VH). The output of the IC is a duty cycle, which is used to turn thesemiconductor switch on and off. The duty cycle can be calculated as

D = VC − VL

VH − VL

The output of the converter is the average of the switch duty cycle. Theconverter output is then defined as

Vo = Vin D

Combining these two equations, we can obtain the modulator transferfunction as

Vo = Vin(VC − VL)VH − VL

Similarly, the input current can be modeled as

Iin = Io D




E1

G1

RS

RP

6

21

3

2

145

3

2

1

2

4

5

3*Pulse Width Modulator .SUBCKT PWM 1 2 3 4 5 E1 6 2 POLY(2) 1 2 4 5 0 0 0 0 1 G1 1 2 POLY(2) 6 3 4 5 0 0 0 0 1KRP 1 2 1MEG RS 3 6 1M .ENDS

Figure 4.2a Pulse width modulator (PWM) equivalent circuit.The dashed line indicates that the voltage V(4,5) controls thedependent sources G1 and E1.

Figure 4.2a demonstrates the basic structure and operation of thestate averaging “PWM switch” subcircuit [5,66]. This model replacesthe pulse width modulator switches. In Fig. 4.2b, a DC analysis isperformed, in which we sweep V2 from 0 to 1. This terminal is theduty cycle control, so we are sweeping the duty cycle from 0% to100%.

As we monitor the output voltage and the input current, we can seethat the output voltage is equal to V1 D, and the input current is equalto I1*D, which agrees with our simplified derivation above.

PWM: TO SIMULATE A VOLTAGE NODE CONVERTER.DC V2 0 1 .01.PROBE.PRINT DC V(2) I(V1)X1 1 0 2 3 0 PWMV2 3 0I1 2 0 1V1 1 0 10.END



96 Chapter Four

V110 X1

PWM

V2

V(2)

I11

I(V1)

I(V1)DC

50.0M

-1.051.000 v2

V(2)DC

10.5

-501M1.000 v2

1

2

3

Figure 4.2b PWM subcircuit to sweep the duty cycle from 0% to 100%.

SG1524A Buck Regulator

The PWM switch can easily be combined with a PWM IC model, suchas the SG1524 pulse width modulator subcircuit, to simulate a com-plete voltage mode converter. The PWM switch represents the Vo = Vin Dfunction, while the SG1524 subcircuit correctly models the modulatorgain.

The next example combines the SG1524A subcircuit with the PWMswitch to model a voltage mode buck regulator (Fig. 4.3). The SG1524model is parameterized, which makes it more flexible. The parameterspassed to the SG1524A subcircuit are

T=10 µs Switching periodTO=1 µs Dead timeTS=0.25 µs Transistor storage timeEP=3.5 V Peak saw voltageEO=0.5 V Minimum saw voltage

You can view the SMPS Book.LIB file on the enclosed CD to see howthe parameters are utilized in the SG1524 subcircuit.

The regulator model is extremely simple. The SG1524A subcircuitcontains the error amplifier, reference, and comparator sections. Thecomparator compares the output of the error amplifier with a sawtoothand generates a resultant duty cycle. The duty cycle is modified bythe storage time and dead time parameters, which are passed to thesubcircuit.




Comp

E/A

5V

Ref.Osc.

-7

+5

X1 SG1524A

X2 PWM

V112

R110K

L1 100U

C1220U R3

100

R4 22K

R5 47KC2 .01U

C3 6.8N

L21

C4 1

V2+

AC

V(10)

V(9)COMP

R6 1.5K

R7.05

9

1

3

2

4 10

13

6

128

11

1

1524BCK: TO MODEL A VOLTAGE MODE BUCK REGULATOR.OP.AC DEC 25 100HZ 1000KHZ.PROBE∗ V(9)=COMP.PRINT AC V(10) VP(10) V(9) VP(9)X2 2 0 4 1 0 PWMV1 2 0 12R1 3 5 10KL1 4 10 100UC1 10 13 220UR3 10 0 100R4 7 6 22KR5 7 8 47KC2 8 9 .01UC3 7 12 6.8NL2 10 6 1C4 6 11 1V2 11 0 AC 1R6 12 6 1.5KR7 13 0 .05X1 7 5 9 1 3 SG1524A Params: T=10U TO=1U TS=.25U EP=3.5 EO=.5.ENDFigure 4.3 Schematic and “top-level” netlist of a complete voltage mode converter usingthe PWM switch and SG1524.

The output filter causes a double pole at

F = 1

2π√

L1C1= 1073 Hz

One of these two poles is canceled by R4 and C3, which has a cornerfrequency of

F = 12π R4C3

= 1064 Hz



98 Chapter Four

A third pole is caused by capacitor C2, which is used to provide maxi-mum DC gain for regulation purposes. R5 provides a zero with C2 at afrequency of

F = 12π R5C2

= 338 Hz

The zero is below the frequency of the output filter pole in order toimprove phase margin. If the output filter has a lower Q (it normallydoes not), then the zero could be at a frequency that is closer to theoutput filter pole. An additional zero exists, because of the output filtercapacitor ESR at

F = 12π R1C7

= 14, 475 Hz

This zero is canceled by R6 and C3, which has a corner frequency of

F = 12π R6C3

= 15, 611 Hz

The DC gain of the modulator is approximated by

Gain = Vin (T − T0)(EP − E0) T

= 3.6 = 11.1 dB

The regulator is configured as an open-loop model in order to measurethe Bode response. Inductor L2 is set to 1 H in order to effectivelyopen the loop. The plots in Figs. 4.4, 4.5, and 4.6 show the modulatorgain (VM(10)/VM(9) and VP(10) - VP(9), where VM is the magnitudeand VP is the phase), the error amplifier gain (V(9)), and the overallloop gain (V(10)), respectively.

In the next simulation, the loop is closed in order to simulate theaudio susceptibility and load transient characteristics of the converter.The modified schematic is shown in Fig. 4.7. Note that L2 has beenremoved.

1524BCK: TO SIMULATE THE AUDIO SUSCEPTIBILITY AND∗THE LOAD CHARACTERISTICS OF THE CONVERTER.OP.TRAN 1U 5M 0 5U.AC DEC 20 100HZ 1MEGHZ.PROBE∗ V(9)=COMP.PRINT AC V(12) VP(12) V(9) VP(9).PRINT TRAN V(12)X2 2 0 4 1 0 PWMV1 2 0 12 AC 1R1 3 5 10K




L1 4 12 100UC1 12 10 220UR3 12 0 1R4 7 12 22KR5 7 8 47KC2 8 9 .01UC3 7 6 6.8NR6 6 12 1.5KR7 10 0 .05I1 0 12 PULSE 0 1 1U 1U 1U 2.5M 5MX1 7 5 9 1 3 SG1524A Params: T=10U TO=1U TS=.25U EP=3.5 EO=.5.END

The results of the load transient response and audio susceptibilitysimulations are shown in Figs. 4.8 and 4.9, respectively.

Discontinuous Mode Simulation

Although this model is extremely simple to use, it does have one sig-nificant drawback. The modulator transfer function is valid only forcontinuous mode operation. The previous example has an inductor rip-ple current of approximately 200 mA peak-to-peak. This allows the con-verter to operate at a load current level as low as 100 mA but maintains

2

11311.2<

x

>

1

1K 10K 100K

Frequency in Hz

20.0

-20.0

-60.0

-100.0

-140

Mod

ulat

or G

ain

(wfm

1) in

dB

(V

olts

)

330

210

90.0

-30.0

-150

Mod

ulat

or P

hase

(w

fm2)

in D

eg

∆x = 12.6 ∆y = 15.8M

Figure 4.4 Graph of the modulator gain and phase. The waveform division and subtractionto create the waveforms was performed in IntuScope.



100 Chapter Four

1

2

1K 10K 100KFrequency in Hz

450

350

250

150

50.0

Err

or A

mp

Pha

se (

wfm

2) in

Deg

30.0

10.00

-10.00

-30.0

-50.0

Err

or A

mp

Gai

n (w

fm1)

in d

B (

Vol

ts)

Figure 4.5 Graph for the error amplifier gain (Vdb(9)) and phase (VP(9)).

1

7.69K76.0<

x

>

279K-61.7M<

x

> 2

1K 10K 100K

Frequency in Hz

330

210

90.0

-30.0

-150

Ope

n Lo

op P

hase

(w

fm2)

in D

eg

20.0

-20.0

-60.0

-100.0

-140

Ope

n Lo

op G

ain

(wfm

1) in

dB

(V

olts

)

Figure 4.6 Graph of the open-loop gain (Vdb(10)) and phase (VP(10)). L2 effectively opensthe loop.




Comp

E/A

5V

Ref.Osc.

-7

X1 SG1524A

X2 PWM

V112

R110K

L1 100U

C1220U R3

1

R4 22K

R5 47K C2 .01U

C3 6.8N

V(12)V(9)COMP

R6 1.5K

R7.05

+5

9

1

3

2

4 12

10

8 6

current

pulse

Figure 4.7 Schematic design for a closed-loop converter. L2 has been removed (see Fig. 4.6).

continuous mode operation. Typical ripple currents will more realisti-cally allow operation from 10% to 100% of the load in continuous mode.This model will not produce accurate results for discontinuous modeoperation. The graph in Fig. 4.10 shows the results of a simulation ofthe previous circuit with a 50-mA load current.

A state space model that can simulate continuous and discontinuousmode operation for both current mode and voltage mode converters isincluded in the AEi Systems Power IC Library for PSpice.

1

500U 1.50M 2.50M 3.50M 4.50M

Time in Secs

5.08

5.04

5.00

4.96

4.92

V(9

) in

Vol

ts

Figure 4.8 Load transient response V(12) as the result of a current pulse from I1.



102 Chapter Four

1

1K 10K 100K

Frequency in Hz

-10.00

-30.0

-50.0

-70.0

-90.0

Aud

io S

usce

ptib

ility

in d

B (

Vol

ts)

Figure 4.9 Audio susceptibility simulation result from the AC analysis. V(12) is shown.

1

2


330

210

90.0

-30.0

-150

Pha

se (

wfm

2) in

Deg

60.0

20.0

-20.0

-60.0

-100.0

Ope

n Lo

op G

ain

(wfm

1) in

dB

(V

olts

)

50mA Load

Figure 4.10 Open-loop gain and phase of the closed-loop converter circuit with a 50-mAload.




R1RB

V(15)VIN

VCC

VEE

V(3)VC

V(9)D

DELAY CLK Q

Q -

S R D

V(6)D

F

TS1:NC

1:NP

LP

K*D

4

6

1 2 16

15 47

3

5

9

14

7

46

13

45

Figure 4.11 Schematic for a buck mode converter that can be used in both voltage andcurrent modes with discontinuous and continuous inductor currents.

An Improved Buck Subcircuit

An improved buck topology subcircuit, which is based on the peak andvalley inductor currents, allows operation in both voltage and currentmode with discontinuous and continuous inductor currents. The deriva-tion of the model is shown in Fig. 4.11.

Definition of terms

Pin Converter input power Vin Converter input voltageLo Output filter inductance VC Control voltageImin Minimum output inductor

currentNp Power transformer ratio Ns/Np

Imax Peak output inductorcurrent

Vo Converter output voltage

Fsw Switching frequency Io Average output currentTs Current loop propagation

delay timeRb Current transformer burden

resistorTon MOSFET on-time Nc Current transformer ratio 1:NcD2 Freewheeling conduction

duty cycleD Switch on-time duty cycle

Dmax Maximum switch duty cyclelimit

Governing equations

The offset error amplifier output (VC) controls the peak current in theprimary of the power transformer, as sensed by a current transformerwith a turns ratio of 1:Nc.



104 Chapter Four

The PWM turns off the switch when the voltage at VC is equal to thecurrent sense voltage across Rb. The switch will remain on for the delaytime of the PWM comparator plus the switch turn-off delay. The totaldelay time is referred to as Ts.

Imax is therefore defined by the control voltage (VC) as

Imax = VcNc

Np Rb+

((VinNp

) − Vo) ∗ Ts

Lo(4.1)

which is valid for VC> 0The on-time of the switch is based upon the voltage across the outputinductor and the (Imax – Imin) of the inductor current:

Ton = Lo(Imax − Imin)VinNp − Vo

(4.2)

Relating Ton to D,

Ton = DFsw

(4.3)

If we substitute and solve for D, Eq. (4.3) becomes

D = Lo Fsw

VinNp − Vo(Imax − Imin) (4.4)

During the time for which the switch is off, the current will decay inthe output inductor. The minimum current is defined as

Imin = Imax − Vo(1 − D

)Lo Fsw

while Imin > 0 (4.5)

If the converter operates in the discontinuous mode, the inductor cur-rent will be zero prior to the end of the switching cycle. If we define theoff conduction time through the freewheeling diode as D2, we can solvefor D2 in terms of (Imax − Imin) as

D2 = Lo Fsw

Vo(Imax − Imin) (4.6)

The output current from the converter is calculated as

Io = (Imax − Imin)(D + D2)

2(4.7)

Note that in continuous conduction mode, D + D2 = 1.




Substituting Eqs. (4.4) and (4.6) into Eq. (4.7) gives

D = Lo Fsw

2

(I2max − I2

min

) (1Vo

+ 1VinNp − Vo

)(4.8)

Finally, rearranging Eq. (4.5), we can obtain the value of Imin. Notethat in the continuous mode the value of Imin will be positive, whereasin discontinuous mode it will be zero. This allows us to equate the volt-second products across the inductor for intervals of D and D2, whichyields the familiar expression

D = Vo

VinNp(4.9)

Combining Eqs. (4.5) and (4.9) yields

Imin = Imax − Vo

Lo Fsw

(1 − Vo

VinNP

)(4.10)

The converter power can be represented on the primary side by equat-ing the input power with the output power:

Iin = Vo Io

Vin(4.11)

Finally, note that by restricting Imin to values greater than or equalto zero, both continuous conduction and discontinuous modes will beproperly represented.

Adding Slope Compensation

The schematic in Fig. 4.12 shows the addition of an external ramp thatprovides slope compensation to the model. The D output of the subcir-cuit is provided for this purpose. The D output is a voltage equivalentof the duty cycle, so that a ramp is defined as K*D, where K is the peakvoltage of the ramp at a duty cycle of 1. K may also be described as theslope of the ramp divided by the switching frequency.

Although we do not have access to the internal nodes that are re-quired in order to add the ramp, we can rotate it through the compara-tor and easily add it externally. A nonlinear arbitrary dependent source(Berkeley SPICE 3 B element) or PSpice E element is used to providethe multiplication K *D. The schematic in Fig. 4.13 shows the imple-mentation of the external slope compensation ramp of the subcircuit.



106 Chapter Four

R1RB

V(15)VIN

VCC

VEE

V(3)VC

V(9)D

DELAY

V(11)VOUT

CLK Q

Q -

S R

D

V(6)D

F

TS1:NC

1:NP

LP

K*D

4

6

1 2 16

15 10

3

5

9

14

7

11

13

Figure 4.12 Buck mode converter with the addition of an external ramp.

Voltage Mode Control

If we use a further extension of the circuitshown in Fig. 4.13, voltagemode control (also called duty cycle control) can be implemented. Inthis case, there is no current sensed, so that RB will ideally be set tozero. RB cannot be set to zero because it will result in a divide-by-zeroerror within the subcircuit. It may, however, be set to a very low valuesuch as 1 m� or less, if necessary. If we set K to 1, the result will be aduty cycle that is equal to the control voltage VC. The modulator gaincan also be represented in this subcircuit by setting K to 1/Vr, whereVr is the peak-to-peak voltage of the ramp. Within the subcircuit, VCis bounded between 0 and 1 V. In order to use this limiting function,it is recommended that you set K to 1 and add the modulator gainexternally.

R1RB

V(15)VIN

VCC

VEE

V(5)VC

V(9)D

DELAY

V(11)VOUT

CLK Q

Q - S R

D

V(6)D

F

TS 1:NC

1:NP

LP

K*D

B4 K*D 4

6

1 2 16

15 10

3

59

14

7

11

13

Figure 4.13 Implementation of the external slope compensation ramp to the subcircuit.




Comp

E/A

5VRef.

Osc.

-1

+7

X1 SG1524A

V112

R110K

L1 100U

C1220U

R2100

R3 22K

R4 47K C2 .01U

C3 6.8N

L2 1

V2AC

V(15)

V(2)COMP

R5 1.5K

R6.05

VIN VOUT

RTNVC DUTY

FORWARD

X3 SSFWD

B1V=V(14)

C51

2

13

4

5 6 15

8

9

10 11

12

3 14

Figure 4.14 The buck mode subcircuit (forward) is used in a buck regulator simulation.

Improved SG1524A Buck Regulator

The example in Fig. 4.14 uses the buck mode subcircuit to model thebuck regulator example (Fig. 4.3).

1524BCK3: A NEW BUCK MODE SUBCIRCUIT.AC DEC 25 100HZ 1000KHZ∗ V(2)=COMP.PRINT AC V(15) VP(15) V(2) VP(2).PROBEV1 5 0 12R1 4 7 10KL1 6 15 100UC1 15 8 220UR2 15 0 100R3 1 9 22KR4 1 10 47KC2 10 2 .01UC3 1 11 6.8NL2 9 15 1V2 12 0 AC 1R5 11 9 1.5KR6 8 0 .05X3 5 0 3 6 14 SSFWD Params: L=100U NC=1 NP=1 F=100K DMAX=.9+ RB=1M TS=.25UEB1 13 3 Value={ V(14) }C5 9 12 1X1 1 7 2 13 4 SG1524A Params: T=10U TO=1U TS=.25U EP=3.5 EO=.5.END



108 Chapter Four

1

2

1K 10K 100K Frequency in Hz

330

210

90.0

-30.0

-150

Pha

se (

wfm

2) in

Deg

20.0

-20.0

-60.0

-100.0

-140

Ope

n Lo

op G

ain

(wfm

1) in

dB

(V

olts

)

50mA Load

Figure 4.15 Graph of the open-loop gain and phase, node 15.

1

2

1K 10K 100K

Frequency in Hz

330

210

90.0

-30.0

-150

Pha

se (

wfm

2) in

Deg

20.0

-20.0

-60.0

-100.0

-140

Ope

n Lo

op G

ain

(wfm

1) in

dB

(V

olts

)

50mA Load

Figure 4.16 Graph of the open-loop gain and phase with a 50-mA load.




The results of the simulation are shown in Fig. 4.15. Note the ex-cellent agreement between this model and the previously used PWMswitch model.

The circuit was resimulated with a 50-mA load current, which causedit to operate in discontinuous conduction mode. The results of the sim-ulation are shown in Fig. 4.16.

Note the drastic difference in the phase gain plot compared with thatof the PWM switch. The improved model correctly shows the reductionin modulator gain and also correctly shows that the modulator is rep-resented by a single pole rather than two poles, as in the continuousconduction mode. From the operating voltages in the schematic, it isalso evident that the improved model correctly shows that the duty cy-cle is significantly reduced as a result of the discontinuous operation.The graph in Fig. 4.17 shows the result of the modulator gain using theimproved model.

Transient Model

The Power IC Model Library for PSpice also includes transient-basedmodels of many pulse width modulators, including the UC1524A, whichis identical to the SG1524A. The next example shows the applicationof the nonlinear switching transient models to simulate the previous

21


20.0

-20.0

-60.0

-100.0

-140

Mod

ulat

or G

ain

(wfm

1) in

dB

(V

olts

)

330

210

90.0

-30.0

-150

Mod

ulat

or P

hase

(w

fm2)

in D

eg

Figure 4.17 Result of the modulator gain using the new model.



110 Chapter Four

INV

NINV

SYNC

+CL

-CL

RT

CT

GND COMP

SD

EA

CA

CB

EB

VIN

VREF

R1 3K

C1 2.2N

R2 10K

V112

Q1QN2222A

R3 1K

D1DN4148

D2SHD1352

L1 100U

C2220U

R4.05

R51

R647K

C3.01U

R722KC4

6.8N

R81.5K

V(18)OUT

C5.047U

R947

C6.01U

R104.7

X3 MTM8P10

I1PULSEI(V1) ISWICH

V(9)DRIVE

V(14)COMP

ISWICHTran

493M

-6.542.00M1.97M time

V(18)Tran

5.10

5.092.00M1.97M time

DRIVETran

13.4

-590M2.00M1.97M time

COMPTran

2.05

1.902.00M1.97M time

12

5

1

2

3

14

9

10

4

8

7

6 18

11

13

17

16

Figure 4.18 Application of the transient subcircuits to simulate the previous buckregulator.

buck regulator circuit (Fig. 4.18). The transient model properly modelsthe output ripple, propagation delay times, and cycle-by-cycle switchingeffects. The disadvantage to the transient models is the increased sim-ulation time and the difficulty in simulating frequency domain charac-teristics such as phase-gain analysis and audio susceptibility.

TRAN1524: TO SHOW THE APPLICATION OF THE TRANSIENT SUBCIRCUIT.TRAN .2U 10M 5M .05U UIC ; Load Step∗.TRAN .2U 5M 0 .05U UIC ; Startup.PROBE.OPTION GMIN=1N ABSTOL=10U VNTOL=10U RELTOL=.01 ITL4=100∗ V(6)=SWITCH∗ V(15)=OUT∗ I(V1)=ISWICH∗ V(9)=DRIVE∗ V(14)=COMP.PRINT TRAN V(6) V(15) I(V1) V(9).PRINT TRAN V(14)R1 2 0 3KC1 3 0 2.2NR2 5 4 10KV1 10 0 12Q1 10 8 7 QN2222AR3 10 8 1KD1 7 8 DN4148D2 0 6 SHD1352L1 6 15 100UC2 15 11 220U




R4 11 0 .05R5 15 0 1R6 12 13 47KC3 13 14 .01UR7 12 15 22KC4 12 17 6.8NR8 17 15 1.5KC5 5 0 .047UR9 8 9 47C6 6 16 .01UR10 16 0 4.7X3 6 7 10 MTM8P10I1 0 15 PULSE 0 1 5.001M 1U 1U 2.5M 5M ; Load Step∗ I1 0 15 1 ; StartupX1 12 5 1 0 0 2 3 0 14 0 0 9 9 0 10 4 UC1524A.END

The graph in Fig. 4.19 displays the results of the transient step loadresponse. The upper trace is the result of the state space model, andthe lower trace is the result of the transient simulation. Note thatthe transient model shows a slightly lower Q, as evidenced by thereduced undershoot that results from the MOSFET’s on resistance.Also note that the transient model includes the output ripple. Thewaveforms in Fig. 4.18 show the MOSFET’s voltage and outputripple.

2

1

5.50M 6.50M 7.50M 8.50M 9.50MTime in Secs

5.35

5.25

5.15

5.05

4.95

Tra

nsie

nt O

utpu

t (w

fm1)

5.10

5.00

4.90

4.80

4.70

Sta

te S

pace

Out

put (

wfm

2) in

Vol

ts

Figure 4.19 Transient step load response.



112 Chapter Four

1.84M5.17<

x

>

1

500U 1.50M 2.50M 3.50M 4.50M

TIME in Secs

6.00

4.00

2.00

0

-2.00

Vou

t in

Vol

ts

Figure 4.20 Turn-on response of the output voltage, V(15), using the nonlinear transientmodel.

2.10M5.18<

x

>

1

500U 1.50M 2.50M 3.50M 4.50M

Time in Secs

6.00

4.00

2.00

0

-2.00

V(9

) in

Vol

ts

Figure 4.21 Turn-on response of the output voltage, V(15), using the state space model.




Time

0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0msV(15)

0V

1.0V

2.0V

3.0V

4.0V

5.0V

6.0V

Figure 4.22 Turn-on response of the output voltage, V(15), using the transient model.

When I first ran this simulation on a 75-MHz Pentium computer,it required approximately 2 hours of simulation time. On a P4 3-GHzcomputer, it ran somewhat faster, taking 4 min 9.42 s.

The simulation speed has obviously improved, although the tran-sient simulation will always be considerably slower than the state spacemodel, which runs in less than a tenth of a second.

Why do we bother using transient models? The transient model al-lows us to view important considerations of the real hardware. In thiscase, the concern was the “cheap and dirty” high side driver circuit.The transient simulation allowed us to view the topological aspectsof the circuit as well as the MOSFET switching speed. The transientmodel was also used to perform a simulation at a light load current of50 mA. According to the state space model, the converter should oper-ate in discontinuous conduction mode. The snubber was removed fromthe Schottky diode in order to make the discontinuity easier to see.

The operating duty cycle under this condition is approximately 25%,which agrees with the state space model. A final simulation shows theturn-on of the buck regulator in order to establish the functionality ofthe soft-start circuit, which comprises R2 and C5.

The buck regulator reached a maximum voltage of 5.17 V (Fig.4.20), which equates to approximately 3% overshoot. Although this isgenerally acceptable, the soft-start time can be increased in order toeliminate the overshoot. For comparison purposes, the turn-on simula-tion was also performed using the new state space and the transientmodels (Figs. 4.21 and 4.22).



114

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