kuliah rangkaian digital kuliah 7: unit aritmatika teknik komputer universitas gunadarma

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Kuliah Rangkaian Kuliah Rangkaian Digital Digital Kuliah 7: Unit Aritmatika Kuliah 7: Unit Aritmatika Teknik Komputer Teknik Komputer Universitas Gunadarma Universitas Gunadarma

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Kuliah Rangkaian Digital Kuliah 7: Unit Aritmatika Teknik Komputer Universitas Gunadarma Slide 2 Topic #7 Arithmetic Units ComparatorAdders Half-adder & Full-adder Half-adder & Full-adder Carry-ripple adder & carry-look-ahead adder Carry-ripple adder & carry-look-ahead adder Overflow detection Overflow detectionSubtractorMultiplier Slide 3 (Equality) Comparators (using XOR) 1-bit comparator 4-bit comparator Slide 4 Adds two 1-bit input to produce a sum and a carry-out Does not account for carry-in Does not account for carry-in XYXY S C out Half adder S = XY + XY = X Y C out = XY Inputs Outputs Y0101Y0101 S0110S0110 X0011X0011 C out 0 1 Slide 5 Full adder Building block to realize binary arithmetic operations 1-bit-wide adder with carry-in, produces sum and carry- out Truth table: XYC in SC out 00000 00110 01010 01101 10010 10101 11001 11111 Slide 6 S Cin X 0 10 1 00 01 11 10 Y Cin XY 0 1 2 3 6 7 4 5 1 1 1 1 Cin X 0 10 1 00 01 11 10 Y Cin XY 0 1 2 3 6 7 4 5 1 11 1 Cout S = XY(Cin) + XY(Cin) + XY(Cin) + XY(Cin) = X Y (Cin) Cout = XY + X(Cin) + Y(Cin) Designing full adder Slide 7 Resulting circuit Slide 8 XY YC-in C-out XC-in X X Y C-in Y YY Y XX X C-in C-in C-in XYC-in XYC-in Sum S XYC-in XYC-in X X X Y Y Y C-in Y C-in Full Adder XY S C-in C-out Alternative: full adder using AND-OR Slide 9 Ripple adder Speed limited by carry chain 2 per full adder 2n for an n-bit adder 2 per full adder 2n for an n-bit adder Approach: eliminate or reduce carry chain Carry look-ahead: compute Cin directly from external inputs Carry look-ahead: compute Cin directly from external inputs Q: Do we need C4 for a 4-bit 2s complement addition? Slide 10 Let C i+1 = (X i Y i )+ (X i +Y i ) C i = G i + P i C i For a 4-bit adder C 1 = G 0 + P 0 C 0 C 2 = G 1 + P 1 C 1 = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C 4 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 where G i = X i Y i P i = X i + Y i where G i = X i Y i P i = X i + Y i This is a 3 level circuit including generating the Gs and Ps Rule of thumb: one carry look-ahead circuit every 4-bit Rule of thumb: one carry look-ahead circuit every 4-bit Carry look-ahead adder Slide 11 Carry look-ahead circuit Gs and Ps are also useful for generating the sums Slide 12 16-bit carry ripple adder Slide 13 16-bit carry look-ahead adder Slide 14 Subtraction Recall our discussion on subtraction for 2s complement X Y = X + Y + 1 X Y = X + Y + 1 Invert all bits of Y and set C in to 1 Invert all bits of Y and set C in to 1 Example: 4-bit subtractor using 4-bit adder Add a control circuit in ALU s.t. same circuit can be used for both addition and subtraction 4-bit Adder X3 X2 X1 X0 D3 D2 D1 D0 C-in C-out C4 Y3 Y2 Y1 Y0 C0 = 1 S3 S2 S1 S0 Slide 15 Multipliers 8x8 multiplier Slide 16 Full-adder array Slide 17 Faster carry chain Slide 18 Binary Multiplication An n-bit X n-bit multiplier can be realized in combinational circuitry by using an array of n-1 n- bit adders where is adder is shifted by one position. For each adder one input is the multiplied by 0 or 1 (using AND gates) depending on the multiplier bit, the other input is n partial product bits. X3 X2 X1 X0 x Y3 Y2 Y1 Y0 __________________________ X3.Y0 X2.Y0 X1.Y0 X0.Y0 X3.Y1 X2.Y1 X1.Y1 X0.Y1 X3.Y2 X2.Y2 X1.Y2 X0.Y2 X3.Y3 X2.Y3 X1.Y3 X0.Y3 _______________________________________________________________________________________________________________________________________________ P7 P6 P5 P4 P3 P2 P1 P0 Slide 19 4x4 Array Multiplier