1 iki20210 pengantar organisasi komputer kuliah no. 23: aritmatika 18 desember 2002 bobby nazief...

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1 IKI20210 Pengantar Organisasi Komputer Kuliah No. 23: Aritmatika 18 Desember 2002 Bobby Nazief ([email protected]) Johny Moningka ([email protected]) bahan kuliah: http://www.cs.ui.ac.id/~iki20210/ Sumber : 1. Hamacher. Computer Organization, ed-4. 2. Materi kuliah CS61C/2000 & CS152/1997, UCB.

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Pengantar Organisasi Komputer2. Materi kuliah CS61C/2000 & CS152/1997, UCB.
*
Hex:
if human looking at long strings of binary numbers, its much easier to convert to hex and look 4 bits/symbol
Terrible for arithmetic; just say no
Binary:
To a computer, numbers always binary
Unsigned Numbers
So far, unsigned numbers
0 => +, 1 => -
Representation called sign and magnitude
*
Arithmetic circuit more complicated
Special steps depending whether signs are the same or not
Also, Two zeros
Sign and magnitude abandoned
Called one’s Complement
Note: postive numbers have leading 0s, negative numbers have leadings 1s.
What is -00000 ?
How many negative ones?
*
Obvious solution didn’t work, find another
What is result for unsigned numbers if tried to subtract large number from a small one?
Would try to borrow from string of leading 0s,
so result would have a string of leading 1s
With no obvious better alternative, pick representation that made the hardware simple: leading 0s positive, leading 1s negative
000000...xxx is >=0, 111111...xxx is < 0
This representation called two’s complement
*
2 N-1 non-negatives
2 N-1 negatives
. . .
. . .
One zero, 1st bit => >=0 or <0, called sign bit
but one negative with no positive –2,147,483,648ten
*
Two’s Complement Formula
Can represent positive and negative numbers in terms of the bit value times a power of 2:
d31 x -231 + d30 x 230 + ... + d2 x 22 + d1 x 21 + d0 x 20
Example
= 1x-231 +1x230 +1x229+... +1x22+0x21+0x20
= -231 + 230 + 229 + ... + 22 + 0 + 0
= -2,147,483,648ten + 2,147,483,644ten
*
Two’s complement shortcut: Negation
Invert every 0 to 1 and every 1 to 0, then add 1 to the result
Sum of number and its one’s complement must be 111...111two
111...111two= -1ten
Let x’ mean the inverted representation of x
Then x + x’ = -1 x + x’ + 1 = 0 x’ + 1 = -x
Example: -4 to +4 to -4
x : 1111 1111 1111 1111 1111 1111 1111 1100two
x’: 0000 0000 0000 0000 0000 0000 0000 0011two
+1: 0000 0000 0000 0000 0000 0000 0000 0100two
()’: 1111 1111 1111 1111 1111 1111 1111 1011two
+1: 1111 1111 1111 1111 1111 1111 1111 1100two
*
Two’s comp. shortcut: Sign extension
Convert 2’s complement number using n bits to more than n bits
Simply replicate the most significant bit (sign bit) of smaller to fill new bits
2’s comp. positive number has infinite 0s
2’s comp. negative number has infinite 1s
Bit representation hides leading bits;
sign extension restores some of them
16-bit -4ten to 32-bit:
1111 1111 1111 1100two
*
The outputs are Sumi, CarryOuti
Note: CarryIni+1 = CarryOuti
*
CarryOut = AB + ACin + BCin
implement gates for Sum
implement gates for CarryOut
Sum
A
B
CarryIn
CarryOut
Critical Path of n-bit Rippled-carry adder is n*CP
CP = 2 gate-delays (Cout = AB + ACin + BCin)
A0
B0
1-bit
FA
Sum0
CarryIn0
CarryOut0
A1
B1
1-bit
FA
Sum1
CarryIn1
CarryOut1
A2
B2
1-bit
FA
Sum2
CarryIn2
CarryOut2
A3
B3
1-bit
FA
Sum3
CarryIn3
CarryOut3
Numbers really have an infinite number of digits
with almost all being zero except for a few of the rightmost digits
Just don’t normally show leading zeros
If result of add (or -,*/) cannot be represented by these rightmost HW bits, overflow is said to have occurred
When CarryOut is generated from MSB
00000
00001
00010
11111
11110
A
B
S
G
P
A
B
S
G
P
A
B
S
G
P
C2 = G1 + G0 · P1 + C0 · P0 · P1
C3 = G2 + G1 · P2 + G0 · P1 · P2 + C0 · P0 · P1 · P2
G = G3 + P3·G2 + P3·P2·G1 + P3·P2·P1·G0
C4 = . . .
A B C-out
Cin
Names: suppose G0 is 1 => carry no matter what else => generates a carry
suppose G0 =0 and P0=1 => carry IFF C0 is a 1 => propagates a carry
Like dominoes
*
All carries can be obtained in 3 gate-delays:
1 needed to developed all Pi and Gi
2 needed in the AND-OR circuit
All sums can be obtained in 6 gate-delays:
3 needed to obtain carries
1 needed to invert carry
2 needed in the AND-OR circuit of Sum’s circuit
Independent of the number of bits (n)
4-bit Adder:
16-bit Adder:
¯ ¯ ¯ ¯ ¯ ¯
*
C1 = G0 + C0 · P0
C2 = G1 + G0 · P1 + C0 · P0 · P1
C3 = G2 + G1 · P2 + G0 · P1 · P2 + C0 · P0 · P1 · P2
G
P
G0
P0
C4 = . . .
C0
C
L
A
4-bit
Adder
4-bit
Adder
4-bit
Adder
Result will be correct, provided there’s no overflow
0 1 0 1 (+5)
+0 0 1 0 (+2)
0 1 1 1 (+7)
0 1 0 1 (+5)
+1 0 1 0 (-6)
1 1 1 1 (-1)
1 0 1 1 (-5)
+1 1 1 0 (-2)
11 0 0 1 (-7)
0 1 1 1 (+7)
+1 1 0 1 (-3)
10 1 0 0 (+4)
0 0 1 0 (+2) 0 0 1 0
0 1 0 0 (+4) +1 1 0 0 (-4)
1 1 1 0 (-2)
1 1 1 0 (-2) 1 1 1 0
1 0 1 1 (-5) +0 1 0 1 (+5)
10 0 1 1 (+3)
Subtraction:
*
- 4 5 = - 9 but ...
0
1
1
1
1
1
0
7
3
1
– 6
– 4
– 5
7
Well so far so good but life is not always perfect.
Let’s consider the case 7 plus 3, you will get 10.
But if you perform the binary arithmetics on our 4-bit adder you will get 1010, which is negative 6.
Similarly, if you try to add negative 4 and negative 5 together, you should get negative 9.
But the binary arithmetics will give you 0111, which is 7.
So what went wrong? The problem is overflow.
The number you get are simply too big, in the positive 10 case, and too small in the negative 9 case, to be represented by four bits.
+2 = 39 min. (Y:19)
Overflow Detection
Overflow: the result is too large (or too small) to represent properly
Example: - 8 < = 4-bit binary number <= 7
When adding operands with different signs, overflow cannot occur!
Overflow occurs when adding:
On your own: Prove you can detect overflow by:
Carry into MSB ° Carry out of MSB
0
1
1
1
0
0
1
1
0
1
1
1
1
1
0
7
3
1
– 6
–4
– 5
7
0
Recalled from some earlier slides that the biggest positive number you can represent using 4-bit is 7 and the smallest negative you can represent is negative 8.
So any time your addition results in a number bigger than 7 or less than negative 8, you have an overflow.
Keep in mind is that whenever you try to add two numbers together that have different signs, that is adding a negative number to a positive number, overflow can NOT occur.
Overflow occurs when you to add two positive numbers together and the sum has a negative sign. Or, when you try to add negative numbers together and the sum has a positive sign.
If you spend some time, you can convince yourself that If the Carry into the most significant bit is NOT the same as the Carry coming out of the MSB, you have a overflow.
+2 = 41 min. (Y:21)
Carry into MSB ° Carry out of MSB
For a N-bit Adder: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1]
A0
B0
1-bit
FA
Result0
CarryIn0
CarryOut0
A2
B2
1-bit
FA
Result2
CarryIn2
A3
B3
1-bit
FA
Result3
CarryIn3
CarryOut3
Overflow
X
Y
0
0
0
0
1
1
1
0
1
1
1
0
A1
B1
1-bit
FA
Result1
CarryIn1
CarryOut1
Recall the XOR gate implements the not equal function: that is, its output is 1 only if the inputs have different values.
Therefore all we need to do is connect the carry into the most significant bit and the carry out of the most significant bit to the XOR gate.
Then the output of the XOR gate will give us the Overflow signal.
+1 = 42 min. (Y:22)