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IKI10230Pengantar Organisasi KomputerBab 4.1: Input/Output & Interrupt

19 Maret 2003

Bobby Nazief (nazief@cs.ui.ac.id)Qonita Shahab (niet@cs.ui.ac.id)

bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/

Sumber:1. Hamacher. Computer Organization, ed-5.2. Materi kuliah CS152/1997, UCB.

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Input/Output: Gerbang Ke Dunia Luar

Processor (active)

Computer

Control(“brain”)

Datapath(“brawn”)

Memory(passive)

(where programs, data live whenrunning)

Devices

Input

Output

Keyboard, Mouse

Display, Printer

Disk (where programs, data live whennot running)

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Motivation for Input/Output

° I/O is how humans interact with computers

° I/O lets computers do amazing things:• Read pressure of synthetic hand and control

synthetic arm and hand of fireman

• Control propellers, fins, communicate in BOB (Breathable Observable Bubble)

• Read bar codes of items in refrigerator

° Computer without I/O like a car without wheels; great technology, but won’t get you anywhere

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I/O Device Examples and Speed

° I/O Speed: bytes transferred per second(from mouse to display: million-to-1)

° Device Behavior Partner Data Rate (Kbytes/sec)

Keyboard Input Human 0.01Mouse Input Human 0.02Line Printer Output Human 1.00Floppy disk Storage Machine 50.00Laser Printer Output Human 100.00Magnetic Disk Storage Machine 10,000.00Network-LAN I or O Machine 10,000.00Graphics Display Output Human 30,000.00

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What do we need to make I/O work?

° A way to connect many types of devices to the Proc-Mem

° A way to control these devices, respond to them, and transfer data

° A way to present them to user programs so they are useful

Proc Mem

PCI Bus

SCSI Bus

cmd reg.data reg.

Operating System

WindowsFiles

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Organisasi I/O

° ° °Prosesor Memori

Control LinesAddress LinesData Lines

Address Decoder

Control Circuits

Data & Status Registers

Input Device

I/O Interface

BUS

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A Bus is:

° shared communication link

° single set of wires used to connect multiple subsystems

Control

Datapath

Memory

ProcessorInput

Output

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Review: Organisasi Input/Output

Prosesor

Bus

SOUT

DATAOUT

Display

SIN

DATAIN

Keyboard

° I/O Device biasanya memiliki 2 register:• 1 register menyatakan kesiapan untuk menerima/mengirim data

(I/O ready), sering disebut Status/Control Register SIN, SOUT

• 1 register berisi data, sering disebut Data Register DATAIN, DATAOUT

° Prosesor membaca isi Status Register terus-menerus, menunggu I/O device men-set Bit Ready di Status Register (0 1)

° Prosesor kemudian menulis atau membaca data ke/dari Data Register

• tulis/baca ini akan me-reset Bit Ready (1 0) di Status Register

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Review: Contoh Program Input/Output

° Input: Read from keyboard Move #LOC,R0 ; Initialize memory

READ: TestBit #3,INSTATUS ; Keyboard (IN) ready?

Branch=0 READ ; Wait for key-inMove DATAIN,(R0) ; Read character

° Output: Write to displayECHO: TestBit #3,OUTSTATUS; Display (OUT) ready?

Branch=0 ECHO ; Wait for itMove (R0),DATAOUT; Write characterCompare #CR,(R0)+ ; Is it CR?

; Meanwhile, stores it

Branch≠0 READ ; No, get moreCall Process ; Do something

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Memory-mapped-I/O vs. I/O-mapped-I/O° Status & Data Registers are treated as memory

locations:• Called “Memory Mapped Input/Output”

• A portion of the address space dedicated to communication paths to Input or Output devices (no memory there)

• The registers are accessed by Load/Store instructions, just like memory

° Some machines have special input and output instructions that read-from and write-to Device Address Space:

• Called “I/O Mapped Input/Output”

• IN Rx,Device-Address ; Processor Device; Rx Rdevice-Address

• OUT Device-Address,Rx ; Device Processor; Rdevice-Address Rx

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Contoh Program Input/Output (I/O-mapped-I/O)

° Input: Read from keyboard Move #LOC,R0 ; Initialize memory

READ: In INSTATUS,R1 ; Read statusTestBit #3,R1 ; Keyboard (IN)

ready? Branch=0 READ ; Wait for key-inIn DATAIN,R1 ; Read characterMove R1,(R0) ; Store in memory

° Output: Write to displayECHO: In OUTSTATUS,R1; Read status

TestBit #3,R1 ; Display (OUT) ready?

Branch=0 ECHO ; Wait for itMove (R0),R1 ; Get the characterOut R1,DATAOUT ; Write itCompare #CR,(R0)+ ; Is it CR?

; Meanwhile, stores it

Branch≠0 READ ; No, get moreCall Process ; Do something

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Polling

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Processor-I/O Speed Mismatch

° 500 MHz microprocessor can execute 500 million load or store instructions per second, or 2,000,000 KB/s data rate

• I/O devices from 0.01 KB/s to 30,000 KB/s

° Input: device may not be ready to send data as fast as the processor loads it

• Also, might be waiting for human to act

° Output: device may not be ready to accept data as fast as processor stores it

° What to do?

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Program-Controlled I/O: Polling

° Input: Read from keyboard Move R1,#line ; Initialize memory

WAITK: TestBit STATUS,#0 ; Keyboard (IN) ready?

Branch=0 WAITK ; Wait for key-inMove R0,DATAIN ; Read character

° Output: Write to displayWAITD: TestBit STATUS,#1 ; Display (OUT) ready?

Branch=0 WAITD ; Wait for itMove DATAOUT,R0 ; Write characterMove (R1)+,R0 ; Store & advanceCompare R0,#$0D ; Is it CR?Branch≠0 WAITK ; No, get moreCall Process ; Do something

° Processor waiting for I/O called “Polling”

OUT IN

STATUSDATAIN

DATAOUT

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Cost of Polling?

° Assume for a processor with a 500-MHz clock it takes 400 clock cycles for a polling operation (call polling routine, accessing the device, and returning). Determine % of processor time for polling

• Mouse: polled 30 times/sec so as not to miss user movement

• Floppy disk: transfers data in 2-byte units and has a data rate of 50 KB/second. No data transfer can be missed.

• Hard disk: transfers data in 16-byte chunks and can transfer at 8 MB/second. Again, no transfer can be missed.

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% Processor time to poll mouse, floppy

° Times Mouse Polling/sec = 30 polls/sec

° Mouse Polling Clocks/sec = 30 * 400 = 12000 clocks/sec

° % Processor for polling: 12*103/500*106 = 0.002%

Polling mouse little impact on processor

° Times Polling Floppy/sec = 50 KB/s /2B = 25K polls/sec

° Floppy Polling Clocks/sec= 25K * 400 = 10,000,000 clocks/sec

° % Processor for polling: 10*106/500*106 = 2%

OK if not too many I/O devices

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% Processor time to hard disk

° Times Polling Disk/sec= 8 MB/s /16B = 500K polls/sec

° Disk Polling Clocks/sec= 500K * 400 = 200,000,000 clocks/sec

° % Processor for polling: 200*106/500*106 = 40%

Unacceptable

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Interrupt

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What is the alternative to polling?

° Wasteful to have processor spend most of its time “spin-waiting” for I/O to be ready

° Wish we could have an unplanned procedure call that would be invoked only when I/O device is ready

° Solution: use interrupt mechanism to help I/O. Interrupt program when I/O ready, return when done with data transfer

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I/O Interrupt

° An I/O interrupt is like a subroutine call except:• An I/O interrupt is “asynchronous”

• More information needs to be conveyed

° An I/O interrupt is asynchronous with respect to instruction execution:

• I/O interrupt is not associated with any instruction, but it can happen in the middle of any given instruction

• I/O interrupt does not prevent any instruction from completion

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Interrupt Driven Data Transfer

(1) I/Ointerrupt

(2) save PC

(3) interruptservice addr

Memory

addsubandor

userprogram

readstore...jr

interruptserviceroutine

(4)

(5)

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Interrupt Service Routine (Interrupt Handler)Main Program

Move #Line,PNTR ; Initialize buffer pointer.

Clear EOL ; Clear end-of-line indicator.

BitSet #2,CONTROL ; Enable keyboard interrupts.

BitSet #9,PS ; Set interrupt-enable bit in the PS.

…

Interrupt Service Routine

Read:

MoveMultiple RO-R1,-(SP) ; Save R0 & R1 on stack.

Move PNTR,R0 ; Load buffer pointer.

MoveByte DATAIN,R1 ; Get input character and

MoveByte R1,(R0)+ ; store it in the buffer.

Move R0,PNTR ; Update buffer pointer.

CompareByte #$0D,R1 ; Check if Carriage Return

Branch≠0 RTRN

Move #1,EOL ; Indicate end-of-line.

BitClear #2,CONTROL ; Disable keyboard interrupts.

RTRN:

MoveMultiple (SP)+,RO-R1 ; Restore R0 & R1.

Return-from-interrupt

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Benefit of Interrupt-Driven I/O

° 400 clock cycle overhead for each transfer, including interrupt. Find the % of processor consumed if the hard disk is only active 5% of the time.

° Interrupt rate = polling rate• Disk Interrupts/sec = 8 MB/s /16B

= 500K interrupts/sec

• Disk Transfer Clocks/sec = 500K * 400 = 200,000,000 clocks/sec

• % Processor for during transfer: 250*106/500*106= 40%

° Disk active 5% 5% * 40%2% busy

Determined by disk’s activity, whereas in Polling-driven I/O the Processor will be busy polling 40% of the time even if the disk is not active

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Instruction Set Support for I/O Interrupt

° Save the PC for return• To enable the “proper return” when the interrupt has been served

• AVR uses the stacks

° Where to go when interrupt occurs?• To allow “proper branch” to the service routine

• AVR defines:

- Locations 0x000 – 0x002 for external interrupts

- Locations 0x003 – 0x00C for internal interrupts

° Determine cause of interrupt?• To guarantee “proper service routine” serving “proper interrupt”

• AVR uses vectored interrupt, which associates the location of the interrupt service routine (see above) with the device that causes it

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Interrupt Hardware

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Interrupt Request

Processor

INTR1

° I/O Devices interrupt processor through a single line known as Interrupt Request signal (INTR)

° To serve n devices, the line uses wired-or connection that allows any interrupting device to activate the signal

• any INTRi is switched on, INTR will become TRUE

INTRnINTR2

Vdd

INTR

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Sequence of Events during Interrupt

1. The device activates interrupt request signal.

2. The processor interrupts the program currently being executed.

3. Interrupts are disabled by changing the control bits in the PS.

4. The device is informed that its request has been recognized, and in response, it deactivates the interrupt request signal.

5. The action requested by the interrupt is performed by the interrupt service routine.

6. Interrupts are enabled and execution of the interrupted program is resumed.

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Multiple Devices/Interrupts° How to handle simultaneous interrupt requests?

• Need to have priority scheme

° Which I/O device caused exception?• Need to convey the identity of the device generating the interrupt

° Can processor avoid interrupts during the interrupt routine?

• In general, interrupts are disabled whenever one is being serviced; interrupts will be enabled after the service is completed

• However, occasionally a more important interrupt may occur while this interrupt being served

° Who keeps track of status of all the devices, handle errors, know where to put/supply the I/O data?

• In general, these is one of the tasks of Operating System

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Device Identification

CPU

Device 1 Device NDevice 2

INTR1

° The Interrupting Device may provide its identity through:

• Interrupt-Request (IRQ) bit in its Status Register, which will be evaluated one-by-one by the processor (polling)

• Sending special code the the processor over the bus (vectored interrupt)

INTRnINTR2

wired-OR

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Prioritized Interrupt: Daisy Chain Scheme

° Advantage: simple

° Disadvantages:• Cannot assure fairness:

A low-priority device may be locked out indefinitely

CPU

Device 1HighestPriority

Device NLowestPriority

Device 2

INTA

Release

INTR

wired-OR

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Prioritized Interrupt: Priority Groups

CPU

Device 1 Device NDevice 2

INTA1

INTR1

° Interrupt Nesting: an Interrupt Service Routine may be interrupted by other, higher-priority interrupt

INTA2INTR2

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Exceptions

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Exceptions

° Interrupt is only a subset of Exception• Exception: signal marking that something “out of the ordinary”

has happened and needs to be handled

° Interrupt: asynchronous exception• Unrelated with instruction being executed

° Trap: synchronous exception• Related with instruction being executed

• To recover from errors: Illegal Instruction, Divide By Zero, …

• To debug a program

• To provide privilege (for Operating System)

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I/O & Operating System° The I/O system is shared by multiple programs using the

processor • OS guarantees that user’s program accesses only the portions

of I/O device to which user has rights (e.g., file access)

° Low-level control of I/O device is complex because requires managing a set of concurrent events and because requirements for correct device control are often very detailed

• OS provides abstractions for accessing devices by supplying routines that handle low-level device operations

° I/O systems often use interrupts to communicate information about I/O operations

• OS handles the exceptions generated by I/O devices (and arithmetic exceptions generated by a program)

° Would like I/O services for all user programs under safe control

• OS tries to provide equitable access to the shared I/O resources, as well as schedule accesses in order to enhance system performance

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I/O – OS – User’s Program

I/O Device

User’sProgram

I/OServices

DeviceDriver

OS

getchar(); System.in.readLine();putchar(); System.out.println();

DeviceDriver

DeviceDriver

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OS Interrupt Services

OSINIT Set interrupt vectorsTime-slice clock SCHEDULERTrap OSSERVICES VDT interrupts IODATA

OSSERVICES Examine stack to determine requested operation

Call appropriate routine

SCHEDULER Save current contextSelect a runnable processRestore saved context of new processPush new values for PS and PC on stackReturn from interrupt

SCHEDULEROSSERVICES

IODATA……

PC

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I/O ROUTINES & DEVICE DRIVER

IOINIT Set process status to BlockedInitialize memory buffer address pointerCall device driver to initialize device & enable

interrupts in the device interface (VDTINIT)

Return from subroutine

IODATA Poll devices to determine source of interruptCall appropriate device driver (VDTDATA)If END = 1, then set process status to RunnableReturn from interrupt

VDTINIT Initialize device interfaceEnable interruptsReturn from subroutine

VDTDATA Check device statusIf ready, then transfer characterIf character = CR, then set END = 1;

else set END = 0Return from subroutine

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Contoh: Main Program.cseg

.org INT0addr

rjmp ext_int0 ;External interrupt handler

.org OVF0addr

rjmp tim0_ovf ;Timer0 overflow handler

main:

Do some initializations

rcall uart_init ;Init UART

sei ;Enable interrupts

idle:

sbrs u_status,RDR ;Wait for Character

rjmp idle

Do the work

wait:

sbrc u_status,TD ;Wait until data is sent

rjmp wait

Wrap it up

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Contoh: Interrupt Handlerext_int0:

ldi u_status,1<<BUSY;Set busy-flag (clear all others)

Do some work

ldi u_tmp,1<<TOIE0 ;Set bit 1 in u_tmp

out TIFR,u_tmp ; to clear T/C0 overflow flag

out TIMSK,u_tmp ; and enable T/C0 overflow interrupt

Do more work

clr u_bit_cnt ;Clear bit counter

out GIMSK,u_bit_cnt ;Disable external interrupt

reti

tim0_ovf:

sbrs u_status,TD ;if transmit-bit set

Do something

ldi u_tmp,1<<INT0 ;(u_bit_cnt==9):

out GIMSK,u_tmp ;Enable external interrupt

clr u_tmp

out TIMSK,u_tmp ;Disable timer interrupt

cbr u_status,(1<<BUSY)|(1<<TD) ;Clear busy-flag and transmit-flag

reti