312 • 2014 IEEE International Solid-State Circuits Conference

ISSCC 2014 / SESSION 18 / BIOMEDICAL SYSTEMS FOR IMPROVED QUALITY OF LIFE / 18.2

18.2 A Fully-Implantable Cochlear Implant SoC with Piezoelectric Middle-Ear Sensor and Energy-Efficient Stimulation in 0.18µm HVCMOS

Marcus Yip1, Rui Jin1, Hideko Heidi Nakajima2,3, Konstantina M. Stankovic2,3, Anantha P. Chandrakasan1

1Massachusetts Institute of Technology, Cambridge, MA, 2Harvard Medical School, Boston, MA, 3Massachusetts Eye and Ear Infirmary, Boston, MA

A cochlear implant (CI) is a device that electrically stimulates the auditory nerveto restore hearing in people with profound hearing loss. Conventional CIs rely onan external unit comprising a microphone and sound processor to pick up andencode sound. The external unit raises concerns with social stigma and limitsusage in the shower or during water sports, motivating the need for a fully-implantable (i.e., invisible) cochlear implant (FICI). The limited energy storagecapacity of the implanted system requires low-power (<1mW total power) soundprocessing and auditory nerve stimulation to enable operation from an implantedbattery that is wirelessly recharged only once daily. Recent state-of-the-art ICsare typically designed for external microphone-based CIs and do not require theneural stimulator to be on the same chip [1]. Prior implantable acoustic sensorssuch as accelerometers sense the sound-induced vibration of the middle ear, butthis approach has limited sensitivity and requires several mW of power for thesensor itself [2].

To address the above issues, this paper presents a system-on-chip (SoC) for aFICI that advances the state-of-the-art in several ways. First, low-powerimplantable acoustic sensing is achieved by interfacing the SoC to a piezoelectricsensor that is mounted at the umbo of the malleus within the middle ear, andthis is demonstrated with measurements from human cadaveric temporal bones.Second, a highly-reconfigurable digital sound processor enables system powerscalability by scaling the number of spectral channels. Third, simulations with anauditory nerve fiber model from [3] are used to determine energy-optimal biphasic stimulation pulses [4], which are delivered to the nerve through an arbitrary waveform neural stimulator. The resulting stimulation power savings(over the conventional rectangular pulse) transfer directly to overall systempower savings because stimulation power typically dominates [4]. The SoC prototyped in 0.18μm HVCMOS integrates implantable acoustic sensing, soundprocessing, and neural stimulation on one chip to minimize the implant size anddemonstrate proof-of-concept for a FICI.

Fig. 18.2.1 shows a block diagram of the FICI SoC. A piezoelectric sensor front-end (PZFE) conditions the signal from the sensor, which is a measure of thesound-induced motion of the umbo. The signal is digitized by a low-power 9b 16kS/s SAR ADC, and a reconfigurable sound processor implements the well-known Continuous Interleaved Sampling (CIS) sound processing strategy. It hasbeen shown that the speech recognition scores of CI users improve with thenumber of electrodes but plateaus after 7 or 8 [5]. Therefore, in this work, thenumber of channels can be reconfigured between 8, 6, or 4 to enable a power-performance tradeoff, and all processor parameters are programmable to enablea patient-specific fit. Finally, a neural stimulator is implemented with a singlecurrent source that is interleaved among all electrodes at 1000 pulses/sec perelectrode, and a high-voltage switch matrix selects the active electrode. Arbitrarywaveforms are generated with a digital arbitrary waveform controller.

The details of the 3-stage PZFE are shown in Fig. 18.2.1. The first stage is acharge amplifier with a gain of CP/C1f and bandwidth of 1/(CPR1f), where CP is thesensor capacitance, and C1f and R1f are a programmable capacitor and resistorto accommodate a range of sensor sizes. The second stage provides additional programmable gain and filtering, and the third stage level shifts andperforms single-ended to differential conversion. The PZFE is tested by mounting the sensor on a human cadaveric temporal bone as shown in Fig.18.2.2. Sound is generated in the ear canal with a speaker, and a probe microphone, laser Doppler vibrometer, and the SoC are used to measure the earcanal pressure, umbo velocity, and piezoelectric sensor output voltage respectively to characterize the channel. The PZFE consumes only 10.3μW from1.5V and can detect sounds from 300Hz to 6kHz over a 50dB dynamic rangefrom 40 to 90dB SPL (Fig. 18.2.2), which is adequate for speech.

Figure 18.2.3 shows a block diagram of the reconfigurable CIS sound processor.A digital approach is chosen to provide more programmability over analogapproaches, and allow voltage scaling down to 0.6V for digital power savings.The processor spectrally decomposes the signal with a log-spaced filter bank toemulate natural hearing, and the output of each channel represents its log spectral energy and is used to modulate the pulse train on the correspondingelectrode. In this work, the gain, rectification type, amount of logarithmic compression, and patient threshold and most-comfortable-level are all programmable. Furthermore, since the channel bandwidths are log-spaced, a 3-stage decimation filter and multi-rate filter bank are used to minimize the number of taps while achieving the required selectivity. Finally, the number ofchannels can be reconfigured by clock-gating a subset of channels, which is crucial for enabling linear power reduction in the stimulator. For example, onlychannels A/C/E/G are active in 4-channel mode. In order to adjust the filter bandwidths for each mode, the filter bank uses 3 types of reconfigurable FIR filters: FIR Type 1, 2, and 3 (e.g., Type 3 has 3 levels of reconfigurability).

To address the need for energy-efficient stimulation, energy optimization of thestimulation waveform using nerve fiber simulations based on [4] is performed,but with a focus on CI specific parameters and without constraint on eitherphase of the biphasic pulse. An arbitrary waveform stimulator shown in Fig.18.2.4 is designed to realize the desired energy-optimal waveform. The core ofthe stimulator is a 6b current source with high output impedance and voltagecompliance using a voltage-controlled resistor (VCR) operating from 3.3V [6]. Alow-power 0.6V digital controller drives a high-speed current-steering DAC togenerate near-arbitrary waveforms with 8 steps/phase. The shape of the pulsecan be programmed with 16 4b values (w00[3:0] to w15[3:0]) representing theweight of each step, and the phase width is determined by the period of φHI. Thestimulation current flows from a high voltage supply (VMID=5-10 V) to accommo-date high electrode impedances, and switches SA/SiA, SC/SiC, Si, and SIPG of theswitch matrix are used to control the anodic and cathodic phases, shorting peri-od, and inter-phase gap respectively for each electrode Ei. Fig. 18.2.4 (bottom)shows measured current pulses on each electrode, and the energy-optimalwaveform at 31.25μs/phase.

Figure 18.2.5 (left) shows the measured spectrogram of the sound processorreconfigured between 4 and 8-channel modes with an exponential chirp input.Since the channels are log-spaced, the spectrograms are linear with time asexpected. Hearing with a cadaver ear is also demonstrated by using the mountedsensor and SoC to process a speech clip generated in the ear canal. Figure18.2.5 (right) shows the input speech spectrogram and the measured chip output spectrogram. A die micrograph of the SoC is shown in Fig. 18.2.7, andthe measured scalability of the stimulation power with chip settings, and measured SoC power breakdown are shown in Fig. 18.2.6. The stimulationpower increases with the pulse width and number of channels, and decreases by20-to-30% when using the optimal waveform from nerve fiber simulations compared to the rectangular waveform. Under typical conditions, the PZFE andsound processor consume 12μW, while the 8-channel stimulator consumes560μW with typical speech input, meeting the 1mW requirement [1]. Since thestimulation power represents 98% of the system power, the power savings fromthe energy-optimal waveform transfer directly to the system. Overall, hearingwith a cadaver ear is demonstrated with the SoC, which integrates implantablesensing, processing, and efficient stimulation to show feasibility for a FICI.

References:[1] R. Sarpeshkar, et al., “An Analog Bionic Ear Processor with Zero-CrossingDetection”, ISSCC Dig. Tech. Papers, Feb. 2005, pp. 78-79.[2] D.J. Young, et al., “MEMS Capacitive Accelerometer-Based Middle EarMicrophone”, IEEE TBME, vol. 59, no. 12, pp. 3283-3292, Dec. 2012.[3] D.M. Whiten, “Electro-anatomical models of the cochlear implant,” Ph.D. the-sis, Massachusetts Institute of Technology, Cambridge, MA, Feb. 2007.[4] A. Wongsarnpigoon, et al., “Energy-efficient waveform shapes for neuralstimulation revealed with genetic algorithm”, JNE, vol. 7, no. 4, Aug. 2010.[5] Q.J. Fu, et al., “Effects of noise and spectral resolution on vowel and consonant recognition: Acoustic and electric hearing,” J. Acoust. Soc. Am., vol.104, no. 6, pp. 3586-3596, Dec. 1998.[6] M. Ghovanloo, et al., “A Compact Large Voltage-Compliance High Output-Impedance Programmable Current Source for Implantable Microstimulators”,IEEE TBME, vol. 52, no. 1, pp. 97-105, Jan. 2005.

978-1-4799-0920-9/14/$31.00 ©2014 IEEE

313DIGEST OF TECHNICAL PAPERS •

ISSCC 2014 / February 11, 2014 / 2:00 PM

Figure 18.2.1: Block diagram of the fully-implantable cochlear implant SoC.Figure 18.2.2: Test setup and characterization results from a piezoelectricsensor mounted on a human cadaveric temporal bone.

Figure 18.2.3: Block diagram of the 0.6V digital reconfigurable CIS soundprocessor.

Figure 18.2.5: Measured spectrogram with a chirp input (left), and demonstration with a sensor mounted on a human cadaveric middle ear(right).

Figure 18.2.6: Measured stimulator power during typical speech, and overallSoC power breakdown.

Figure 18.2.4: Arbitrary waveform stimulator and HV electrode switch matrixwith measured current waveforms.

VP

CP

Arbitrary waveform current stimulator

Middle ear-mounted

piezoelectricsensor

HV electrodeswitch matrix

SA SC

VMID

E1 - E88

0.6 V Reconfigurable sound processor

6

C2i=105p

R2ia R2ib

C2f =816f

R2f [2:0]=1.1-30M

0.5M 0.5M

C1f [2:0]=6-66p

R1f =88.4M

R1i [3:0]

1-100kVREF

VO1VO2

VREF

VCM

10M

10M

10M

10M

10M

10M

SARADC

Fully-implantable CI SoC

Waveformselect

Channelselect

0.6 V Digital arbitrary waveform control

3-st

age

deci

mat

ion

filte

r

9

1.5 V Piezoelectric sensor front-end (PZFE)

Charge amplif ier Programmable-gain amplifier ADC driver (S2D)

Config. registers

VREF

0.6 V, 9-bit16 kS/s

ECOM

SiC[7:0] SiA[7:0]

LaserDoppler

vibrometerProbe

microphone

Speaker

Sensormount

Temporalbone

holder

SoCprototype

10−8

10−7

10−6

10−5

10−4

10−3

10−2

Frequency [kHz]

Cha

rge

Am

plifi

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utpu

t [V r

ms]

90 dB SPL80 dB SPL70 dB SPL60 dB SPL50 dB SPL40 dB SPL

1 100.3 3

40 dB SPL

90 dB SPL

3-stage decimation filterFromADC

@16 kHz

2Half-bandFIR LPF 2Half-band

FIR LPF 2Half-bandFIR LPF9

Logcomp.

Ch HType 1

16

6

Logcomp.

Ch GType 3

16

6

Logcomp.

Ch FType 2

8

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Logcomp.

Ch EType 3

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Logcomp.

Ch DType 1

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Logcomp.

Ch CType 3

4

6

Logcomp.

Ch BType 2

2

6

Logcomp.

Ch AType 3

2

6

@ 16 kHz @ 8 kHz @ 4 kHz @ 2 kHz

Reconfigurable multi-rate FIR filter bank

6-bit output @ 1 kHz analysis rate

Patientfitting

Patientfitting

Patientfitting

Patientfitting

Patientfitting

Patientfitting

Patientfitting

Patientfitting

High-frequencychannels

Low-frequencychannels

Env.detect

Env.detect

Env.detect

Env.detect

Env.detect

Env.detect

Env.detect

Env.detect

IDAC

MHV

VMID

Ecom

SIPG

E1 E2 E8

S1

SCSA

S1AS1C

S8AS8C

S2AS2C

S2 S8

D[5:0]

100 mV

6-bit current source

DAC VCR

HV electrode switch matrix

w15[3:0]

Stepcounter

w00[3:0]

chA[5:0]

chH[5:0]

Channelselect

Electrode selectstate machine

6

4

ΦLO (1 kHz)

FromSPI

Fromsound

processor

0.6 V Digital arbitrary waveform control

Waveformselect

ΦHI (10-20 kHz)

ΦHI (10-20 kHz)ΦW = 16 x ΦHI

−1 −0.5 0 0.5 1Time [ms]

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ctro

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1

2

3

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5

6

7

8

−40 −20 0 20 40−1

−0.5

0

0.5

1

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rent

[mA

]

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Energy-optimal biphasicwaveform @ 31.25 µs/phase

Time [sec]

Cha

nnel

4 5 6 7 8

1

2

3

4 Measured (4 ch)

Time [sec]

Cha

nnel

3 4 5 6

2

4

6

8 Measured (8 ch)

Exponential chirp @ ADC input

Time [sec]

Freq

uenc

y [k

Hz]

0 0.5 1 1.50

2

4

6

8Input to ear canal

Time [sec]

Cha

nnel

0 0.5 1 1.5

2

4

6

8 Measured (8 ch)

Ear canal speech input with sensormounted on human cadaveric middle ear

Her hus- band brought some flow- ers

Measured SoC power breakdown

System component Supply voltage [V]

Power [µW]

Piezoelectric sensor front-end 1.5 10.3

SAR ADC 0.6 0.3

Digital CIS sound processor 0.6 (8 / 6 / 4 chan) 1.6 / 1.3 / 1.1

Stimulator and switch matrix Digital waveform control

Level shifters Current source circuits

Stimulator supply (VMID=5-10V) HV switch matrix control (7-12V)

0.6 1.8 3.3 7 9

(8 / 6 / 4 chan) 0.35 / 0.32 / 0.30 0.38 / 0.29 / 0.20

75 / 57 / 40 479 / 351 / 226 5.4 / 4.1 / 2.7

Total (8-channel mode) Total (6-channel mode) Total (4-channel mode)

572 425 281

Measured neural stimulation power

8 6 40

200

400

600

800

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Pow

er [µ

W]

25 µs/phase

8 6 40

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400

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Channel Mode

Pow

er [µ

W]

Rectangular Optimal

18

• 2014 IEEE International Solid-State Circuits Conference 978-1-4799-0920-9/14/$31.00 ©2014 IEEE

ISSCC 2014 PAPER CONTINUATIONS

Figure 18.2.7: Die micrograph of the prototype SoC.

3.6 mm

3.6

mm

Reconf.CIS

soundprocessor

Piezoelectric

HVstim. & switch matrix

SPIA

rbitr

ary

wav

efor

m

inte

rface

ADCBias

sensor front-end