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“CARRIZO” ISSCC 2015

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  • CARRIZO ISSCC 2015

  • 2 | CARRIZO | ISSCC 2015 |

    CAUTIONARY STATEMENT

    The following presentation contains forward-looking statements concerning Advanced Micro Devices, Inc. (AMD or the Company) including, among other things: timing, availability, features and functionality of the AMD Carrizo APU, AMD Carrizo L SoC; AMDs ability to improve its energy efficiency technologies for its future products; AMDs goal to improve energy efficiency for AMD mobile platforms by at least 25 times by 2020; and AMDs goal to outpace historical energy efficiency trends, which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act. Forward-looking statements are commonly identified by words such as "would," "may," "expects," "believes," "plans," "intends," "projects," and other terms with similar meaning. Investors are cautioned that the forward-looking statements in this press release are based on current beliefs, assumptions and expectations, speak only as of the date of this press release and involve risks and uncertainties that could cause actual results to differ materially from current expectations. Investors are cautioned that the forward-looking statements in this presentation are based on current beliefs, assumptions and expectations, speak only as of the date of this presentation and involve risks and uncertainties that could cause actual results to differ materially from current expectations. Risks include that Intel Corporation's pricing, marketing and rebating programs, product bundling, standard setting, new product introductions or other activities may negatively impact AMDs plans; that AMD will require additional funding and may be unable to raise sufficient capital on favorable terms, or at all; that customers stop buying AMDs products or materially reduce their operations or demand for AMDs products; that AMD may be unable to develop, launch and ramp new products and technologies in the volumes that are required by the market at mature yields on a timely basis; that AMDs third-party foundry suppliers will be unable to transition AMDs products to advanced manufacturing process technologies in a timely and effective way or to manufacture AMDs products on a timely basis in sufficient quantities and using competitive process technologies; that AMD will be unable to obtain sufficient manufacturing capacity or components to meet demand for its products or will not fully utilize its projected manufacturing capacity needs at GLOBALFOUNDRIES, Inc. (GF) microprocessor manufacturing facilities; that AMDs requirements for wafers will be less than the fixed number of wafers that it agreed to purchase from GF or GF encounters problems that significantly reduce the number of functional die it receives from each wafer; that AMD is unable to successfully implement its long-term business strategy; that the completion and impact of the 2014 Restructuring Plan and AMDs transformation initiatives could adversely affect AMD; that AMD inaccurately estimates the quantity or type of products that its customers will want in the future or will ultimately end up purchasing, resulting in excess or obsolete inventory; that AMD is unable to manage the risks related to the use of its third-party distributors and add-in-board (AIB) partners or offer the appropriate incentives to focus them on the sale of AMDs products; that AMD may be unable to maintain the level of investment in research and development that is required to remain competitive; that there may be unexpected variations in market growth and demand for AMDs products and technologies in light of the product mix that it may have available at any particular time; that global business and economic conditions will not improve or will worsen; that PC market conditions will not improve or will worsen; that PC market conditions will not improve or will worsen; that demand for computers will be lower than currently expected; and the effect of political or economic instability, domestically or internationally, on AMDs sales or supply chain. Investors are urged to review in detail the risks and uncertainties in the Company's Securities and Exchange Commission filings, including but not limited to the Quarterly Report on Form 10-Q for the quarter ended September 27, 2014.

  • 3 | CARRIZO | ISSCC 2015 |

    Single, scalable infrastructure shared with Carrizo-L

    New Excavator core optimized for low power notebook/convertible form factors

    Next Generation AMD Radeon Graphics Core Next architecture with support for Mantle, DirectX 12, and Dual Graphics

    Single-chip integration of the APU and the Southbridge onto a single die

    Significant performance and battery life improvements. First processor in the world with full HSA 1.0 support

    AMD Secure Processor, leveraging ARM TrustZone technology for Enterprise-class security

    NEW PERFORMANCE MOBILE APU CARRIZO

    NEXT GENERATION PERFORMANCE APUs WITH FULL HSA CAPABILITY

  • 4 | CARRIZO | ISSCC 2015 |

    INTRINSIC ENERGY EFFICIENCY WITH ACCELERATED PROCESSORS (APU)

    75.0

    80.0

    85.0

    90.0

    95.0

    100.0

    75.0

    80.0

    85.0

    90.0

    95.0

    100.0

    75.0

    80.0

    85.0

    90.0

    95.0

    100.0

    GPU-centric Balanced CPU-centric

    CPU GPU Power Trading

    GPU Power CPU Power

    Combines CPUs, GPU and multi-media accelerators on a single die

    APUs are optimized for greater efficiency

    Efficient, fine-grained power management between CPU and GPU

    CPU GPU communication power dramatically reduced relative to separate chips

    Shared memory interface helps save power

    Temperature Distribution Plots

    GPU

    Dual Core x86 Module

    Dual Core x86 Module

    L2 CacheL2 Cache

    UNBGMC

    DDR3 Controller

    Multimedia

  • 5 | CARRIZO | ISSCC 2015 |

    AMD APU ENERGY EFFICIENCY WITH HSACARRIZO IS THE FIRST FULLY HSA COMPLIANT SOC

    COMPUTE CAPACITY TREND IN PCs

    Source: AMD Internal data

    0

    100

    200

    300

    400

    500

    600

    2010 2011 2012 2013 2014G

    FLO

    PS

    Product Year

    CPU GFLOPs GPU GFLOPs

    PCMark7

    PCMark8 v2

    FUTURE

    Example Improvement from GPU-Compute

    1st APU

    WHAT DOES THIS MEAN FOR POWER?

    Many workloads execute more efficiently using GPU compute resources rather than CPU only

    E.g. video indexing, natural human interfaces, pattern recognition

    For the same power, much better performance: lower energy per operation greater efficiency

    INTEGRATED GPU TREND

    CPU TREND

  • 6 | CARRIZO | ISSCC 2015 |

    POWER OPTIMIZED CPU EXCAVATOR WITH HIGH DENSITY LIBRARY DESIGN

    Steamroller Library Implementation Excavator High-density Library Design

    L2

    XV

    0.40

    0.50

    0.60

    0.70

    0.80

    0.90

    1.00

    1.10

    0.0W 5.0W 10.0W 15.0W 20.0W 25.0WNo

    rmal

    ize

    d F

    req

    ue

    ncy

    Power Per Core Pair

    SteamRoller_x86-64 CPU High performance library

    Excavator_x86-64 CPU High density libraryHP Library HD Library

    Floating PointScheduler38%

    FMAC 35%

    I-Cache Control35%

    High Performance vs. High Density Cell Example

    Prior generation CPU-centric tapered metal stack

    General purpose GPU-oriented stack enables greater density

    Achieves 23% area reduction, and lower power in the same 28nm technology node

    L2L2

    SR

  • 7 | CARRIZO | ISSCC 2015 |

    CARRIZO LOW POWER OPTIMIZED GRAPHICS

    0.0W 5.0W 10.0W 15.0W 20.0W 25.0W 30.0W

    No

    rmal

    ized

    Fre

    qu

    ency

    Power (8 GCN core GFX engine)

    High density power optimized High perf legacy design

    18% leakage reduction and timing with faster RVT devices enables 10% higher frequency at same power level, or up to 20% lower power at same frequency

    34.9%

    23.7%

    8.2%

    32.7%

    0.3%

    0.01

    0.1

    1

    10

    0.6 0.7 0.8 0.9 1 1.1 1.2

    No

    rmal

    ize

    d Io

    ff

    Normalized Ion

    high-density device selection high-performance device selection

    28nm universal curve

    48.8%

    43.2%

    7.9%

    0.1%

    0.3%

    Leakage reduced with heavy use of high Vt devices

    Speed set by faster devices

    28nm device suite

  • 8 | CARRIZO | ISSCC 2015 |

    VOLTAGE ADAPTIVE OPERATION

    Voltage adaptive feature applied to both CPU and GPU in Carrizo results in 19% and 10% power savings respectively

    Vdd above threshold

    Vdd drops below thresholdResponse Time < 1 nano-second

    Traditional margined frequency

    Operating frequencytemporarily decreases

    ~ 5%FrequencyBenefit

    Vdd Supply

    Delivering low noise voltage to high performance CPUs, GPUs and APUs has always been a challenge for the industry

    The variations that happen are typically about 10% of the nominal value that means at least 20% power is wasted covering these voltage variations (power goes as the square of voltage)

    AMDs unique voltage adaptation feature recovers much of that wasted power by operating at the average voltage and quickly reducing frequency for the brief periods when the voltage reduces

    0.0%

    5.0%

    10.0%

    15.0%

    20.0%

    25.0%

    1 1.15 1.2 1.3 1.33 1.4 1.5 1.65 1.7

    Pe

    rcen

    t P

    ow

    er

    Savi

    ngs

    Normalized Clock Frequency

    Adaptive Clocking Power Savingswith Voltage Adaptive feature vs. without

    CPU Power Savings GPU Power Savings

  • 9 | CARRIZO | ISSCC 2015 |

    AVFS TO OPTIMIZE PERFORMANCE PER WATT

    Excavator core incorporates

    10 AVFS modules containing

    ~500 frequency sensing paths

    0.40

    0.50

    0.60

    0.70

    0.80

    0.90

    1.00

    1.10

    0.0W 5.0W 10.0W 15.0W 20.0W 25.0W

    No

    rmal

    ize

    d F

    req

    uen

    cy

    Power Per Core Pair

    SteamRoller_x86-64 CPU High performance library

    Excavator_x86-64 CPU High density library

    Excavator High Density library AVFS

    AVFS provides additional power reduction at a given performance level over the High Density library gains

    Reliably extract the true silicon speed capability of CPU Includes effects of part-to-part processing, temperature and power delivery

    Add both a voltage and frequency sensor to existing power and temperature sensors

    Enables accurate setting of the optimal operating point for a given power or performance level across process, voltage and temperature ranges

    Improved energy efficiency across the entire voltage/temperature operating range

  • 10 | CARRIZO | ISSCC 2015 |

    RUN-TIME ACCESS TO LOW POWER STANDBY STATE

    The S0i3 state achieves the same power level as the legacy S3 state, traditionally known as standby which is very time-consuming to enter and exit because it requires operating system intervention.

    This state has almost all of the APU silicon power-gated and all relevant I/O devices in their low-power states, driving platform power to extremely low levels.

    By enabling access to this state on the fly, under the control of power management, the APU can achieve standby equivalent power levels transparently at sub-second time frames

    Lower average power consumption for typical use conditions.

    Boost Active Sustained Idle S0i3

    AP

    U P

    ow

    er

    Power vs. State

    < 50mW

    GFX

    IO

    ACP FCH

    NBPLL

    Co

    re

    Co

    re

    Co

    re

    Co

    re

    GFX

    IO

    ACP FCH

    NBPLL

    Co

    re

    Co

    re

    Co

    re

    Co

    re

    GFX

    IO

    ACP FCH

    NBPLL

    Co

    re

    Co

    re

    Co

    re

    Co

    re

    I/O

    < 1.5W

    > 10 W

  • 11 | CARRIZO | ISSCC 2015 |

    DRAMATIC IMPROVEMENTS IN ENERGY EFFICIENCY

    TRENDS IN THE ENERGY EFFICIENCY OF COMPUTATION1

    IMPROVEENERGY

    EFFICIENCYfor AMD mobile platforms

    1

    10

    100

    1000

    10000

    100000

    1000000

    10000000

    1985 1990 1995 2000 2005 2010 2015 2020

    Effi

    cien

    cy R

    ela

    tive

    to

    19

    85

    (1

    98

    5=1

    .0)

    Post 1946 historical trend 2000 to 2009 historical energy efficiency

    Efficiency growth starts to fall off after 2000

    AMD goal: outpace the historical trend by 70%+

    2

    Energy use drops While performance increases = Increased efficiency

    by at least

    25TIMES

    GOAL BY 2020

  • 12 | CARRIZO | ISSCC 2015 |

    CARRIZO TAPS INTO A DEEP PIPELINE OF IMPROVEMENTS

    AMD has been building a pipeline of power focused IP for many years

    Watch for more leading edge innovations enabling accelerated power gains in the future on all product lines

    2013201220112010

    Dynamic power tracking and management with DVFS

    Thermal aware power

    management

    Platform aware dynamic thermal management

    Fine grained power gating

    Dynamic CPU GPU power sharing

    2014

    Dynamic thermal tracking for short

    term boost

    Finer grained voltage planes

    Voltage-adaptive frequency

    scaling

    ACPI driven workload specific optimization

    Intelligent boost andPerformance aware energy

    optimization

    Finer grained power tracking, increased voltage granularity

    2015

    Video encode acceleration

    Video decode acceleration

    Audio acceleration

    Power efficient APU architecture integrating GPU+CPU and accelerators

    In market In product In development

    2016

    Environment and reliability aware

    boost

    Advanced bandwidth

    compression

    Inter-frame power gating

    Per-IP adaptive voltage

    Per part adaptive voltage

    Workload aware energy optimization

    Integrated voltage regulation

    OpenCL GPU compute moving to full HSA enabled programming

    "Puma" "Tigris" "Danube""Llano"

    "Trinity""Richland"

    "Kaveri"

    "Carrizo"

    2008 2009 2010 2011 2012 2013 2014 2015

    Ener

    gy E

    ffic

    ien

    cy

    Typical-Use Energy Efficiency

  • 13 | CARRIZO | ISSCC 2015 |

    High density design library resulting in 29% more transistors than Kaveri in approximately the same die area

    3.1 billion transistors

    Excavator cores: 5% more IPC at 40% less power and 23% less area

    H.265 support and > 3.5x transcode performance of Kaveri

    Device selection and implementation tuning enable the eight AMD Radeon cores to reduce power 20% from Kaveri

    Double digit increases in performance and battery life

    NEW PERFORMANCE MOBILE APU CARRIZOISSCC 2015 DISCLOSURES

    A 28NM X86 APU OPTIMIZED FOR POWER AND AREA EFFICIENCY SESSION 4.8*

    *A 28nm x86 APU Optimized for Power and Area Efficiency , presented by Kathryn Wilcox. Session 4.8, Solid-State Circuits Conference Digest of Technical Papers (ISSCC). 2015 ISSCC Conference, February, 2015.

  • 14 | CARRIZO | ISSCC 2015 |

    ENDNOTES

    1 Koomey, Jonathan G., Stephen Berard, Marla Sanchez, and Henry Wong. 2011. "Implications of Historical Trends in The Electrical Efficiency of Computing." IEEE Annals of the History of Computing. vol. 33, no. 3. July-September. pp. 46-54. [http://doi.ieeecomputersociety.org/10.1109/MAHC.2010.28]

    2 Typical-use Energy Efficiency as defined by taking the ratio of compute capability as measured by common performance measures such as SpecIntRate, PassMark and PCMark, divided by typical energy use as defined by ETEC (Typical Energy Consumption for notebook computers) as specified in Energy Star Program Requirements Rev 6.0 10/2013

  • 15 | CARRIZO | ISSCC 2015 |

    ATTRIBUTIONS

    DISCLAIMERThe information contained herein is for informational purposes only, and is subject to change without notice. While every precaution has been taken in the preparation of this document, it may contain technical inaccuracies, omissions and typographical errors, and AMD is under no obligation to update or otherwise correct this information. Advanced Micro Devices, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this document, and assumes no liability of any kind, including the implied warranties of noninfringement, merchantability or fitness for particular purposes, with respect to the operation or use of AMD hardware, software or otherproducts described herein. No license, including implied or arising by estoppel, to any intellectual property rights is granted by this document. Terms and limitations applicable to the purchase or use of AMDs products are as set forth in a signed agreement between the parties or in AMD's Standard Terms and Conditions of Sale.

    AMD, the AMD Arrow logo, Radeon and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. DirectX is a registered trademark of Microsoft Corporation in the U.S. and other jurisdictions.