implementation of inter and intra vehicular …

Web Site: www.ijettcs.org Email: [email protected], [email protected] Volume 1, Issue 3, September – October 2012 ISSN 2278-6856

Volume 1, Issue 3, September – October 2012 10

Abstract: A Design approach for vehicle Black Box system using FPGA Based CAN Controller. It is proposed that the system will consists of monitor as CAN Controller. Which on activation test its run application after authentication it will form packets of emergency data depending upon spontaneous situation & risk; Packets which are generated through CAN Controller namely flows in all network buses which are connected to CAN master and Slaves. As on the same time packets are store into the memory which is present in FPGA as a Black Box for vehicle. Stored data we can retrieve for analysis to see accident cause or any emergency situation occurs. Analog to digital conversion is required for digital data in along with controller for Black Box. Fully hardware is responsible for sensed data in to memory part of Black Box and VHDL language is used for coding Keywords: CONTROL AREA network, ADC-Analog to digital convertor, FPGA- Field programmable gate array.

1. INTRODUCTION A new technology tell for future to do fully automated system may call as good driving experience with driver comforts and safety. But it is also look after for economical standard in today’s world. As expectation from vehicular manufacture, researchers led to design easily interlinking with ECU part now are very common. ECU part required the communication media with intelligent system may known as controller mostly the controller having its internal bus mechanism that will help to communicate with each other. Here CAN act as Controller which having one master and we can design system up to 16 salves which are connected to its master with link called as bus. CAN is used for controlling between controller and device. The CAN is a serial communication protocol which efficiently supports the control of mechatronic nodes in distributed automotive applications. CAN bus has Single master / multiple slaves (maximum 16) configuration with self synchronized low cost silicon single wire implementation with around 20 k bits/ s data transfer rate. Master task is allowed to transmit the message header and slave task responds to the header. Because there is no arbitration, to

avoid error multiple slave reception, the slave is specified with application. The master checks the Consistency of message and can change message schedule. To reduce the power consumption of the system, a CAN node may be sent to sleep node which has no internal activity & passive bus driver A new methodology is now demanded more where vehicle communicate with the world, devices with them this will create more opportunity to develop advanced communication devices which are isn’t smart to tell its status and its internal working pro forma at same time of activation or in the middle of journey. A smart vehicle is always look after on its all devices which is sensed every some time instances decided by the programmer.

1.1 Control Area Network

The Controller Area Network (CAN)[1] is a serial communications protocol which efficiently supports distributed real time control with a very high level of security. Its domain of application ranges from high speed networks to low cost multiplex wiring. In automotive electronics, engine control units, sensors are connected using CAN with bit rate up to 1M bit/s. At the same time it is cost effective to build into vehicle body electronics, e.g. lamp clusters electric windows etc. to replace the wiring harness required. The intention of this specification is to achieve compatibility between any two CAN implementations. Compatibility however has different aspects regarding e.g. electrical features and the interpretation of data to be transferred. Nowadays, there are FPGA-based integrated solutions where programmable logic is included in addition to general purpose processors, allowing dedicated hardware to be synthesized according to the application needs. Besides re-configurability features, low turnaround time of rapid prototyping using FPGA devices is an attractive alternative of system validation, especially when fast time-to-market is required. Equally important, FPGA technology is being largely used in final products when total demand is restricted to few units because of the high cost associated to ASIC fabrication Not only HDL

IMPLEMENTATION OF INTER AND INTRA VEHICULAR COMMUNICATION SYSTEM

D.Sridhar1, N.Mallika2 and Chirivella Anjaneyulu3

1JNTU KAKINADA, SRI VASAVI INSTITUTE OF ENGINEERING AND TECHNOLOGY, Nandamuru, Krishna (d.t), A.P, INDIA

2Graduate Engineer Trainee*(TC&TS), Chennai, INDIA

3Building Management Systems, Electronics Engineer (Research & Development)

Johnson Controls, Low Voltage Systems, Under Agency DAWAER ALSHARQ, WADIMARAMER GROUP


Volume 1, Issue 3, September – October 2012 Page 111

developers but also the IP industry as a whole are aware of all those benefits. Standard CAN Frame

Figure 1 Standard CAN Frame

The meaning of the bit fields of Figure 1 are: SOF–The single dominant start of frame (sof) bit marks the start of a message, and is used to synchronize the nodes on a bus after being idle. Identifier-the standard can 11-bit identifier establishes the priority of the message. The lower the binary value, the higher its priority. Rtr–the single remote transmission request (rtr) bit is dominant when information is required from another node. all nodes receive the request, but the identifier determines the specified node. The responding data is also received by all nodes and used by any node interested. in this way, all data being used in a system is uniform. IDE–a dominant single identifier extension (ide) bit means that a standard can identifier with no extension is being transmitted. R0–reserved bit (for possible use by future standard amendment). DLC–the 4-bit data length code (dlc) contains the number of bytes of data being transmitted. Data up to 64 bits of application data may be transmitted. CRC–the 16-bit (15 bits plus delimiter) cyclic redundancy check (crc) contains the checksum (number of bits transmitted) of the preceding application data for error detection. ACK–every node receiving an accurate message overwrites this recessive bit in the original message with a dominate bit, indicating an error-free message has been sent. Should a receiving node detect an error and leave this bit recessive, it discards the message and the sending node repeats the message after re arbitration. in this way, each node acknowledges (ack) the integrity of its data. ack is 2 bits, one is the acknowledgment bit and the second is a delimiter. EOF–this end-of-frame (eof), 7-bit field marks the end of a can frame (message) and disables bit-stuffing, indicating a stuffing error when dominant. When 5 bits of the same logic level occur in succession during normal operation, a bit of the opposite logic level is stuffed into the data. IFS–this 7-bit inter frame space (ifs) contains the time required by the controller to move a correctly received frame to its proper position in a message buffer area. 2. THE CAN STANDARD CAN is an International Standardization Organization (ISO) defined serial communications bus originally

developed for the automotive industry to replace the complex wiring harness with a two-wire bus. The specification calls for high immunity to electrical interference and the ability to self-diagnose and repair data errors. These features have led to CAN’s popularity in a variety of industries including building automation, medical, and manufacturing .The CAN communications protocol, ISO-11898: 2003, describes how information is passed between devices on a network and conforms to the Open Systems Interconnection (OSI) model that is defined in terms of layers. Actual communication between devices connected by the physical medium is defined by the physical layer of the model. The ISO 11898 architecture defines the lowest two layers of the seven layer OSI/ISO model as the data-link layer and physical layer in Fig. 2.

Figure 2 the Layered ISO 11898 Standard Architecture

2.1 The CAN Bus

The data link and physical signaling layers of Figure 2, which are normally transparent to a system operator, are included in any controller that implements the CAN protocol, such as TI's TMS320LF28123.3-V DSP with integrated CAN[4] controller. Connection to the physical medium is then implemented through a line transceiver such as TI's SN65HVD230 3.3-V CAN transceiver to form a system node as shown in Figure 3.

Figure 3 Details of a CAN Bus

Signaling is differential which is where CAN derives its robust noise immunity and fault tolerance. Balanced differential signaling reduces noise coupling and allows



for high signaling rates over twisted-pair cable. Balanced means that the current flowing in each signal line is equal but opposite in direction, resulting in a field-canceling affect that is a key to low noise emissions. The use of balanced differential receivers and twisted-pair cabling enhance the common-mode rejection and high noise immunity of a CAN bus. Automotive black box will be installed in vehicle and will be used to store the data supplied by CAN [2] host downloaded on FPGA. The data thus stored in Black box can be retrieved and can be used for simulating any external or internal emergency situation which has lead to cause of accident. In the implementation Authors have assumed the simulated emergency situation with the help 3.BLOCKDIAGRAM

Figure 4 Block diagram of design Methodologyof

Analogue to Digital Converter. The design methodology is shown in Fig.ure 4. The digital signal thus derived from output of ADC is given as input to CAN host FPGA which holds Data frame and directs it to Black box. The black box will store the frame and will make available as and when required. The 8-bit input from the analog to digital converter is used to form the complete data frame by the CAN Host which will be transmitted to the black box[3]. All the fields of the data frame will be decided according to the input from the analog to digital converter. As the input to the CAN-Host is digital data of 8-bit, it can range from 00000000 to 11111111 in binary digital logic where 0 represents a ground voltage and 1 represents a +Vcc (Typically 5 volts).The operation of system is as shown in the flow chart of Figure 4. Thus after reading these 8 bits first task is to decide the dependency of all the fields of the data frame on the combination of these data bits. The data frame that is to be transmitted by the CAN-Host will consist of the following fields: Identifier field, control field, data field and CRC field. Obviously all of these fields will vary according to the system. The emergency situation in Vehicle i.e. output of sensor element from the Engine of a car can be simulated using ADC converter in which the Analog input is varied by potentiometer or the same can be simulated

by operating DIP switches on XILINX FPGA Board. Then according to the input from the sensor the output of the ADC is needed to be interpreted or calibrated. This digital signal is given as input to CAN host FPGA which is employed to operate specific application in the vehicle. The instantaneous CAN Frame of that particular application is hold of and is stored in memory of intelligent vehicle black box. The Figure.5. Shows how the system is generally works and what external parts it interacts with. AUTOMATIVE BLACK BOX procedure goes throw two steps. The first one is before the accident occurrence and the second one after the accident occurs. The most important assumption on the second step is that all the data stored in the microcontroller are transferred successfully to the terminal which in this case a PC The second step is the process where the data will. 3.1 System Design

Figure5 System Design

Be transferred into the PC [5]. This will require the data to be stored in a file. The file will be converted to decimal numbers. After the file is ready and contains the appropriate format, the simulation software will generate a simulation for the accident based on the data provided. And the operational flow chart showed in the Figure 6. 3.2 Hardware Components

Microcontroller: The microcontroller that was used in this is Motorola Handy Boards HC11. Each car will have this Handy Board inserted somewhere safe in the car to ensure that it will not be affected or crashed if a collision happens .The HC11 will have 32 Kbytes of External RAM that will allow the team to store up to 30 seconds or even memory. The handy board is able to read from eight analog inputs and eight digital sensors. Sensors: Different types of sensors where used to measure distance, speed and rotation. The sensors vary from analog sensors to digital ones. The total number of sensors used in the project is ten sensors (8 sonar’s, 1 gyro and 1 acidometer).The data of these sensors will be save din the microcontroller. Operational Flow Chart: how data bits can be combined showed in the Figure 6. Data sending and receiving in a vehicle: Every module (node) that is attached to the data bus network is capable



of sending and receiving signals. Each module (node) has its own unique address on the network. This allows the module to receive the inputs and data it needs to function, while ignoring information intended further modules that share the network. Shown in the Figure 7 when a module transmits information over the network, the information is coded so that all the other modules recognize from where it came. Data is sent as a series of digital bits consisting of "0's" and "1's" end a square wave pattern that changes between a high and Low received by a module on the network, there is a beginning bit (called the "start of frame" or "start of message" bit), followed by an "identifier" code (an 11 bit code that tells what kind of data the message contains), followed by a priority code ("remote transmission request") that says how important the

Figure 6 Operational Flow Chart

Figure 7 Modules Arrangement

Data is, followed by 0 to 8 bytes (one byte equals 8 bits) of actual data, followed by some more bits that verify the information (cyclic redundancy checks), followed by some end of message bits and an "end-of-frame" bit. Usually the body control module or instrument cluster module is assigned the task of managing the network traffic. When it sees a message coming over the bus, it looks at the first bit in the data stream. If the bit is a "0", the message is given priority over the others. This is called a "dominant"

message. If the first bit is a "1" it is given a lower priority (a "recessive" message). Thus, the highest priority messages always get through to their intended destinations but the lowest of priority messages might not be. In this technique user can take the ADC information according to this information sends to the black box then Black box simulates the given information and it generates necessary control signals and transfer to

Figure 8 Message Transmission in vehicle

The gyrators. According to the back box and gyrators control signals wheel moment of vehicle can be controlled in this way user can eliminate the accidents Fig .9. Explanation of CAN Frame simulation

Figure 9 Operation of Automated Vehicular system

This CAN frame simulation can be explained in Figure 9. shown above when two vehicles are installed with inter communication systems when the vehicle exceeds the limited range The sensor senses the information passed to the black and the box black box generates the control signals then the vehicle will move to another direction. In this way detection and elimination of accidents could be done.

Figure 10 Automated Vehicular System

4. SIMULATION & SYNTHESIS RESULTS

4.1.1 Incan Block The simulation [6] results of Incan block is shown in Figure 11.. It takes adc of 8bits and tx_cn of 1bit provides

8 Sonar’s surrounded the car



id_cntrl,dlc_cntranddata_cntrlOutputs.

Figure 11 Simulation results of Incan block.

Inference When tx_cn=1 and adc Input is (38) h then respective out puts of id_cntrl,dlc_cntrl,data_cntrl When tx_cn=0 all outputs are undefined 4.1.2 Identifier block The simulation results of identifier block are shown Figure 12. It takes iden_cntrl of 5-bits and reset as inputs to generate 11 bit identifier and state outputs.

Figure 12 Simulation results of identifier block

Inference When rst=0, iden_cntrl=(04)h are input then respective out puts are identifier=(07f)h, state=(f)h when rst=1all outputs are identifier =zero, state = zero. 4.1.3 Data block The simulation results of data block are shown Figure13. It takes data_cntrl, dlc_cntrl, state and rst as the inputs and a 64 –bit data frame is generated as output.

Figure13 Simulation results of data block

Inference When rst=0, dlc_cntrl= (05) h are input then respective out puts are data_cntrl= (7) h, data and a64–bit data frame is generated as output= (000000E5FC) h AND When rst=1all outputs are data_cntrl, data =zero 4.1.4 DLC block The simulation results of dlc block are shown Figure14. Inference Dlc block act as a buffer unit whatever input at transmitter can be received at receiver

Figure 14 Simulation results of dlc block

4.1.5 Final Block The simulation results of final block are shown Figure15. It takes dlc, identifier, and data to produce a 114-bit transmission frame (frame_tx).

Figure 15 Simulation results of final block Inference When dlc= (5)h , data=(000000DD29)he5fc22h , identifier=(07F)h input s then respective Out puts is 114-bit tx frame (frame_tx). frame_tx= (0FC280000072FE) h. 4.1.6 CAN Frame The simulation results of a CAN data frame are shown Figure 16. The 114 bits data frame is generated by taking adc_in, rst, tx_cn as inputs.

Figure 16 Simulation results of Can frame

Inference When dlc=(5)h , data=(000000DD29)he5fc22h , identifier=(07F)h input s then respective Out puts is 114-bit transmission frame (frame_tx). frame_tx=(0FC280000072FE)h

4.2 SYNTHESIS RESULTS

4.2.1 Entity and RTL diagram of CAN frame:

Figure 17 Entity diagram of CAN frame

Figure18 RTL schematic of CAN frame

4.2.2 Entity and Rtl diagram of in can block:



Figure19 Entity diagram of Incan block

Figure 20 RTL schematic of Incan block

4.2.3 Entity and RTL schematic of identifier block:

Figure 21 Entity of Identifier block

4.2.4 Entity and RTL schematic of data block:

Figure 22 Entity of data block

Figure23 Gate level schematic of data block

4.2.5 Entity and RTL schematic of final block:

Figure 24 Entity diagram of final block

Figure 25 Gate level schematic of final block

4.3 Technology schematic of Can Frame:

Figure 26 Technology schematic of Can Frame

SLACK OF CAN FRAME : 0.23 4.4.Floor Planning Diagram of Can Frame:

Figure 27 Floor Planning Diagram of Can Frame

4.5 Summary of CAN Frame

Technology Used

0.18um CMOS

Power supply 0.9v No. of routing

layers 6



Avg. power dissipation

0.29mw

Clock frequency

15.1 MHz

No. of pad components

133

Total Area of chip

3485325.984 um^2

Table 1. Summary of CAN frame 5. CONCLUSION & FUTURE SCOPE

We have presented design approach for automotive black box using CAN protocol. The design is implemented in VHDL. VHDL code is simulated and synthesized. The signal from sensors of automotive is simulated using A/D converter to implement CAN data frame. As the analog signal form ADC deviates from threshold boundaries the CAN host responsible for that automotive application is supplying the data, which can be stored in black box. The design can be extended for more signals of automotive accounting under Controller Area Network. The multiplexer is used to route one signal at a time to CAN host. With this data related with all the applications under CAN umbrella can be stored in an automotive black box. As ECU part is much more flexible and available in bulk; that support the future aspect which required intelligence from the automobile part and stored data is retrieved easily for to know cause of error and risk at emergency condition that make future more safe.

FUTURE SCOPE

Measure car rotation around z-axis to account for car turning over

Include more sensors for better accuracy Approach virtual reality using a 3-D simulation engine. Add GPRS and GPS modems to locate the exact

location of the accident and transmit the data, time-stamped, to the police station and insurance servers

6. REFERENCES [1] CAN Specification, BOSCHGmbE 1991 [2] Bloomer Douches, Marin Hristov, Implementation of

CAN Controller with FPGA Structures. CADSM’2003, February 18-22, 2003, Lviv-Slasko, Ukraine

[3] Yousef Al-Ali, Ghaleb Al-Habian, Sadiq Saifi, “Automobile Black Box for Accident Simulation”, published in CSIDC 2005, American university of Sharjah

[4] Milind Khanapurkar, Dr. Preeti Bajaj, Dakshata Gharode, “A Design Approach for Intelligent Vehicle Black Box System withIntra-vehicular communication using LIN/Flex-ray Protocols”IEEE-ICIT, April- 2008

[5] Fabiano C. Carvalho, Ingrid Jansch-Porto and Edison P. Freitas, Carlos E. Pereira .The Tiny CAN: An Optimized CAN Controller IP for FPGA-Based Platforms, 2005

IEEE

[6] Reference websites www.xilinx.xom, www.opencore.org, www.digitalcoredesign.org

ABOUT THE AUTHORS

D.Sridhar Received the M.Tech degree in VLSI SYSTEM DESIGN from Avanthi Institute of Engineering and Technology, Narsipatnam, B.Tech degree in Electronics and communication Engineering at Gudlavalleru Engineering College. He has total Teaching Experience (UG and PG) of 6 years. He has guided and co-

guided 4 P.G and U.G students .His research areas included VLSI SYSTEM DESIGN, Digital signal processing.

N.Mallika is born in Guntur. She Received the B.Tech degree in Electronics and Communication Engineering at Avanthi Institute of Engineering and Technology, Tagarapuvalasa. She is working as Graduate Engineer Trainee in Tata

Communicationand Transformation Services. Her research areas included Embedded systems, Digital signal processing,

Chirivella Anjaneyulu received the B.Tech degree from SVH college of Engineering in Electronics and communication Engineering in year 2005 and M.Tech VLSI systems Design degree from AIET in year 2011 under gate rank. He stayed Assistant professor in Electronics and communications

Department. He now with part of Johnson controls, Building Management Systems (BMS),as Electronics engineer (Research and Development) for Low Voltage systems. Research work is on Energy efficiency, Energy saving by reducing power consumption of low voltage systems with different optimize Techniques for HVAC, lightning for Buildings and vehicular systems. He has overall 12 years of teaching and Industrial experience.

implementation of inter and intra vehicular …

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