Hsiu-Yu Lai

Ting-Chi Wang

A TPL-Friendly Legalizer for Standard Cell Based Design

SASIMI ‘15

Outline

Introduction Problem Formulation The Legalizer Experimental Results Conclusion

Introduction

As the shrinking of the feature size patterning lithography (DPL) is no longer enough for 14/10nm technology node

Triple patterning lithography (TPL) is a nature extension from DPL

The TPL decomposition problem in two types of standard cell based design pre-colored design

Foundries

un-colored design Design houses

Most of the related work focus on minimal conflicts and stitches for TPL layout decomposition during or after the routing stage

TPL-friendly standard cell legalization problem in order to move the TPL layout decomposition issue to an earlier design stage

Problem Formulation

No prior work on standard cell legalization considers the possibility of reordering cells and inserting white space to help resolve TPL conflicts

Given Global placement of standard cells

Do Produce a legal placement

Objective Primary objective is to minimize the total number

of TPL coloring conflicts Secondary objective is to minimize the total

amount of cell displacement

The Legalizer

Cell Reordering

Since each standard cell from the cell library has a fixed layout

Pre-construct a table to store the minimum number of sites that has to keep between any two cells such that no pair of polygons cells has a TPL coloring violation

Cell Reordering by Grouping

Divide a row of cells into small groups and consider all cell permutations in each group

For each cell permutation, a cost measuring the difference between the permutation and the original cell order is calculated

The total amount of white space it needs to reserve between each pair of adjacent cells in the permutation is also calculated

To consider cell displacement The amount of position change from the original

order as the cost

EX:

Original : ABCDE

A permutation : BADCE

To consider the amount of white space that needs to be reserved for a permutation

A reordering graph

Amplify the amount of white space on each node or edge in the graph

Multiplying it by a constant to minimize the number of sites reserved for avoiding any TPL spacing violation

Find a shortest path from a node in the first group to a node in the last group

Refinement

After reordering cells in a row, there may still leave room for further reducing required white space by swapping cells

Swapping a cell that has white space reserved to its left or right with another cell

White Space Insertion

If a row has enough space for all of white spaces we reserve, we will insert all of them in the row

Dynamic programming based linear placement algorithm to place the cells and blank cells

Try to further minimize the total displacement

When a row is not wide enough, we need to choose which white space should we insert

In order to reduce TPL conflicts as many as possible

First sort the set of white spaces reserved in adjacent cells in a non-decrease order of their amounts

Experimental Results

Implemented in C++ Linux workstation with an Intel Xeon 2.4

GHz and 12G memory

Comparisons of Algorithm

Comparisons of Group Size

Conclusion

Presented a TPL-friendly legalizer that adopts cell reordering and white space insertion

A possible future work is to combine our legalizer and a TPL-aware detailed placer, to achieve a TPL conflict-free placement