hpi presentacion_2

8/12/2019 HPI Presentacion_2

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Host Port Interface (HPI)

Martínez Robles Marco Antonio

Macedo Santiago Luis Alberto



HPI

Is a parallel port through which ahost processor can directly accessthe CPU memory space.

Connectivity to the CPU memoryspace is provided through thedirect memory access (DMA) orenhanced DMA (EDMA) controller.



Both the host and theCPU can access theHPI control register(HPIC). The host can

access the HPI addressregister (HPIA), the HPIdata register (HPID),and the HPIC by using

the external data andinterface controlsignals.

HPI

HPIC

HPIA

HPID



Through the HPI, an external host is

capable of accessing the entire DSPmemory map except the following:

L2 control registers (C6x1x DSP only)

Interrupt selector registers

Emulation logic



C ‘C6x

Ser. Port

32

|| Bus

Ded. Bus

Dedicated to memory access

Dedicated to Codecs and A/D’s



Data Bus: HD[15:0] or HD[31:0]HD[15:0] or HD[31:0] is aparallel, bidirectional, 3-state data bus. HD is placed

in the high-impedance state when it is not responding to anHPI read access.

Pins HD[31:16] apply to the C64x HPI32 only.

Access Control Select: HCNTL[1:0]HCNTL[1:0] indicatewhich internal HPI register is being accessed. The states

of these two pins select access to the HPI address (HPIA),HPI data (HPID), or

HPI control (HPIC) registers. Additionally, the HPID registercan be accessed

with an optional automatic address increment



Halfword Identification Select: HHWIL

HHWIL identifies the first or second halfword of a transfer, but

not the most significant or least significant halfword. Thestatus of the HWOB bit of the HPIC register, described later inthis chapter, determines which halfword is least significant ormost significant. HHWIL is low for the first halfword and highfor the second halfword.

Since byte enable pins HBE[1:0] are removed from the

C621x/C671x and C64x HPI, HHWIL in combination withHWOB specify the half-word position in the data register,HPID

Address Strobe Input: HAS

HAS allows HCNTL[1:0], HR/W, and HHWIL to be removedearlier in an access cycle, which allows more time to switch

bus states from address to data information. This feature facilitates interface to multiplexed address and

data buses. In this type of system, an address latch enable(ALE) signal is often provided and is normally the signalconnected to HAS.



Interrupt to Host: HINT

HINT is the host interrupt output that is controlled by the HINT

bit in the HPIC. This The HINT bit is set to 0 when

the chip is being reset. Thus, the HINT pin is high at reset.



Read/Write Select: HR/W

HR/W is the host read/write select input. The host must drive

HR/W high to read and low to write HPI. A host without eithera read/write select output or a read or write strobe can use anaddress line for this function.

Ready: HRDY

When active (low), HRDY indicates that the HPI is ready for atransfer to be performed. When inactive, HRDY indicates that

the HPI is busy completing the internal portion of a currentread access or a previous HPID read prefetch or write access.HCS enables HRDY; HRDY is always low when HCS is high.

Strobes: HCS, HDS1, HDS2

HCS, HDS1, and HDS2 allow connection to a host that haseither:

A single strobe output with read/write select (HR/W)

Separate read and write strobe outputs. In this case, read orwrite select

can be done by using different addresses.



HPI data register (HPID)

HPI Address Register (HPIA)

HPI Control Register (HPIC)



C HPI Bus

Since the HPI bus (HD) is only 16 bits wide, eachread/write requires two operations.

‘C6x

HPIHPIC

HPIA

HPID

DMA

Aux. Ch.Addr.

Data

Memory

..

.

16

Setup HPIC

S t HPIC



Setup HPIC

1. Use HCNTL[1:0] = 00b to enable access to HPIC

C ‘C6x HPI

DMA

Aux. Ch.Addr.

Data

2HCNTL

HPID

HPIA

Memory

.

..

HD

16

HPIC

HCNTL Values

HCNTL1 HCNTL0 Description

0 0 HPIC

0 1 HPIA

1 0 HPID (HPIA++)

1 1 HPID

T TOTechnical Training

Organization

S t HPIC



Setup HPIC

C ‘C6x HPI

DMA

Aux. Ch.Addr.

Data

2 HCNTL

HPID

HPIA

Memory

.

..

HD

16

HPIC

HR/W


HR/W to write (0). HD = ctrl bits (HWOB= xxx1)


Organization

S t HPIC 1



Setup HPIC - 1

C ‘C6x HPI

DMA Aux. Ch.

Addr.

DataHPID

HPIA

Memory

.

..

HD

16

HPIC

HR/W

HHWIL

1. Use HCNTL[1:0] = 00b to enable access to HPIC HR/W to write (0), HD = ctrl bits (HWOB = xxx1)

HHWIL = 0 indicates first halfword transfer

2 HCNTL


Organization

HSTRB 2



HSTRB - 2

C ‘C6x HPI

DMA Aux. Ch.

Addr.

DataHPID

HPIA

Memory

.

..

HPIC

HSTRB


HR/W to write (0). HD = ctrl bits (HWOB = xxx1)


2. HSTRB to indicate active

HD

16

HR/W

HHWIL

2 HCNTL

xxx1


Organization

Set p HPIC 3



Setup HPIC - 3

C ‘C6x HPI

DMA Aux. Ch.

Addr.

Data

HPID

HPIA

Memory

.

..

HPIC



HHWIL = 1 indicates second halfword transfer

HD

16

HR/W

HHWIL

2 HCNTL

xxx1

T TOTechnical TrainingOrganization

Setup HPIC 4



Setup HPIC - 4

C ‘C6x HPI

DMA Aux. Ch.

Addr.

Data

HPID

HPIA

Memory

.

..

HPIC

HSTRB





HD

16

HR/W

HHWIL

2 HCNTL

xxx1xxx1


Setup HPIA 1



Setup HPIA - 1

C

Write

8000_0000

to

HPIA

‘C6x HPI

DMA Aux. Ch.

Addr.

Data

HPID

HPIA

Memory

.

..

HPIC

1. Use HCNTL[1:0] = 01b to enable access to HPIA HR/W to write (0), HD = 0000


HR/W

HHWIL

HD

16

2HCNTL

xxx1xxx1


Setup HPIA 2



Setup HPIA - 2

C

Write

8000_0000

to

HPIA

‘C6x HPI

DMA Aux. Ch.

Addr.

Data

HPID

HPIA

Memory

.

..

HPIC

HSTRB

1. Use HCNTL[1:0] = 01b to enable access to HPIA

HR/W to write (0). HD = 0000



HD

16

HR/W

HHWIL

2 HCNTL

xxx1xxx1

0000


Setup HPIA 3



Setup HPIA - 3

C

Write

8000_0000

to

HPIA

‘C6x HPI

DMA Aux. Ch.

Addr.

Data

HPID

HPIA

Memory

.

..

HPIC




HD

16

HR/W

HHWIL

2 HCNTL

xxx1xxx1

0000


Setup HPIA 4



Setup HPIA - 4

C

Write

8000_0000

to

HPIA

‘C6x HPI

DMA Aux. Ch.

Addr.

Data

HPID

HPIA

Memory

.

..

HPIC

HSTRB





HD

16

HR/W

HHWIL

2 HCNTL

xxx1xxx1

00008000




Writing Example

Example 1: Writing a 32 bit Value 1



Example 1: Writing a 32-bit Value - 1

1. HCNTL[1:0] = 11b (HPID)

HR/W = 0 , HD = 5678

HHWIL = 0

C

Write

1234_5678

to

8000_0000

‘C6x HPI

HPID

DMA Aux. Ch.

Addr.

Data

HHWIL

2HCNTL

HPIA

8000 0000

Memory

.

..

HD

16

HR/W

HPIC

xxx1xxx1





3. HCNTL[1:0] = 11b (HPID)

HR/W = 0

Write value: HHWIL = 1, HD = 1234

C

Write

1234_5678

to

8000_0000

‘C6x HPI

HPID

5678

DMA Aux. Ch.

Addr.

Data

HHWIL

2HCNTL

HPIA

8000 0000

Memory

.

..

HD

16

HR/W

HPIC

xxx1xxx1






3. HCNTL[1:0] = 11b (HPID)

HR/W = 0


4. HSTRB

C

Write

1234_5678

to

8000_0000

‘C6x HPI

HPID

1234 5678

DMA Aux. Ch.

Addr.

Data

HHWIL

2HCNTL

HPIA

8000 0000

Memory

.

..

HD

16

HR/W

HPIC

xxx1xxx1

HSTRB






3. HCNTL[1:0] = 11b (HPID)

HR/W = 0


4. HSTRB

5. HRDY high (not-ready) until DMA is finished

C

Write

1234_5678

to

8000_0000

‘C6x HPI

HPID

1234 5678

DMA Aux. Ch.

Addr.

Data

HHWIL

2HCNTL

HPIA

8000 0000

Memory

.

..

HD

16

HSTRB

HRDY

HPIC

8000 0000

1234 5678

1234 5678

xxx1xxx1HR/W






3. HCNTL[1:0] = 11b (HPID)

HR/W = 0


4. HSTRB

5. HRDY high (not-ready) until DMA is finished

C

Write

1234_5678

to

8000_0000

‘C6x HPI

HPID

1234 5678

DMA Aux. Ch.

Addr.

Data

HHWIL

2HCNTL

HPIA

8000 0000

Memory

.

..

HD

16

HSTRB

HPIC

8000 0000

1234 5678

1234 5678

xxx1xxx1HR/W




Reading Example

Example 2: Reading a 32-bit Value - 1




1. HCNTL[1:0] = 11b (HPID)

HR/W = 1

Read value: HHWIL = 0

C

Read

8000_0000

‘C6x HPI

HPID

DMA Aux. Ch.

Addr.

Data

HHWIL

2HCNTL

HPIA

8000 0000

Memory

.

..

HR/W

HPIC

1234 5678

xxx1xxx1






1. HCNTL[1:0] = 11b (HPID)

HR/W = 1


2. HSTRB, HPIA is copied to DMA address

C

Read

8000_0000

‘C6x HPI

HPID

DMA Aux. Ch.

Addr.

Data

HHWIL

2HCNTL

HPIA

8000 0000

Memory

.

..HSTRB

HPIC

1234 5678

xxx1xxx1HR/W






1. HCNTL[1:0] = 11b (HPID)

HR/W = 1



3. HRDY is asserted until HD = 5678

C

Read

8000_0000

‘C6x HPI

HPID

DMA Aux. Ch.

Addr.

Data

HHWIL

2HCNTL

HPIA

8000 0000

Memory

.

..

HPIC

1234 5678

xxx1xxx1

HD

16

1234 5678

HR/W

HSTRB

HRDY

1234 56785678

Host Data

8000 0000






1. HCNTL[1:0] = 11b (HPID)

HR/W = 1



3. HRDY is asserted until HD = 5678

C

Read

8000_0000

‘C6x HPI

HPID

DMA Aux. Ch.

Addr.

Data

HHWIL

2HCNTL

HPIA

8000 0000

Memory

.

..

HPIC

1234 5678

xxx1xxx1

HD

16

1234 5678

HR/W

HSTRB 1234 56785678

Host Data

8000 0000





Example 2: Reading a 32 bit Value 4

4. HCNTL[1:0] = 11b (HPID)

HR/W = 1


C

Read

8000_0000

‘C6x HPI

HPID

DMA Aux. Ch.

Addr.

Data

HHWIL

2HCNTL

HPIA

8000 0000

Memory

.

..

HPIC

8000 0000 1234 5678

xxx1xxx1

HD

16

1234 5678

1234 5678

HR/W

5678

Host Data






4. HCNTL[1:0] = 11b (HPID)

HR/W = 1


5. HSTRB

C

Read

8000_0000

‘C6x HPI

HPID

DMA Aux. Ch.

Addr.

Data

HHWIL

2HCNTL

HPIA

8000 0000

Memory

.

..

HPIC

1234 5678

xxx1xxx1

1234 5678

1234 5678

8000 0000

HD

16

HR/W

HSTRB5678

Host Data






4. HCNTL[1:0] = 11b (HPID)

HR/W = 1


5. HSTRB

6. HD = 1234

C

Read

8000_0000

‘C6x HPI

HPID

DMA Aux. Ch.

Addr.

Data

HHWIL

2HCNTL

HPIA

8000 0000

Memory

.

..

HPIC

8000 0000 1234 5678

xxx1xxx1

HD

16

1234 5678

1234 5678

HR/W

HSTRB1234_5678

Host Data




Referencia:

Manual del Codec CompouserVersion 3.1

hpi presentacion_2

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