hcs12 a tod converters
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A/D and D/A Converters
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Registers for the HC12 A/D Converter
ATDCTL2 ADPU AFFC ASWAI ETRIGLE ETRIGP ETRIGE ASCIE ASCIF
ATDCTL3 0 S8C S4C S2C S1C FIFO FRZ1 FRZ0
ATDCTL4 SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
ATDCTL5 DJM DSGN SCAN MULT CD CC CB CA
ATDSTAT0 SCF 0 ETORF FIFOR CC3 CC2 CC1 CC0
ATDSTAT1 0 0 0 0 0 0 0 SC
Minimum bit fields to consider when configuring the A/D
ADPU = 1 (Power up A/D)ASCIE = 0 (A/D Sequence Complete Interrupt Disabled)ASCIE = 1 (A/D Sequence Complete Interrupt Enabled)ASCIF = 1 (A/D Sequence Complete Interrupt Pending)ASCIF = 0 (A/D Sequence Complete Interrupt Not Pending)
S8C..S1C Conversion Sequence Length Coding -- See Table 3-3 on page 19 ofS12ATD10B16CV2.pdf for details
SRES8 = 1 (8 bit A/D Resolution) SRES8 = 0 (10 bit A/D Resolution)PRS4..PRS0 ATD Clock Prescaler (this value must create a clock between 500 KHz and 2
MHz using the formula ATDclock = (busclock) / (PRS + 1) * 0.5
DJM = 1 (Left justified result) DJM = 0 (Right justified result)DSGN = 1 (Signed A/D result) DSGN = 0 (Unsigned A/D result)SCAN = 1 (Continuous conversion) SCAN = 0 (Single conversion)MULT = 1 (Sample across multiple channels) MULT = 1 (Sample across single channel)CD..CA Analog Input Channel Select Coding -- See Table 3-9 on page 25 of
S12ATD10B16CV2.pdf for details
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Status Registers
SCF = ASCIFFIFOR indicates that the data has been over-written before the appropriate CCFx bit has been cleared.
This is useful to know if you are working with the most recent data.CC3..CC0 These bits are used to indicate where the current conversion will be stored. For example, itCC3..CC0 = 0x2 then the conversion that is executing will be stored in result register 2.
SC is a special status bit that can be written to allow the user to check the status of special conversionsas listed below instead of the normal conversion sequence.
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HCS12 D/A Converter
The DAC is a 8-bit, 1-channel digital to analog converter module.
The HCS912E128 has 2 of DAC modules.
The DAC includes these features:
8 bit Resolution.
1 output independent monotonic channel.
D/A Block Diagram
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HCS12 DAC Registers
DACC0 DACE DACTE 0 0 DJM DSGNDACWAI DACOE
DACD(left justified)
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
DACD(right justified)
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Minimum bit fields to consider when configuring the A/D
DACE = 1 (D/A is enabled) DACE = 0 (D/A is disabled)
DJM = 1 (D/A data is right justified) DJM = 1 (D/A data is left justified)DSGN = 1 (D/A data is signed) DSGN = 0 (D/A data is unsigned)DACOE = 1 (D/A output is enabled) DACOE = 1 (D/A output is enabled)
Since the D/A is only 8 bit we can use either data register without any data manipulationunlike on the A/D with 10 bit operation. But, you need to be sure that you are using thecorrect address for the data register that corresponds to either right or left justification.
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D/A Functionality
Data to be converted is written to DACD register. The data can be mapped either to leftend or right end of DACD register by clearing or setting DJM bit of DACC0 register.Also, the data written to DACD can be a signed or unsigned data depending on DSGN
bit of DACC0 register. See the table for data formats. The maximum unsigned data thatcan be written to DACD register is $FF while the minimum value is $00. If the data issigned, the maximum value that can be written to DACD is $7F while the minimumvalue is $80, where $7F(signed) corresponds to $FF(unsigned) and $80(signed)corresponds to $00(unsigned). Table shows this characteristic between signed,unsigned data values and their corresponding voltage output. See the table markedsigned and Unsigned data and DAC Output Codesfor DAC signed and un-signed dataand DAC output codes. One thing to also note is to be sure that the DACOE is set inorder for the output to be driven onto the D/A pin.
Data Formats
Signed and Unsigned data and DAC Output Codes
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Conversion of the data in DACD register takes place as soon as DACE bit of DACC0 isset. The transfer characteristic of the dac module is shown in the figure below,DAC_8B1C Transfer Function.
DAC_8B1C Transfer Function