003-hcs12 instruction set (1)

8/10/2019 003-HCS12 Instruction Set (1)

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HCS12 Technical TrainingModule 3 - Instruction Set, Slide 1

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001.

HCS12

Instruction set


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INSTRUCTION SET

Data Handling

Arithmetic

Logic

Data Test

Branch

Jump & Subroutine Calls


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DATA HANDLING INSTRUCTIONS(DATA MOVEMENT)

(M) R(M+1) R

FUNCTION MNEMONIC OPERATION

LOAD ACMLTR LDAA

LDAB (M) B

LOAD 16 BIT REG

LOAD LEAX X

LEAY Y

LEAS SP

LDDLDXLDYLDS

H

L

(M) A

EXAMPLE: LEAX B,Y

Y

B

X REG 2025

+ACCB

2 5

Y

2000MEM


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DATA HANDLING INSTRUCTIONS

(DATA MOVEMENT)

R (M)R (M+1)


STORE ACMLTR STAA

STAB

A (M)

B (M)

STORE 16 BIT REG STD

STX

STY

STS

H

L

PUSH DATA

TO STACK

PSHA

PSHBPSHC

PSHD

PSHX

PSHY

PULL DATA

FROM STACK PULB

PULC

PULDPULX

PULY

PULA

MOVE MOV MEM MEM

EXAMPLE: MOVW 2,X+ , 2,-Y

(SP)

(SP) - 1 SP

( REG) M

(M ) REG(SP)

(SP) - 2 SP(R : R ) (M ):(M )(SP) (SP+1)H L

(SP) + 1 SP

(M ):(M ) R : R

(SP) + 2 SP

LH(SP) (SP)+1


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STACK OPERATION

MEM

TOP OF STACK

EXAMPLE:

PSHX

BEFORE

MEM

XHXL

TOP OF STACK

PSHX

AFTER

INCREASINGADDRESSES

INCREASINGADDRESSES

SP$3FFE

SP $4000SP $3FFF

SP $4000

B7 B0 B7 B0


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(TRANSFER AND EXCHANGE)


TRANSFER DATA

TRANSFER REG TO REG TFR A, B, CCR, D, X, Y, SP

A, B, CCR, D, X, Y, SP

EXCHANGE EXG A, B, CCR, D, X, Y, SP

A, B, CCR, D, X, Y, SP

TBATAB

TXSTYS

TSX

TSY

XGDX

XGDY

EXCHANGE DATA

B AA B

R SP

SP R

D X

D Y

EXAMPLE1: TFR X ,A

EXAMPLE2: EXG Y ,B


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HCS12 Technical TrainingModule 3 - Instruction Set, Slide 7MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001.


(ALTER DATA)


DECREMENT DECDECADECB

DEXDEYDES

(M)-1 (M)A-1 AB-1 B

X-1 XY-1 YS-1 S

INCREMENT INCINCAINCB

INXINYINS

(M)+1 (M)A+1 AB+1 B

X+1 XY+1 YS+1 S


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(ALTER DATA)


COMPLEMENT, 2'S(NEGATE)

NEGNEGANEGB

COMCOMACOMB

COMPLEMENT, 1'S

CLEAR CLRCLRACLRB

0-(M) (M)0-A A0-B B

(M) (M)A AB B

0 (M)0 A0 B

BIT(S) CLEAR BCLR (M) MASK (M)

BIT(S) SET BSET (M) + MASK (M)

Bit Manipulation Example: BSET OFFSET,X, #MASK


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MININUM OF TWOUNSIGNED 8-BIT

VALUE


MIN ((A), (M)) (A)MINA


VALUE

MIN ((A), (M)) (M)MINM

MAXIMUM OF TWOUNSIGNED 8-BIT

VALUE

MAX ((A), (M)) (A)MAXA


VALUE

MAX ((A), (M)) (M)MAXM

LOOP MINA 1,X+BHS LOOP


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VALUE


MIN ((D), (M:M+1)) (D)EMIND


VALUE

EMINM


VALUE

MAX ((D), (M:M+1)) (D)EMAXD


VALUE

EMAXM

MIN ((D), (M:M+1))

M:M+1

MAX ((D), (M:M+1))

M:M+1


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(SHIFT AND ROTATE)


ROTATE LEFT ROLROLAROLB

MAB

ROTATE RIGHT RORRORARORB

MAB

SHIFT LEFT,ARITHMETIC(LOGICAL)

ASL(LSL)ASLA(LSLA)ASLB(LSLB)ASLD(LSLD)

MABD

SHIFT RIGHT,ARITHMETIC

ASRASRAASRB

MAB

SHIFT RIGHT,LOGICAL

LSRLSRALSRBLSRD

MABD

C b7 b0

C b7 b0

C b7 b0

0

C b15 b0

0A B

Cb7 b0

0

0

Cb7 b0

Cb15 b0

A B


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DATA TEST INSTRUCTIONS

R -(M+1)R -(M)-C

FUNCTION MNEMONIC TEST

BIT TEST BITABITB

A (M)B (M)

COMPARE CBACMPA

CMPB

CPDCPXCPY

TEST, ZERO OR

MINUS

TST

TSTATSTB

A-BA-(M)

B-(M)

(M)-0

A-0B-0

L

H

COMPARE STACK CPS SP - ( M :M +1)


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CONDITIONAL BRANCH INSTRUCTIONS (1 0F 3)

MNEMONIC CONDITION CCR TEST INDICATION

(L) BMI MINUS N=1 r=NEGATIVE

(L) BPL PLUS N=0 r=POSITIVE

*(L) BVS OVERFLOW V=1 r=SIGN ERROR

*(L) BVC NO OVERFLOW V=0 r=SIGN OK

*(L)BLT LESS [N V]=1

*(L)BGE GREATER OR EQUAL [N V]=0

A < M

A >= M

* (L)BLE LESS OR EQUAL [Z+(N V)]=1 A M

(L)BEQ EQUAL Z=1 A=M

(L) BNE NOT EQUAL Z=0 A M

(L)BHI HIGHER [C+Z]=0 A > M

(L) BLS LOWER OR SAME [C+Z]=1 A = M

(L) BCS (BLO) CARRY SET C=1 A < M

Indicationrefers to theuse of aCMPA Minstruction

immediatelybefore thebranch

*Use for signed

arithmetic only


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CONDITIONAL BRANCH INSTRUCTIONS (2 0F 3)

DECREMENT & BRANCH DBEQ COUNTER - $01 COUNTERIF COUNTER =0, THEN (PC)+$0003 +REL PC

DBNE COUNTER - $01, COUNTERIF COUNTER 0, THEN (PC)+$0003 +REL PC

INCREMENT & BRANCH IBEQ COUNTER + $01 COUNTERIF COUNTER =0, THEN (PC)+$0003 +REL PC

IBNE COUNTER + $01 COUNTERIF COUNTER 0, THEN (PC)+$0003 +REL PC

TBEQ IF COUNTER = 0, THEN PC+$0003 + REL PC

TBNE IF COUNTER 0, THEN PC+$0003 + REL PC

EXAMPLE:-

LOOP MOVW $1000, 2,X+DBNE D,LOOP

--


TEST & BRANCH


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BRANCH IF BITS SET OR CLEAR (3 of 3)

SINGLE INSTRUCTION TO LOGICALLY "AND" MASK WITH OPERAND AND

BRANCH IF BITS ARE EITHER SET OR CLEARED.

USEFUL FOR POLLING INTERRUPT STATUS FLAGS, AND FOR MAKING PROGRAM

DECISIONS BASED ON BIT(S) VALUES.

BRANCH IS TAKEN FROM NEXT INSTRUCTION ADDRESS (OCL+4, 5, OR 6 )

ADDESSING MODES ALLOWED ARE: DIR, EXT, IDX,IDX1 & IDX2.

EXAMPLE:

WAIT BRCLR PORTD,Y $80, WAIT

BRSET

BRCLR(M) MASK SERVICE

OP CODE

OPERAND

MASK

BRANCH DISP.

OCL


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IF NUMERATOR IS GREATER THAN OR EQUAL TO THE DENOMINATOR,

FRACTIONAL DIVIDE FDIV

RADIX POINT OF THE RESULT IS TO THE LEFT OF THE MSB

THEN V FLAG IS SET.

RESULT EXAMPLES:

A RESULT OF 1 IS 1/$10000 WHICH IS .0001A RESULT OF $C000 IS $C000/$10000 WHICH IS .75A RESULT OF $FFFF IS $FFFF/$10000 WHICH IS .9999

ARITHMETIC INSTRUCTIONS (4 of 4)

FRACTIONAL DIVIDE INSTRUCTION


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A + (M) AB + (M) BD + (M+1) D ; D + M + C D


ADD ADDAADDBADDD L HL H

ADDACCUMULATORS

ABAABXABY

A + B AX + B XY + B Y

ADD WITH CARRY ADCA

ADCBA + M + C AB + M + C B

DECIMAL ADJUST DAA CONVERTS BINARY ADDITION OFBCD CHARS INTO BCD FORMAT


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A (M)B (M) BD (M+1) D ; D (M)C D


SUBTRACT SUBASUBBSUBD L HL H

SUBTRACTACCUMULATORS

SBA AB A

SUBTRACT WITHCARRY

SBCASBCB

A(M)C AB(M)C B

A

EXTENDED MULTIPLY EMUL D * Y Y : D

EXTENDED MULTIPLY EMULS D * Y Y : DSIGNED

MULTIPLY MUL A * B D


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DIVIDE INSTRUCTIONS

OPERATION D REG / X REG

RADIX POINT OF THE RESULT IS TO THE RIGHT OF THE LSB

INTEGER DIVIDE IDIV/IDIVS

EXTENDED DIVIDE 32-BIT BY 16-BIT ( [UN ]SIGNED) EDIV/EDIVS

RESULT QUOTIENT IS IN XREMAINDER IS IN D

EDIV EXAMPLE: EDIV[ S ]

OPERATION (Y:D)/ (X) Y; REMAINDER D

V = 1, IF RESULT > $FFFF FOR UNSIGNED, UNDEFINED IF DIVISOR IS $0000V = 1, IF RESULT > $7FFF FOR SIGNED, UNDEFINED IF DIVISOR IS $0000

C = 1, IF DIVISOR WAS $0000


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EXTENDED MULTIPLY AND ACCUMULATE

(EMACS)

OPERATION: (M : M ) * (M : M ) + M ~ M+3) M ~ M+3(X) (X+1) (Y) (Y+1)

X Y

EXAMPLE:

EMACS $2500 (* 32-BIT RESULT *)

15 0 15 0


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LOGIC INSTRUCTIONS

A (M) AB (M) B


AND ANDAANDB

ANDCC CCR MASK CCR

EXCLUSIVE OR EORAEORB

A (M) AB (M) B

INCLUSIVE OR ORAAORAB B + (M) B

A + (M) A

ORCC CCR + MASK CCR


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JUMP AND BRANCH INSTRUCTIONS

PC (M ), SP-1 SPPC (M ), SP-1 SP(M) PC , (M+1) PC

SPSP

HL

FUNCTION MNEMONIC OPERATION/BRANCH TEST

NO OPERATION NOP PC ADVANCES TO NEXT INST.

JUMP TO ADDRESS JMP (M) PC , (M+1) PCH L

JUMP TO SUBROUTINE JSR

LH

RETURN FROM SUBRTN RTSSP+1 SP,(M ) PCSP+1 SP,(M ) PC

L

H

BRANCH TO SUBRTN

BRANCH ALWAYSBRANCH NEVER

BSR

BRABRN

NO TESTNO TEST, PC NEXT INST.

SP

SP

PC (M ), SP-1 SPPC (M ), SP-1 SP(M) PC , (M+1) PC

SP

SPH

L

H


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CONDITION CODE REGISTER INSTRUCTIONS


CLEAR CARRYCLEAR INTERRUPT MASK

CLEAR OVERFLOWSET CARRYSET INTERRUPT MASKSET OVERFLOWACCUMULATOR A CCRCCR ACCUMULATOR A

CLCCLI

CLVSECSEISEVTAPTPA

0 C0 I

0 V1 C1 I1 VA CCRCCR A

OR CONDITION CODE ORCC CCR + OPERAND

AND CONDITION CODE ANDCC CCR ^ OPERAND


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CLEAR RAM ROUTINE

Write a routine to clear the HCS12 RAM memory, assume RAM begins at $5000

and ends at $5FFF.

003-hcs12 instruction set (1)

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