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DESCRIPTIONhcs12 timer, How to program HCS12 microcontroller
Chapter 8 HCS12 Timer Functions
Why are Timer Functions Important? y p It is very difficult and impossible to implement the following applications without a timer function: g pp Time delay creation and measurement Period and pulse width measurement Frequency measurement Event counting Arrival time comparison Time-of-day tracking Periodic interrupt generation Waveform generation g
The HCS12 Timer System (1 of 2) y The HCS12 has a standard timer module (TIM) that consists of: Eight channels of multiplexed input capture and output compare functions. 16-bit pulse accumulator A p 16-bit timer counter The TIM block diagram is shown in Figure 8.1.
The HCS12 devices in the automotive family have implemented an Enhanced Capture Timer module ( p (ECT). The ECT module contains: ) All the features contained in the TIM module One 16-bit buffer register for each of the input capture channels Four 8-bit pulse accumulator A 16-bit Modulus Down Counter with 4-bit prescaler p Four user selectable delay counters for increasing input noise immunity
The TIM (of course ECT also) shares the eight Port T pins (IOC0IOC7).
The HCS12 Timer System (2 of 2)Bus clock Prescaler Channel 0 Input Capture Output compare Timer overflow interrupt Channel 1 16-bit counter Input Capture Output compare Channel 2 Input Capture TC0 interrupt TC1 interrupt TC2 i t interrupt t TC3 interrupt TC4 interrupt TC5 interrupt TC6 interrupt TC7 interrupt PA overflow interrupt i t t PA input interrupt Registers Output compare Channel 3 Input Capture Output compare Channel 4 Input Capture Output compare Channel 5 Input C Capture Output compare Channel 6 Input Capture Output compare 16-bit Pulse accumulator A Channel 7 Input Capture Output compare IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
Figure 8.1 HCS12 Standard Timer (TIM) block diagram
Timer Counter Register ( g (TCNT) ) Required for input capture and output compare functions Must be accessed in one 16-bit operation in order to obtain the correct value Three other registers related to the operation of the TCNT: TSCR1, TSCR2, TFLG2.
Timer System Control Register 1 (TSCR1)7 value after reset TEN 0 6 5 4 3 0 0 2 0 0 1 0 0 0 0 0 TSWAI TSFRZ TFFCA 0 0 0 TEN -- timer enable bit
The contents of TSCR1 are shown i Fi h in Figure 8 2 8.2. Setting and clearing the bit 7 of TSCR1 will start and stop the counting of the TCNT. TCNT Setting the bit 4 will enable fast timer flag clear function. If , this bit is clear, then the user must write a one to a timer flag in order to clear it.
0 = disable timer; this can be used to save power consumption 1 = allows timer to function normally ll i f i ll TSWAI -- timer stops while in wait mode bit 0 = allows timer to continue running during wait mode 1 = disables timer when MCU is in wait mode TSFRZ -- timer and modulus counter stop while in freeze mode 0 = allows timer and modulus counter to continue running while in freeze mode 1 = disables timer and modulus counter when MCU is in freeze mode TFFCA -- timer fast flag clear all bit g g y 0 = allows timer flag clearing to function normally 1 = For TFLG1, a read from an input capture or a write to the output compare channel causes the corresponding channel flag, CnF, to be cleared. For TFLG2, any access to the TCNT register clears the TOF flag. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG register. Any access to the PACN1 and PACN0 registers clears the i t A t th d i t l th PBOVF flag in the PBFLG register. Figure 8.2 Timer system control register 1 (TSCR1)
Timer System Control Register 2 (TSCR2) (1 of 2) Bit 7 is the TCNT overflow interrupt enable bit bit. TCNT can be reset to 0 when TCNT equals TC7 by setting bit 3 of TSCR2. The clock input to TCNT can be prescaled by a factor selecting by bits 2 to 0 of TSCR2. Th contents of TSCR2 are shown i Fi The t t f h in Figure 8 2 8.2.
Timer System Control Register 2 ( y g (TSCR2) ) (2 of 2)7 value after reset TOI 0 6 0 0 5 0 0 4 0 0 3 TCRE 0 2 PR2 0 1 PR1 0 0 PR0 0
Table 8.1 Timer counter prescale factor PR2 PR1 PR0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Prescale Factor 1 2 4 8 16 32 64 128
TOI -- timer overflow interrupt enable bit 0 = interrupt inhibited 1 = interrupt requested when TOF flag is set TCRE -- timer counter reset enable bit 0 = counter reset inhibited and counter free runs 1 = counter reset by a successful output compare 7 If TC7 = $0000 and TCRE = 1, TCNT stays at $0000 continuously. If TC7 = $FFFF and TCRE = 1, TOF will never be t h b set when TCNT rolls over from $FFFF t $0000. ll f to $0000 Figure 8.3 Timer system control register 2 (TSCR2)
Timer Interrupt Flag 2 Register ( p g g (TFLG2) ) Only bit 7 (TOF) is implemented. Bit 7 will be set whenever TCNT overflows.
Input Capture Functions (1 of 2) Physical time is often represented by the contents of the main timer timer. The occurrence of an event is represented by a signal edge (rising or falling edge). The time when an event occurs can be recorded by latching the count of the main timer when a signal edge arrives as illustrated in Figure 8.4. g p p The HCS12 has eight input capture channels. Each channel has a 16-bit capture register, an input pin, edge-detection logic, and interrupt generation logic. Input capture channels share most of the circuit with output compare functions. For this reason, they cannot be enabled simultaneously. f ti F thi th tb bl d i lt lRising edge or Falling edge
Figure 8.4 Events represented by signal edges
Input Capture Functions (2 of 2) The selection of input capture and output compare is done by programming the TIOS register. The contents of the TIOS register are shown in Figure 8.5. Setting a bit select the output compare function. Otherwise, the input capture function is selected.7 6 5 4 3 2 1 0 value after reset IOS7 0 IOS6 0 IOS5 0 IOS4 0 IOS3 0 IOS2 0 IOS1 0 IOS0 0
IOS[7:0] -- Input capture or output compare channel configuration bits 0 = The corresponding channel acts as an input capture 1 = The corresponding channel acts as an output compare Figure 8.5 Timer input capture/output compare select register (TIOS)
The following instruction will enable the output compare channels 7...4 and g p p input capture channel 30: movb #$F0,TIOS
Timer Port Pins Each port pin can be used as a general I/O pin when timer function is not selected. selected Pin 7 can be used as input capture 7, output compare 7 action and pulse accumulator input action, input. When a timer port pin is used as a general I/O pin, its direction is configured by the DDRT register.
Timer Control Register 3 and 47 6 5 4 3 2 1 0
value The signal edge to afte r re s e t be captured is selected by TCTL3 and TCTL4. The edge to be captured is selected by two bits. The user can choose to capture the rising edge, falling edge, or both edges.
ED G 7 B ED G 7 A ED G 6 B ED G 6 A ED G 5 B ED G 5 A ED G 4 B ED G 4 A 0 0 0 0 0 0 0 0
(a) Tim e r c o ntro l re giste r 3 (TC TL3 ) 7 6 5 4 3 2 1 0
ED G 3 B ED G 3 A ED G 2 B ED G 2 A ED G 1 B ED G 1 A ED G 0 B ED G 0 A 0 0 0 0 0 0 0 0
(b) Tim e r c o ntro l re gis te r 4 (TC TL4 ) ED G nB ED G nA -- Edge c o nfiguratio n 0 0 1 1 0 1 0 1 : : : : C apture t C apture C apture C apture dis able d di bl o n ris ing e dge s o nly o n falling e dge s o nly o n bo th e dge s
Figure 8 .5 Tim e r c o ntro l re gis te r 3 and 4
Timer Interrupt Enable Register ( p g (TIE) ) The arrival of a signal edge may optionally generate an interrupt to the CPU CPU. The enabling of the interrupt is controlled by the Timer Interrupt Enable Register. Register7 C7I reset: 0 6 C6I 0 5 C5I 0 4 C4I 0 3 C3I 0 2 C2I 0 1 C1I 0 0 C0I 0
C7I-C0I: input capture/output compare interrupt enable bits 0 = interrupt disabled 1 = interrupt enabled Figure 8.7 Timer interrupt enable register (TIE)
Timer Interrupt Flag 1 Register ( p g g (TFLG1) ) Whenever a signal edge arrives, the associated timer interrupt flag will be set to 1 1.7 C7F reset: 0 6 C6F 0 5 C5F 0 4 C4F 0 3 C3F 0 2 C2F 0 1 C1F 0 0 C0F 0
CnF: input capture/output compare interrupt flag bits 0 = interrupt condition has not occurred 1 = interrupt condition has occurred Figure 8.8 Timer interrupt flag register 1 (TFLG1)
How to Clear a Timer Flag Bit In normal mode write a 1 to the flag bit to be cleared mode, cleared. Method 1 Use the BCLR instruction with a 0 at the bit position(s) corresponding to the flag(s) to be cleared. For example, BCLR TFLG1, $FE will clear the C0F flag. g
Method 2 Use the movb instruction with a 1 at the bit position (s) corresponding to the flag (s) to be cleared. For example, movb #$01,TFLG1
will clear the C0F flag.
When fast timer flag clear function is enabled, see Figure 8.1.
Applications of Input Capture Function E Event arrival ti t i l time recording Period measurement: need to capture the main timer values corresponding to two consecutive rising or falling edgesone period p
( ) p (a) Capture two rising edges g g one period
(b) Capture two falling edges Figure 8.9 Period measurement by capturing two consecutive edges
- Pulse width measurement: need to capture the rising and falling edgesPulse width
Figure 8.10 Pulse-width measurement using input capture
Input Capture Interrupt generation: Each input capture function can be used as an edgesensitive interrupt source source. Event counting: count the number of signal edges arrived during a periode1 e 2 e3 e4
Start of interval Figure 8.11 Using an input-capture function for event counting
End of interval
- Time reference: often used in conjunction with an output compare functio