hcs12 timer system.pdf

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    The HCS12 Timer System

    These notes pertain specifically to the MC9S12DP256B derivative of the family of HCS12 Microcontrollers

    The HCS12 has a standard timer module (TIM) that consists of:

    Eight channels of multiplexed input capture and output compare functions. 16-bit pulse accumulator A 16-bit timer counter

    The TIM block diagram is shown in the diagram. The Bus Clock for the MC9S12DP256B runs at 24 MHz

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    Timer Functions allow for the following applications to be implemented Time delay creation and measurement Period and pulse width measurement Frequency measurement Event counting Arrival time comparison Time-of-day tracking Periodic interrupt generation Waveform generation

    Components of the Timer Module (TIM) Eight channels that can be configured for Input Capture or Output Compare applications - IOCx The TIM shares the eight Port T pins with IOC0IOC7. Each Port pin can be used as a general I/O pin when timer functions are not selected. Pin 7 can be used for Input Capture, Output Compare and pulse accumulator input. To use a Port pin as a general I/O pin its direction must be configured by the DDRT register. The Bus Clock for the TIM is the HCS12 system clock for the MC9S12DP256B this is 24 MHz Timer Counter Register (TCNT) - address $0044. This is a 16 bit free running counter clocked by the Timer System clock which runs at the Bus clock frequency of 24 MHz or pre-scaled versions of this clock.

    Required for Input Capture and Output Compare functions Must be accessed in one 16-bit operation in order to obtain the correct value order There are numerous other registers related to the operation of the TCNT: TIOS, TIE, TSCR1, TSCR2, TFLG1, TFLG2, TCLT3, TCLT4.

    Registers that must be programmed to control the desired functions TIM System Registers When a value of TCNT is read for a particular channel the counter value is automatically copied in to a register - TC0 to TC7. TC0 - Timer Input Capture/Output Compare Register 0 - address $0050 TC1 - Timer Input Capture/Output Compare Register 1 - address $0052 . . . TC7 - Timer Input Capture/Output Compare Register 7 - address $005E

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    Timer System Control Register 1 (TSCR1) - address $0046 The main use of this register is to enable or disable the timer

    Setting and clearing bit 7 (TEN) of TSCR1 will also start and stop the counting of the TCNT counter. Setting bit 4 (TFFCA) will enable fast timer flag clear function. If this bit is clear, then the user must write a one to a timer flag in order to clear it. TEN Timer Enable bit

    0 - disable timer - can be used to save power 1 - enable timer

    TSWAI - timer stops while in wait mode

    0 - allows timer to continue running during wait mode 1 - disables timer when HCS12 is in wait mode

    TSFRZ - timer and modulus counter stop while in freeze mode

    0 - allows timer and modulus counter to continue running during freeze mode 1 - disables timer and modulus counter when HCS12 is in freeze mode

    TFFCA - timer fast flag clear all bit

    0 - allows timer flag clearing to work normally 1 - for TFLG1, a read from an input capture or a write to the output compare channel causes

    the corresponding channel flag, CnF, to be cleared. For TFLG2, any access to the TCNT register clears the TOF flag. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register.

    Timer System Control Register 2 (TSCR2) - address $004D The main use of this register is to set the pre-scale value for the timer clock frequency

    TOI - timer overflow interrupt enable bit

    0 - disable interrupt 1 - enable interrupt when TOF flag is set

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    TCRE - timer counter reset enable bit 0 - counter reset disabled counter runs free 1 - counter reset by a successful

    output compare 7 PR2, PR1, and PR0 set the pre-scale values for dividing the Bus clock Pre-Scale Computations The Timer function of the HCS12 microcontroller uses a 16 bit free-running counter called TCNT. The maximum count is 216 -1 with a total of 216 = 65,536 counts (0 to 65535 counts). The MC9S12DP256B microcontroller has an E Clock of 24 MHz. The longest time that can be measured with this clock and a pre-scale value of 1 is thus:

    Tlongest = 65,536/24Mhz = 2.74 msec.

    The use of a pre-scale factor larger than 1 is necessary if measuring longer times. Pre-scale values range from 1 to 128 in binary multiples. If the pre-scale value is 2, then the value of the pre-scaled Timer clock is Pre-scaled clock = 24 MHz /2 = 12 MHz The Table shows the choice of possible pre-scale values

    Pre-scale value E Clock Pre-scaled clock Max time delay

    2 24 MHz 12 MHz 2.74 msec

    4 24 MHz 6 MHz 10.9 msec

    8 24 MHz 3 MHz 21.8 msec

    16 24 MHz 1.5 MHz 43.7 msec

    32 24 MHz 750 kHz 87.4 msec

    64 24 MHz 375 kHz 175 msec

    128 24 MHz 187.5 kHz 350 msec

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    Questions What pre-scale value is needed to measure a time delay of 100 msec? What pre-scale value is needed to measure a time delay of 500 msec? Timer Interrupt Flag Register 2 (TFLG2) - address $004F

    7 6 5 4 3 2 1 0

    TOF 0 0 0 0 0 0 0

    Only bit 7 is used. Bit 7 will be set when overflow of TCNT occurs

    Timer Function Applications Input Capture Function The HCS12 has eight Input Capture channels. Each channel has a 16-bit capture register, an input pin, edge-detection logic, and interrupt generation logic. Input Capture channels share most of the circuit with Output Compare channels so they cannot be enabled simultaneously for anyone channel. The selection of Input Capture or Output Compare for a channel is done by programming the TIOS register. TIOS Register address $0040 This register is used to select the Input Capture or Output Compare functions for each channel.

    When an Input Capture event occurs the current value of the 16 bit counter TCNT is copied into the corresponding Timer Input Capture/Output Compare Register - TCx.

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    Example: The command movb #$F0, TIOS will enable channels 0 to 3 as Input Capture and channels 4 to 7 as Output Compare. Use of Input Capture Physical time is often represented by the contents of the main timer. The occurrence of an event is represented by a rising or falling edge of a signal waveform. The time when an event occurs can be recorded by latching the count of the main timer into a register when a signal edge arrives as illustrated in the diagram. Timer Control Registers 3 and 4 (TCTL3 and TCTL4) - address $004A and $004B The signal edge to be captured is specified by TCTL3 and TCTL4 and can be a rising edge, a falling edge or both edges. Timer Interrupt Flag Register 1 (TFLG1) - address $004E

    7 6 5 4 3 2 1 0

    C7F C6F C5F C4F C3F C2F C1F C0F

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    As the counter TCNT counts up it is compared with the appropriate TCx register after each count. If they match the corresponding bit for that channel is set to a 1. In appropriate applications such as Input Capture, this would indicate that an edge has been detected. To clear a bit in TFLG1, write a 1 to the appropriate bit. Alternately setting the TFFCA bit in the TRSC1 register allows the clearing of a flag by reading the corresponding Input Capture register or writing a value to the Output Capture register. Applications of Input Capture Input Capture can be used as an Event Arrival Time Recording mechanism. The period of a waveform can be measured by capturing the TCNT timer value for two corresponding rising or falling edges. Measurement of Period Measurement of Pulse Width The pulse width of a waveform can be measured by capturing consecutive rising and falling edges.

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    If period and pulse width have both been measured then the Duty Cycle of a waveform can be determined. Calculation of Duty Cycle

    Programming with the Input Capture Function The following Flow Chart and program code illustrate how to use the Input Capture function to measure the period of a TTL level square wave connected to channel 0. The program initially is configured to capture a rising edge of the wave form on channel 0, the pre-scale factor is set to 16, the C0F flag is cleared and then the timer counter is enabled. The code waits for the first rising edge to arrive, stores the TCNT value in memory, clears the C0F flag again, captures the next rising edge, computes the difference in the 2 stored values of TCNT and stores this value in memory.

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    When an Edge Arrives When a selected edge arrives at the input capture pin, the corresponding flag in TFLG1 is set. To proceed in the code the flag must be cleared. To clear a flag in the TFLG1 register, write a 1 to it. As an alternative if the TFFCA bit (bit 4) of the TSCR1 register is set then the required flag can be set by simply reading the corresponding input capture register or writing a new value to the output compare register. Assembler Code ; Uses Input Capture Channel 0

    TIOS: equ $40 ;address of TIOS register TSCR1: equ $46 ;address of TSCR1 register TSCR2: equ $4D ;address of TSCR2 register TCTL4: equ $4B ;address of TCTL4 register TFLG1: equ $4E ;address of TFLG1 register TC0: equ $50 ;mask values IOS0: equ $01 ;mask to select channel 0 as Input capture C0F: equ $01 ;mask to clear channel 0 edge1: ds.b 2 ; memory to hold the first edge edge2: ds.b 2 ; memory to hold the second edge period: ds.b 2 ; memory to store the