guide to draw stick diagrams in vlsi

8/9/2019 Guide to draw Stick diagrams in VlSI

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02/13/15 1

VLSI Design and Layout PracticeVLSI Design and Layout PracticeLect5 – Stick Diagram & ScalaleLect5 – Stick Diagram & Scalale

Design !ulesDesign !ules

Danny "en#$a% 'ungDanny "en#$a% 'ung

Institute o( )lectronic )ngineeringInstitute o( )lectronic )ngineering

'ung#$uan 'ristian *ni+ersity'ung#$uan 'ristian *ni+ersity

Se,t- 200.Se,t- 200.


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02/13/15 2Wen-Yaw Chung/Chung-Yuan University VLSI Design

IC Layout Concept and Exap!es

I" Stic# Diagra

II" Design $u!es

III" Layout Veri%cation

!e( 'tt,//10-135--5/4S/

http://140.135.9.56/XMS/http://140.135.9.56/XMS/


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&" 'asic Concept

(" 'ased on the view point o) IC !ayout* thestic# diagra can he!p us understand the circuit)unction and its geoetrica! !ocation re!ative toother circuit +!oc#s"

Legend:

contact

metal 2

metal 1

poly

ndiff

pdiff

VDD

in

VSS

out


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&" 'asic Concept

," &!though the stic# diagra is an a+stractpresentation o) rea! !ayout* it can use

graphica! sy+o!s or !egend to a!!ocate the

circuit to ,-dioensiona! p!ane and reach the

ai sae as the physica! !ayout does"

" .he stic# diagra is sii!ar to a +ac#+one

o) the rea! !ayout +ut without the rea! sie

and aspect ratio o) the devices* it sti!! can

re0ect the rea! condition to !ayout o) the

si!icon chip"


7/5302/13/15 7Wen-Yaw Chung/Chung-Yuan University VLSI Design

'" 1otations o) the stic# diagra



Stic# Diagra

Interediate representation +etween the transistor !eve! and the as#

2!ayout3 !eve!"

4ives topo!ogica! in)oration 2identi%es di5erent !ayers and their

re!ationship3 &ssues that wires have no width"

It is possi+!e to trans!ate stic# diagra autoatica!!y to

!ayout with correct design ru!es"

[Ref]: 育部顧問室

「超大型積體電路與系統設計」育改進計畫

DA 聯盟 – 推廣課程 Chap.1


9/5302/13/15 Wen-Yaw Chung/Chung-Yuan University VLSI Design

Stic# Diagra

1- "'en t'e same material 6on t'e same layer7 touc' or cross8 t 'ey are connected and elong to t'e same electrical node-

2- "'en po!ysi!icon crosses 9 or P di5usion8 an 9 or P transistor is (ormed- Polysilicon is dra%n on to, o( di:usion- Di:usion must e dra%n connecting t'e source and t'e drain- ;ate is automatically sel(#aligned during (arication-






Stic# Diagra

3- "'en a metal line needs to e connected toone o( t'e ot'er t'ree conductors8 a contact

cut 6via7 is re


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Stic# Diagra

6" 7anhattan geoetrica! ru!e8 When we use on!yvertica! and horionta! !ines In orthogona! todescri+e circuitry"

'oston geoetrica! ru!e8 .he stic# diagra a!soa!!ows curves to descri+e circuitry"

9" In order to descri+e 1/:7;S ore cop!ete!y* toadd n-we!!、 :< se!ect、 we!! contact and su+strate

contact are optiona! )or 6-terina! notation"


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Conc!usion

1- Stick diagram is a dra(t o( real layout8 itser+es as an astract +ie% et%een t'esc'ematic and layout-

2- Stick diagram uses di:erent lines8 colorsand geometrical s'a,es to ,resent circuitnodes8 de+ices8 and t'eir relati+e location-

3- Stick diagram doesn=t include in(ormation

aout t'e accurate coordinates and si>es o(de+ice8 t'e lengt' and %idt' o( conductorsand t'e real si>e o( %ell region-


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4?S In+erter StickDiagrams

'asic !ayout

․More area efficient layout





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C7;S inverter descri+ed in otherway"

VDD

in

VSS

out

4?S In+erter StickDiagrams


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4?S @ransmission ;ate

.he transission gate Circuit scheatic Stic# diagra


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4?S Stick Diagrams9A9D/9?!


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[Ref]:

育部顧問室



4?S Stick Diagrams9A9D


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= Exercise ( >

.o draw the )o!!owing circuitry +y using a stic# diagra


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= Exercise , >

.o draw the stic# diagra and the scheatic )or the )o!!owing !ay


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4?S Stick Diagrams[Ref]:

育部顧問室



9?!


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4?S In+erter 4askLayout

4in- s,acing andline %idt' consideration


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Lamda#ased Design !ules

Lamda design rules are ased on are(erence metric Bt'at 'as units o(um-

All %idt's8 s,acing and distances are%ritten in t'e (orm Value C m B

"'ere m is scaling multi,lier-

e-g-E BC 1um % C 2 BC2um s C 3BC3um


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Lam!da !a"ed de"ign: #alf of tec#nology "ince 185$ %" tec#nologyc#ange" &it# "malle' dimen"ion"( a "imple c#ange in t#e )alue of λ can

!e u"ed to p'oduce a ne& ma"* "et$

%ll de)ice ma"* dimen"ion" a'e !a"ed on multiple" of λ( e$g$( poly"ilicon

minimum &idt# + 2λ$ ,inimum metal to metal "pacing + 3λ

6

2

6

3

3

Lamda#ased Design !ules


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Acti+e ontact and Surround !ule


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:otentia! :ro+!e - 7isa!igne


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:otentia! :ro+!e ? Short +etween Source and Dr


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Degree o( anisotro,y A C 1 –rlat/r+ert"'ere r res,ecti+e etc' rates

:hysica! Liitations


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Design $u!e 607

Due to t'e ,'oto resolution8 concentration8tem,erature and reaction time o( t'ec'emical reagents8 t'e layout s'ould

tolerate some errors caused y ,rocessen+ironment-

In order to a+oid t'e inFuence (rom ,rocess

+ariation8 t'e layout o( t'e circuitsc'ematics s'ould (ollo% t'e design !ule。

@' ( d i


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@'e ,ur,ose o( designrules

Ref. Jan M. Rabaey, et. al, © DigitalIntegrated Circuits 2nd Edition

Inter(ace et%een designer and ,rocessengineer

;uidelines (or constructing ,rocessmasks

*nit dimension 4inimum line %idt'

scalale design rules lamda ,arameter asolute dimensions 6micron rules7


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Design !ules617

Layout ru!es are used )or preparing the as#s )or )a+rication" @a+rication processes have inherent !iitations in accuracy" Design ru!es speci)y geoetry o) as#s to optiie yie!d and

re!ia+i!ity 2trade-o5s8 area* yie!d* re!ia+i!ity3"

.hree aAor ru!es8 Wire width8 7iniu diension associated with a given

)eature" Wire separation8 &!!owa+!e separation" Contact8 over!ap ru!es"





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Design !ules627

.wo aAor approaches8 B7icron ru!es8 stated at icron

reso!ution" ru!es8 sip!i%ed icron ru!es with

!iited sca!ing attri+utes"

ay +e viewed as the sie o) iniu)eature"

Design ru!es represents a to!erance whichinsures very high pro+a+i!ity o) correct)a+rication 2not a hard +oundary +etweencorrect and incorrect )a+rication3"

Design ru!es are deterined +y experience"




. i !


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.erino!ogy De%nition

7in" Width 8 .he in" width o) the !ine2!ayer3

=Exap!e> Wpo!y2in"3 F"9u

7in" Space 8 .he in" spacing +etween!ines with sae ateria!

)Gam,leE S,oly#,oly6min-7 C 0-5um

. i !


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=7in" Extension 8 .he in" extension over di5erent!ayers

=Exap!e> :o!y-gate extension over di5usion area F"99u

4in- ?+erla, @'e o+erla, et%een di:erent

layers )Gam,leE Poly1 o+erla, Poly2 min- C 0-Hum


. i !


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7ax" area o) the speci%c region"

=Exap!e> 'onding :ad &rea* ax" (FFu x (FFu

ti l L


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on+entional LayerDenition


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S4?S Design !ules

$e)" Gan 7" $a+aey* et" a!* H Digita! Integrated Circuits ,nd Edition


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S4?S Design !ules

1

2

1

Via

Metal to

Poly ContactMetal toActive Contact

1

2

5

4

3 2

2


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S4?S Design !ules

1

3 3

2

2

2

WellSubstrate

Select

3

5


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S4?S Design !ules




4?SIS Layout Design


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4?SIS Layout Design!ules

7;SIS design ru!es 2SC7;S ru!es3 are avai!a+!e athttp8//www"osis"org"

+asic design ru!es8 Wire width Wire separation Contact ru!e

4?SIS design rule eGam,les

[Ref]:

育部顧問室


DA

聯盟 – 推廣課程

Chap.1


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III" Layout Veri%cation

&" De%nition

D$C ? Design $u!e Chec#

E$C ? E!ectrica! $u!e Chec# LVS ? Layout Versus Scheatic

L:E ? Layout :araeter

Extraction


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Layout Veri%cation

'" D$C2Design $u!e Chec#3：

> .o chec# the in" !ine width andspacing +ased on the design ru!es"

C" E$C2E!ectrica! $u!e Chec#3：

> .o chec# the short circuit

+etween :ower and 4round* or chec#the 0oating node or devices"


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Layout Veri%cation

D" LVS2Layout versus Scheatic3：

> .o veri)y the consistency +etween Scheatic

and Layout" @or exap!e： to chec# the aount o)

transistor nu+ers* sies o) W/L"

E" L:E or :E2Layout :araeter

Extraction3：

> @ro the data+ase o) !ayout* to extract thedevices with parasitics inc!uding e5ective W/L*

parasitic capacitances and series resistance" .he

extracted %!e is in S:ICE )orat and can +e used )or

:ost-Layout Siu!ation。


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Layout Veri%cation

F. Simulationsre!"ayout Simulation ! before layout #or$

ost!"ayout Simulation % after layout #or$, &ost layout

simulation #ill reflect more realistic circuit &erformance.


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Layout Veri%cation

.he cop!ete design environent o) @i!!-Custo De Design data+ase ? Cadence Design @raewor# II

Circuit Editor ? .ext editor/Scheatic editor 2S-edit* Coposer3Circuit Siu!ator ? S:ICE*.S:ICE* JS:ICELayout Editor ? Cadence Virtuoso* La#er* L-editLayout Veri%cation Diva* Dracu!a* Ca!i+re* Jercu!es


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oncluding !emarks

7i!estones techno!ogy in si!icon era .ransistor Integrated Circuits C7;S .echno!ogy

Key weapons in S;C era

Design &utoation

Design $euse

'rea#through techniues in design autoation

Siu!ation 2e"g"* S:ICE* Veri!og-L* etc"3

&utoatic :!aceent and $outing 2&:$3

Logic Synthesis 2e"g"* Design Copi!er3

@ora! Veri%cation

.est :attern 4eneration

It is ED' t(at &us(es t(e IC design tec(nology for#ard )

[Ref]:

育部顧問室


DA

聯盟 – 推廣課程

Chap.1


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M$e)"N Gohn :" Uyeura* B:hysica! Design o) C7;SIntegrated Circuits Using L-EDI.* :WS :u+!ishing Copany*

SC1& Layout $u!es


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SC1& Layout $u!es


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SC1& Layout $u!es


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SC1& Layout $u!es


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SC1& Layout $u!es


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SC1& Layout $u!es


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LAJ- 3

SetK1 – Stick Diagram Practice

SetK2 – !e+erse )ngineering

guide to draw stick diagrams in vlsi

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