Stick Diagrams

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<p>STICK DIAGRAMS</p> <p>1</p> <p>STICK DIAGRAM:green,, yellow Red Blue Yellow Black n-diffusion, p-difffusion Polysilicon Metal Implant Contact areas</p> <p>2</p> <p>NMOS ENHANCEMENT TRANSISTOR:</p> <p>When polysilicon crosses n-diffusion a transistor forms n-diffusion</p> <p>polysilicon</p> <p>3</p> <p>NMOS DEPLETION TRANSISTOR:implant diffusion</p> <p>polysilicon</p> <p>4</p> <p>PMOS ENHANCEMENT TRANSISTOR:</p> <p>When polysilicon crosses p-diffusion a transistor forms</p> <p>P-diffusion</p> <p>polysilicon5 5</p> <p>STICK DIAGRAM FOR NMOS INVERTER:</p> <p>vin gnd</p> <p>6</p> <p>STEP1:</p> <p>Draw metal(blue) VDD and GND rails in parallel with enough separationVDD</p> <p>GND7</p> <p>STEP2:Forming transistorsVDD</p> <p>vin gnd</p> <p>GND8</p> <p>STEP2-1:</p> <p>vin gnd Vin</p> <p>9</p> <p>STEP3:</p> <p>interconnections</p> <p>vin gnd</p> <p>Vout</p> <p>10</p> <p>STEP4:</p> <p>Contact pointsVDD</p> <p>vin gnd</p> <p>Vout</p> <p>VinGND11</p> <p>Vdd</p> <p>A nand B A</p> <p>B</p> <p>Vss</p> <p>12</p> <p>Nmos NAND GATEVdd</p> <p>Ploy(G)</p> <p>Vout(A nand B) D A s D B Ploy(G) s Vss Ploy(G)</p> <p>13</p> <p>Nmos NOR GATEVdd</p> <p>A nor B A B</p> <p>Vss</p> <p>14</p> <p>Nmos NOR GATEVdd</p> <p>Ploy(G)</p> <p>Vout(A nor B)</p> <p>D A s B</p> <p>D Ploy(G) s Vss</p> <p>15</p> <p>CMOS STICK ENCODINGSlayer color stick notation color code</p> <p>n-diffusion</p> <p>Green</p> <p>p-diffusion</p> <p>yellow</p> <p>polysilicon</p> <p>red</p> <p>metal-1</p> <p>blue</p> <p>metal-2</p> <p>dark blue or purple</p> <p>contact cut</p> <p>black</p> <p>via</p> <p>black</p> <p>demarcationline</p> <p>-------------------------------------------------------'</p> <p>brown</p> <p>16Vdd orVss contact black</p> <p>CMOS INVERTER:</p> <p>17</p> <p>STEP1:</p> <p>Draw VDD &amp; GND rails</p> <p>18</p> <p>STEP2:</p> <p>Forming transistors</p> <p>19</p> <p>STEP3:How to identify whether the transistor is nmos or pmos???????????????? Using demarcation line(----------------)</p> <p>Vdd pmos</p> <p>Demorcation line</p> <p>nmos Vss20</p> <p>STEP4:</p> <p>Inter connections</p> <p>pmosinputoutput</p> <p>Demorcaion line</p> <p>nmos21</p> <p>STEP5:</p> <p>Contact points</p> <p>VDDpmosinputoutput</p> <p>Demorcaion line</p> <p>nmos GND22</p> <p>Cmos NAND GATEVdd</p> <p>A B</p> <p>A nand B</p> <p>Vss</p> <p>23</p> <p>Cmos NAND GATEVdd contact Vdd</p> <p>s Demarcation Line D</p> <p>Ploy(G)</p> <p>s Ploy(G) D Vout(A nor B)</p> <p>A</p> <p>B D s D s Ploy(G) Ploy(G)</p> <p>Vss contact</p> <p>Vss</p> <p>24</p> <p>Cmos Nor GATEVdd</p> <p>B A A nor B</p> <p>Vss</p> <p>25</p> <p>Cmos Nor GATEVdd contact Vdd</p> <p>s Ploy(G) Demarcation Line D s Ploy(G) D</p> <p>A D s Vss contact</p> <p>Vout(A nand B) B D Ploy(G) Ploy(G) s Vss</p> <p>26</p> <p>BiCmos inverterVdd</p> <p>Vin</p> <p>Vout</p> <p>Vss</p> <p>27</p> <p>BiCmos inverter</p> <p>Vdd contact</p> <p>Vdd</p> <p>Vout Demarcation Line</p> <p>Vss contact</p> <p>Vss</p> <p>BiCmos inverterVdd</p> <p>Vin Vout</p> <p>Vss</p> <p>29</p> <p>BiCmos inverter</p> <p>Vdd contact</p> <p>Vdd</p> <p>Demarcation Line</p> <p>Vout</p> <p>Vss contact</p> <p>Vss</p> <p>30</p>