layouts and stick diagrams

8/3/2019 Layouts and Stick Diagrams

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Layout design rules:For complex processes, it becomes difficultto understand the intricacies of thefabrication process and interpret differentphoto masks.

They act as interface between the circuitdesigner and the process engineer.


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The fundamental unity in the definition of

a set of design rules is the minimum linewidth.

i.e. a design rule stands for the minimummask dimension that can be safelytransferred the semiconductor material.

Even for the same minimum dimension,design rules differ from company to company

and from process to process.

However, there are CAD tools that allowthe migration of the design between

compatible process.


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For complex processes, it becomes difficultto understand the intricacies of thefabrication process and interpret differentphoto masks.

They act as interface between the circuitdesigner and the process engineer.


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Design Rules:

N- Well

r101 Minimum width 12

r102 Between wells 12r110 Minimum well Area 1442

r 102r 101

N -

Well


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r201 Minimum N+ and P+ diffusion width 4

r 201

r 201

N -Well

P+ Diff

N+ Diff


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r202 Between two P+ and N+ diffusions 4

N -Well

P+ Diff

N+ Diff

r 202

r 202


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r203 Extra N-well after P+ diffusion 6

N -Well

P+ Diff

N+ Diff

r 203

r 203


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r204 Between N+ diffusion and n-well 6

r 204

N -Well

P+ Diff

N+ Diff


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r210 Minimum diffusion area 162

r 210

r 210

N -Well

P+ Diff

N+ Diff


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r301 Polysilicon Width 2

N -Well

P+ Diff

N+ Diff

Polysilicon

r 301

r 301

Polysilicon


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r302 Polysilicon gate on Diffusion 2

N -Well

P+ Diff

N+ Diff

Polysilicon

r 302

r 302

Polysilicon


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r307 Extra Polysilicon surrounding Diffusion 3

N -Well

P+ Diff

N+ Diff

Polysilicon

r 307

r 307

r 307

r 307

Polysilicon


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r304 Between two Polysilicon boxes 3

N -Well

P+ Diff

N+ Diff

Polysilicon

Polysilicon

r 304

r 304


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r307 Diffusion after Polysilicon 4

N -Well

P+ Diff

N+ Diff

Polysilicon

Polysilicon

r 307

r 307

r 307

r 307


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r401 Contact width 2

Contact

PolysiliconContact

Metal/Polysilicon

Contact

r 401


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r404 Extra Poly surrounding contact 1

Contact

PolysiliconContact

Metal/Polysilicon

Contact

r 404 r 404


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r405 Extra metal surrounding contact 1

Contact

PolysiliconContact

Metal/Polysilicon

Contact

r 405 r 405


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N -Well

P+ Diff

N+ Diff

Polysilicon

Polysilicon

r403 Extra diffusion surrounding contact 1

r 403

r 403


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Metal 1

Metal 2

Metal 3

Metal 4

Metal 5

Metal 6

r 501

r 501

r501 Between two Metals 4


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r510 Minimum Metal area 162

r 510 r 510

r 510r 510

r 510 r 510

Metal 1

Metal 2

Metal 3

Metal 4

Metal 5

Metal 6


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It is necessary for the polyto completely cross active,

other wise the transistor thathas been created crossingof diffusion and poly, will beshorted by diffused path of

source and drain.

2

Poly crosses diffusion

Poly does not cross diffusion

Creating a short circuit

GATE EXTENSION:


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Proper Transistor Formed Diffused Path Between Source And Drain


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NAND2 layout


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NOR2 layout


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Constructing a minimum area layoutStick diagram layout of the

complex CMOS logic gate witharbitrary ordering of poly gatecolumns.


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Ordering of polysilicon gate columns in Euler graph sequence results inuninterrupted p-type and n-type diffusion areas.

Adv: Compact area, simple routing of signals and less parasitic capacitance.


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2 I/P MUX AND ITS LAYOUT

F = (A.S+B.S)


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4 input NAND gate:


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STICKDIAGRAMS


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CONCEPT

Popular Way Of symbolic design.

Free hand layout

Colored lines for various process layers.

Poly crossing diffusion gives transistors.

Metal touching diffusion gives contacts.

C


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Concept Notation gives only relative position of

various design components.

A compactor is used to convert it intoabsolute design.

The compactor translates design rules intoconstraints on the component positions.

It also gives optimized design layout withefforts for minimization of area and costfunction.


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Pros and cons

Designer does not have to worry aboutdesign rules.

Compactor takes care of that.

Outcome of the compactor may beunpredictable and may not match manualapproach.


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Typical Stick Diagram


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Layers in the stick diagrams


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TheProcedure

ForDrawingStick

Diagrams:


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Draw stick diagrams for the above circuits.


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Back end optimization of a circuit

using

Euler's Graph approach


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Constructing a minimum area layout

Stick diagram layout of the complex CMOS logic gate


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Stick diagram layout of the complex CMOS logic gatewith arbitrary ordering of poly gate columns.

Ordering of polysilicon gate columns in Euler graph sequence results in


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Ordering of polysilicon gate columns in Euler graph sequence results inuninterrupted p-type and n-type diffusion areas.

Adv: Compact area, simple routing of signals and less parasitic capacitance.

Euler Graph Approach:


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Euler Graph Approach:(Good Density, Min Area, Abutting of S-D Connections,

Single Diffusion Strip In Both Wells, , Easy Automation)

Construction Of Logic Graph:

1. Vertices : Nodes of the N/W.

2. Edge: I/P.

3. Dual Graphs for PUN & PDN.

Identification Of Euler Paths:

1. Path through all nodes such that an edge is visited only once.

2. Uninterrupted diffusion strip in the layout is possible iff Eulerpath exists.

3. Many solutions exist.

4. Common Euler path in PUN & PDN

5. Sequence of edges in the Euler path = Order of I/Ps in the layout.


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E - D - A - B - C


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Ex: 1.


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Ex: 2.


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Ex: 3.

Effect Of Restructuring


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Ex: 3.



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Ex: 3.



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Sketch a stick diagram for a combinational circuit evaluating followingBoolean expression.

layouts and stick diagrams

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