ENHANCING SRAM PERFORMANCE OF COMMON GATE FINFET BY

USING CONTROLLABLE INDEPENDENT DOUBLE GATES

CHONG CHUNG KEONG

UNIVERSITI TEKNOLOGI MALAYSIA

ENHANCING SRAM PERFORMANCE OF COMMON GATE FINFET BY

USING CONTROLLABLE INDEPENDENT DOUBLE GATE

CHONG CHUNG KEONG

A project report submitted in partial fulfilment of the

requirements for the award of the degree of

Master of Engineering (Electrical - Computer and Microelectronic System)

Faculty of Electrical Engineering

Universiti Teknologi Malaysia

JUNE 2015

iii

DEDICATION

Specially dedicated to my beloved family, lecturers and friends

For the guidance, encouragement and inspiration

Throughout my journey of education

iv

ACKNOWLEDGEMENT

I wish to take this opportunity to express my sincere thanks to my project

supervisor Ir. Dr. Michael Tan Loong Peng, for his valuable guidance and advice in

this research. He has been very helpful with the setup of software needed to simulate,

and any technical advice throughout this research.

Besides that, I would like to thank my mangers who gave endless supports and

understanding when carried out this project research.

In addition, I would like to thank my postgraduate course-mates for their

kindness of information sharing in completing this project. Moreover, I would like to

express my thanks to my friends who supporting and encouraging me throughout this

project. Last, I’m also grateful to my family members and partner for their moral

supports.

v

ABSTRACT

This project is focus on the research and evaluation on the characteristic of

independent controllable gate FinFET structure in static random access memory

(SRAM) circuitry. BSIM-CMG model for common gate FinFET is chosen in this

research. The independent controllable gate FinFET is constructed using two parallel

connection of common gate FinFET except the gate terminal, thus it has the

independent controllable gate capability. SRAM 6T scheme is being chosen in this

study and benchmarking with the conventional common gate FinFET SRAM. Netlist

for device NMOS and PMOS, and the SRAM circuitry are being constructed and

simulated with HSPICE tool. From the device perspective, through the dynamic gate

voltage adjustment capability, the IV characteristic of this proposed structure has better

drive currents with 1.1X for NMOS and 1.3X for PMOS compare to conventional

common gate FinFET. Besides that, there is a significant reduction of leakage current

in this proposed structure compare to the conventional common gate FinFET, the

reduction leakage for NMOS and PMOS is up to 3 order magnitude. The results of the

SRAM circuitry constructed by this proposed independent controllable gate FinFET

structure has shown that the read and write margin are higher than the conventional

common gate FinFET SRAM design. Besides that, the proposed structure in SRAM

design is beneficial to low power application design as it has lower standby current.

Furthermore, different back gate bias scheme for this structure is explored, and the

optimum back gate scheme is proposed which having the reverse biased on Pull Down

device and Pull Up device, with the dynamic gate voltage control on the Pass Gate

device.

vi

ABSTRAK

Projek ini bertujuan untuk memberi penyelidikan dan penilaian tentang ciri-

ciri bebas kawalan get FinFET struktur dalam litar pegun rawak laluan ingatan

(SRAM). Dalam kajian ini, pengunaan BSIM-CMG model untuk get samaan FinFET

dipilih. Bebas kawalan get FinFET struktur dibina daripada dua sambungan selari get

samaan FinFET, dua get dibiarkan untuk membentuk ciri bebas kawalan. SRAM 6T

skema dipilih dalam kajian ini dan dibandingkan dengan get samaan FinFET SRAM.

Semua peranti NMOS, PMOS dan litar SRAM disimulasikan oleh alat HSPICE, di

mana ia merupakan industry piawai. Dari segi peranti, ciri IV untuk bebas kawalan jet

FinFET memiliki lebih banyak arus pengaliran dengan 1.1X untuk NMOS dan 1.3X

untuk PMOS dibandingkan the get samaan FinFET. Di samping itu, arus bocoran

untuk bebas kawalan get FinFET struktur adalah kurang daripada tradisi get samaan

FinFET sebanyak tiga magnitude apabila dibandingkan dengan tradisi get samaan

FinFET. Keputusan untuk bebas kawalan get FinFET struktur dalam litar SRAM

adalah lebih baik dari segi pembacaan dan penulisan margin apabila dibandingkan

dengan rekabentuk dalam tradisi get samaan FinFET SRAM. Cadangan struktur ini

dalam litar rekabentuk SRAM memberi kebaikan dalam bidang kegunaan kuasa

rendah kerana ia mempunyai arus bocor yang rendah. Di samping itu, berbeza-beza

skema belakang get voltan pincang juga disiasat dan optimum skema belakang get

voltage pincang telah diperkenalkan, di mana ia mempunyai terbalik pincang kepada

Tarik Ke-bawah dan Tarik Ke-atas peranti, dengan dinamik kawalan get voltan kepada

Lalu Get peranti.

vii

TABLE OF CONTENTS

CHAPTER TITLE PAGE

DECLARATION ii

DEDICATION iii

ACKNOWLEDGEMENT iv

ABSTRACT v

ABSTRAK vi

TABLE OF CONTENTS vii

LIST OF TABLES ix

LIST OF FIGURES x

LIST OF ABBREVIATIONS xv

LIST OF APPENDICES xvii

1 INTRODUCTION 1

1.1 Background 1

1.2 Problem Statement 2

1.3 Objectives 3

1.4 Research Scope 4

2 LITERATURE REVIEW 5

2.1 Introduction 5

2.1.1 Planar Bulk MOSFET 5

2.1.2 FinFET Device 6

2.2 Compact Modeling of BSIM-CMG 10

2.3 SRAM Operation 12

2.3.1 Standby (Hold) 12

viii

2.3.2 Read 12

2.3.3 Write 13

2.4 SRAM Performance Metrics 13

2.4.1 Static Noise Margin 13

2.4.2 Read Noise Margin 14

2.4.3 Write Noise Margin 14

2.4.4 Power and Delay 14

2.5 FinFET Based SRAM Design 15

2.5.1 Common gate FinFET SRAM 15

2.5.2 Independent gate FinFET SRAM 17

3 RESERCH METHODOLOGY 36

3.1 Introduction 36

3.2 Circuit Analysis Instrument 39

3.3 Proposed SRAM Scheme 39

3.4 SRAM Circuit Simulation 41

3.4.1 Static Noise Margin 42

3.4.2 Write Noise Margin 44

3.4.3 N-Curves 45

3.4.4 Standby Leakage 46

4 RESULTS AND DISCUSSION 48

4.1 Introduction 48

4.2 Device Parameters 48

4.3 SRAM Circuitry 51

5 CONCLUSION AND FUTURE WORK 57

5.1 Conclusion 57

5.2 Future Work 58

REFERENCES 59

Appendices A-M 62

ix

LIST OF TABLES

TABLE NO. TITLE PAGE

2.1 Simulation results of tied gate SRAM and independent

gate SRAM

19

2.2 Summary of bulk and FinFET SRAM characteristics 26

2.3 SNM and WNW of the two cells 35

3.1 Device parameters of the independent controllable gate

structure

40

4.1 Comparison of drive current (idsat) and Leakage

current (isoff) of independent controllable gate (CG)

FinFET structure and shorted gate (SG) FinFET

50

4.2 Performance metrics comparison of different type of

controllable gate FinFET SRAM with single gate

FinFET SRAM

55

x

LIST OF FIGURES

FIGURE NO. TITLE PAGE

2.1 Planar bulk MOSFET in 3D view 5

2.2 Simulated drive current and threshold voltage (Vt)

versus gate length at constant leakage current

6

2.3 FinFET structure (a) one fin tied gate (b) one fin

independent gate

8

2.4 IV curves of Independent Gate, Shorted gates and

asymmetrical shorted gates FinFET (a) NMOS device

(b) PMOS device

8

2.5 Leakage current, leakage power and power

consumption in 6T SRAM cell design using planar

bulk, shorted gate and independent gate devices

9

2.6 Drain Current characterize of NMOS IG- 10

2.7 The different multi gate FINFETs that can be simulated

by BSIM-CMG. BULKMOD selects the substrate for

Bulk or SOI , ASYMMOD enables for asymmetric IV

11

2.8 Typical 6T SRAM schematic 12

2.9 Schematic of common gate FinFET 6T SRAM cell 16

xi

2.10 6T SRAM read butterfly plots (a) planar MOSFET with

β ratio 1.5 and 2.0 (b) FinFET based with 1 fin and 2

fins.

16

2.11 Impact of number of fins in pull down devices on read

and write margins

17

2.12 Schematic design of SRAM cell using independent gate

FinFET

18

2.13 Power Leakage consumption of 6T SRAM design in

common gate FinFET (Tied) and Independent Gate

FinFET (Ind)

18

2.14 Static voltage transfer characterist of common gate

FinFET (DG-3: 3 fins at pull down) and independent

gate FinFET (IG: 1 fin at pull down)

20

2.15 Circuit schematic of Pass Gate Feedback SRAM 21

2.16 Nominal read stability for a conventional FinFET

SRAM cell and PGFB cell with ϕm values chosen to give

180mV RSNM at Vdd=0.7V

22

2.17 Nominal write ability current Iw for conventional

common gate FinFET SRAM cell and PGFB cell

23

2.18 6T SRAM cell layout (a) conventional common gate (b)

with back gate connections

24

2.19 Impact of process variation on SNM among 6T PGFB,

planar MOSFET, common gate and 4T feedback design

schemes

25

2.20 6T PUWG design with PU gates connected to a write

word line

26

xii

2.21 PUWG with PGFB design provides higher Iw at high

VDD

27

2.22 Butterfly curves for PGFB with PUWG SRAM cell

design

28

2.23 Nominal read stability with PGFB+PUWG design 29

2.24 Schematic design of row based back gate biasing for

double gate FinFET SRAM

30

2.25 Schematic of dynamic generator 31

2.26 Layout of row based back gate biased of double gate

FinFET 6T SRAM design

31

2.27 Comparison of IV curve for the device of row based

back gate bias with tie gates FinFET

32

2.28 (a) Drive current (b) Leakage current of the row based

back gate design with different back gate voltage bias

32

2.29 Read waveform of the row based gate bias with forward

bias 0.9V, 1.0V compared with conventional tied gates

(DG) FinFET SRAM

33

2.30 Write performance of the row based gate bias compared

with conventional tied gates (DG) FinFET SRAM

33

2.31 The back gate scheme design of separate wordline with

back gate of Pull Up connected to VDD

34

3.1 Flow chart of research methodology 38

3.2 Proposed SRAM scheme for this research 40

3.3 Node labelling of SRAM scheme with independent

controllable gate capability

41

xiii

3.4 Simulation setup for retention and read access mode 42

3.5 Simulation setup for SNM measurement 43

3.6 Simulation setup for write margin measurement 44

3.7 Simulation setup for N-curve measurement 45

3.8 Simulation setup for standby leakage measurement 46

4.1 IV curves of independent controllable gate (CG)

FinFET structure compared with common gate (SG)

FinFET device, (a) NMOS IV curve (b) PMOS IV

curve

49

4.2 Static Noise Margin (SNM) in (a) retention mode (b)

read access mode for Independent Controllable (CG)

FinFET SRAM and shorted gate (SG) FinFET SRAM

51

4.3 N-curves analysis curves for (a) read mode (b) write

mode

52

4.4 Schematic design for pass gate feedback scheme 52

4.5 Static Noise Margin (SNM) in (a) retention mode (b)

read access mode for Independent Controllable (CG)

FinFET SRAM in pass gate feedback scheme and

conventional shorted gate (SG) FinFET SRAM

53

4.6 Schematic design for flexi pass gate with back gate of

pull up connected to VDD

54

xiv

4.7 Static Noise Margin (SNM) in (a) retention mode (b)

read access mode for Independent Controllable (CG)

FinFET SRAM in flexi pass gate with back gate of pull

up connected to VDD scheme and conventional shorted

gate (SG) FinFET SRAM

54

xv

LIST OF ABBREVIATIONS

SRAM - Static Random Access Memory

MOSFET - Metal–Oxide–Semiconductor Field-Effect Transistor

SCE - Short Channel Effects

LDE - Layout Dependent Effects

GIDL - Gate Induced Drain Leakage

RDF - Random Dopant Fluctuations

CMC - Compact Modeling Council

NMOS - N-channel Metal-Oxide-Semiconductor

PMOS - P-channel Metal-Oxide-Semiconductor

W - Width

L - Length

SNM - Static Noise Margin

RNM - Read Noise Margin

WNM - Write Noise Margin

Vth - Threshold Voltage

IG - Independent Gate

SG - Shorted Gate

DG - Double Gate

RSNM - Read Static Noise Margin

PG - Pass Gate

PU - Pull Up

PD - Pull Down

AR - Aspect Ratio

PGFB - Pass Gate Feedback

PUWG - Pull Up Write Gating

BSIM - Berkeley Short-channel IGFET Model

PTM - Predictive Technology Model

xvi

PSP - Penn State-Philips

HICUM - High Current Model

BSIM-CMG - BSIM Common Multi-Gate

CMC - Compact Modeling Council

SINM - Static Current Noise Margin

WTI - Write Trip Current

CG - Controllable Gate

xvii

LIST OF APPENDICES

APPENDIX TITLE PAGE

A

Netlist- Drive and Off currents measurement by

Common Gate FinFET

62

B Netlist- IV curve by Common Gate FinFET 63

C Netlist- Butterfly curve by Common Gate FinFET 64

D Netlist-SNM measurement by Common Gate FinFET 65

E Netlist-WNM measurement by Common Gate

FinFET

66

F Netlist-Standby current of SRAM measurement by

Common Gate FinFET

67

G

Netlist- Drive and Off currents measurement by

Independent Controllable Gate FinFET

68

H Netlist- IV curve by Independent Controllable Gate

FinFET

69

I Netlist- Butterfly curve by Independent Controllable

Gate FinFET

70

J Netlist-SNM measurement by Independent

Controllable Gate FinFET

71

K Netlist-WNM measurement by Independent

Controllable Gate FinFET

72

L Netlist-Standby current of SRAM measurement by

Independent Controllable Gate FinFET

73

M Subckt Model for Independent Controllable Gate

FinFET

74

CHAPTER 1

INTRODUCTION

1.1 Background

Semiconductor memories can be categorized as volatile and non-volatile type.

The main difference between volatile memory and non-volatile memory is that volatile

type only retain the data when there is a power supply but non-volatile type can obtain

the stored information even though it is not powered. Volatile type is widely use as

primary storage in semiconductor design because it is faster, reliable and cost effective

compare to non-volatile type of memory. Static Random Access Memory (SRAM) is

classified as volatile memory.

In VLSI design especially multi core processor architectures, the demand of

on-chip caches for data sharing and storage efficiency is high and important across

parallel processing units [1]. The memory is designed in SRAM array thus it is

occupying a large fraction of chip area in many design nowadays. In the recent deep

submicron technology, both static and dynamic power dissipated is high. Static power

dissipation has concern because most of the time SRAM stays in standby mode and

compared to switching time. However dynamic power dissipation cannot be

neglected, it can be minimized with the scaling of voltage supply due to the square law

dependency of digital circuit active power. Thus it requires the scaling of threshold

voltage to maintain the performance but low threshold voltage introduces high leakage

currents such as sub threshold leakage current due to shorter channel length. In

2

addition, the scaling of supply voltage and threshold voltage will cause instability of

the SRAM cell for nanometer technology nodes [2].

SRAM design in planar MOSFET is challenging in deep submicron technology

due to short channel effect (SCE), layout dependent effect (LDE) and high leakage

current. The thinning of gate oxides result in higher gate leakage and causing gate

induced drain leakage (GIDL) [3]. FinFET device architecture is a promising candidate

to replace MOSFET in SRAM design for improved scalability. FinFET offer lower

gate leakage and sub-threshold leakage due to two electrically coupled gates and the

thin silicon body which suppress the short channel effects [2]. Moreover it enhances

gate controllability over the channel allowing thicker gate oxide which can reduce the

gate leakage significantly [2]. Moreover, FinFET has a lower process variation

compared to planar MOSFET as FinFET has minimum random dopant fluctuations

(RDF) due to the lightly body doping [4].

1.2 Problem Statement

Planar MOSFET scaling could not continue forever with Moore’s law, planar

structure in nanometer range introduced a lot of degradation effects and deep

submicron effect to the device such as short channel length effect. Aggressive scaling

in MOSFET result in higher leakage current and sensitive to process variation. FinFET

architecture is chosen as promising candidate due to its lower leakage current and

better scalability and higher Ion/Ioff ratio [5].

SRAM arrays greatly contribute to overall VLSI design thus power

consumption is always a concern for SRAM especially standby power as it is having

the behavior of short active periods but long idle periods [1]

3

In common gate FinFET, two gates are biased together to switch the FinFET

on or off. Thus this gives no flexibility control over the gate bias. However,

independent gate FinFET provides independent biasing on gate with one gate used to

switch the FinFET on and off and the other gate used to determine the threshold voltage

to minimize the leakage. The back gate operation mode offer the flexibility to tune the

static and dynamic performance characteristic. The only drawback of independent gate

finFET is having lower drive current strength compared to common gate FinFET.

It is clear that SRAM in planar bulk MOSFET is not a solution in future

anymore and FinFET is a good candidate to address its weakness. In addition, the

intention of this proposal is to combine both advantage of common gate and

independent gate FinFET into one model for SRAM design. This model is consists of

parallel common gate FinFET with source and drain connected but having two gates

to enable independent gate biasing. Each of the common gate FinFET is having half

dimension to compensate the area penalty imposed.

1.3 Objectives

The study of Static Random Access Memory (SRAM) circuitry by using

independent gate controllable technique on common gate FinFET. The objectives are:

To develop a simple subckt model in order to enable the behavior of

independent gate control

To explore the technique of independent gate controllable technique on SRAM

To evaluate the performance and standby leakage on proposed technique

benchmarking with conventional SRAM FinFET structure.

4

1.4 Research Scope

The scope of study includes the literature review of SRAM circuitry on FinFET

device and fundamental of SRAM operation is studied. Common gate FinFET device

has been commercialize widely and FinFET based SRAM design has becoming

popular practice, thus comparison with conventional common gate FinFET SRAM is

carried out.

In this research, independent controllable gate structure on common gate

FinFET is proposed. The proposed approach is to minimize the leakage current and

boost up the performance of SRAM. Performance of SRAM with this new technique

is evaluated and compared with conventional common gate FinFET SRAM.

The research also includes the investigation on the behaviour, advantages and

disadvantages on this technique. Various aspect like power, performance and area are

discussed.

59

REFERENCES

1. Jaksic, Z. and R. Canal. Enhancing 6T SRAM cell stability by back gate biasing

techniques for10nm SOI FinFETs under process and environmental variations.

in Mixed Design of Integrated Circuits and Systems (MIXDES), 2012

Proceedings of the 19th International Conference. 2012.

2. Zhiyu, L., S.A. Tawfik, and V. Kursun. An independent-gate FinFET SRAM

cell for high data stability and enhanced integration density. in SOC

Conference, 2007 IEEE International. 2007.

3. Chenming, H. Gate oxide scaling limits and projection. in Electron Devices

Meeting, 1996. IEDM '96., International. 1996.

4. OZA, S., FINFET BASED SRAM DESIGN FOR LOW POWER

APPLICATIONS. International Journal of Electrical, Electronics and Data

Communication, 2014. 2(3).

5. Sreyas Mohan, K.S.P., Jibu Varghese K, Stability Investigation of Sub-

Threshold Thin Body FinFET Dual Port SRAM Structures for Ultra Low

Power Applications. IOSR Journal of VLSI and Signal Processing (IOSR-

JVSP), 2014. Vol-4(Issue 4): p. 08-15.

6. Plummer, J.D. Silicon MOSFETs (conventional and non-traditional) at the

scaling limit. in Device Research Conference, 2000. Conference Digest. 58th

DRC. 2000.

7. Chauhan, Y., et al. BSIM 2014; Industry standard compact MOSFET models.

in Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of

the European. 2012.

8. Chauhan, Y.S., et al. BSIM 2014; Industry standard compact MOSFET models.

in ESSCIRC (ESSCIRC), 2012 Proceedings of the. 2012.

9. Packan, P., et al. High performance 32nm logic technology featuring

2^nd generation high-k + metal gate transistors. in Electron

Devices Meeting (IEDM), 2009 IEEE International. 2009.

10. Joshi, R., K. Keunwoo, and R. Kanj. FinFET SRAM Design. in VLSI Design,

2010. VLSID '10. 23rd International Conference on. 2010.

60

11. Sikarwar, V., S. Khandelwal, and S. Akashe, Analysis of Leakage Reduction

Techniques in Independent-Gate DG FinFET SRAM Cell. Chinese Journal of

Engineering, 2013. 2013: p. 8.

12. Tawfik, S.A., L. Zhiyu, and V. Kursun. Independent-gate and tied-gate

FinFET SRAM Circuits: Design guidelines for reduced area and enhanced

stability. in Microelectronics, 2007. ICM 2007. Internatonal Conference on.

2007.

13. Bhattacharya, D. and N.K. Jha, FinFETs: From Devices to Architectures.

Advances in Electronics, 2014. 2014: p. 21.

14. Paydavosi, N., et al., BSIM2014;SPICE Models Enable FinFET and UTB IC

Designs. Access, IEEE, 2013. 1: p. 201-215.

15. Fu-Liang, Y., et al. A 65nm node strained SOI technology with slim spacer. in

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE

International. 2003.

16. Carlson, A., et al., SRAM Read/Write Margin Enhancements Using FinFETs.

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2010.

18(6): p. 887-900.

17. Carlson, A., et al. FinFET SRAM with Enhanced Read / Write Margins. in

International SOI Conference, 2006 IEEE. 2006.

18. Young Bok, K., K. Yong-Bin, and F. Lombardi. New SRAM Cell Design for

Low Power and High Reliability Using 32nm Independent Gate FinFET

Technology. in Design and Test of Nano Devices, Circuits and Systems, 2008

IEEE International Workshop on. 2008.

19. Zhang, K., et al. A 3-GHz 70MB SRAM in 65nm CMOS technology with

integrated column-based dynamic power supply. in Solid-State Circuits

Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE

International. 2005.

20. Joshi, R.V., et al. A High-Performance, Low Leakage, and Stable SRAM Row-

Based Back-Gate Biasing Scheme in FinFET Technology. in VLSI Design,

2007. Held jointly with 6th International Conference on Embedded Systems.,

20th International Conference on. 2007.

21. Rahaman, M. and R. Mahapatra. Design of a 32nm independent gate FinFET

based SRAM cell with improved noise margin for low power application. in

Electronics and Communication Systems (ICECS), 2014 International

Conference on. 2014.

61

22. Sourabh Khandelwal, J.D., Sriramkumar V., Navid Paydavosi, Darsen Lu,

Chung-Hsun Lin,Mohan Dunga, Shijing Yao, Tanvir Morshed, Ali Niknejad,

and Chenming Hu, Multi-Gate MOSFET Compact Model, BSIM, Editor. 2014.

23. Ohbayashi, S., et al., A 65-nm SoC Embedded 6T-SRAM Designed for

Manufacturability With Read and Write Operation Stabilizing Circuits. Solid-

State Circuits, IEEE Journal of, 2007. 42(4): p. 820-829.

24. Zheng, G., et al. FinFET-based SRAM design. in Low Power Electronics and

Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium

on. 2005.

25. Iwai, H., Roadmap for 22nm and beyond (Invited Paper). Microelectronic

Engineering, 2009. 86(7–9): p. 1520-1528.

26. Arandilla, C.D.C., A.B. Alvarez, and C.R.K. Roque. Static Noise Margin of 6T

SRAM Cell in 90-nm CMOS. in Computer Modelling and Simulation (UKSim),

2011 UkSim 13th International Conference on. 2011.

27. Ajay Gadhe, U.S., Read stability and Write ability analysis of different SRAM

cell International Journal of Engineering Research and Applications 2013.

3(1): p. 1073-1078.

28. Zheng, G., et al., Large-Scale SRAM Variability Characterization in 45 nm

CMOS. Solid-State Circuits, IEEE Journal of, 2009. 44(11): p. 3174-3192.

29. Torrens, G., et al., Design Hardening of Nanometer SRAMs Through

Transistor Width Modulation and Multi-Vt Combination. Circuits and Systems

II: Express Briefs, IEEE Transactions on, 2010. 57(4): p. 280-284.

30. Hu, V.P.H., et al. Evaluation of Read- and Write-Assist circuits for GeOI

FinFET 6T SRAM cells. in Circuits and Systems (ISCAS), 2014 IEEE

International Symposium on. 2014.