ece 551 digital design and synthesis lecture 2 structural verilog wrap-up timing controls for...

ECE 551Digital Design And

Synthesis

Lecture 2

Structural Verilog Wrap-UpTiming Controls for Simulation

Testbenches Introduction to RTL Verilog

Overview Module Port List: Revisited Simulation and Testbenches

Simulation Overview Timing Controls and Delay Testbenches

Introduction to RTL Verilog(Continuous Assignments)

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Module Port List Two basic ways to declare the ports of a

module

Note that each port after a vector declaration will be a vector; need to use , input port_x, to have scalar ports again.

module xor_8bit(out, a, b); output [7:0] out; input [7:0] a, b; …endmodule

module xor_8bit(output [7:0] out, input [7:0] a, b); …endmodule

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Analog Circuit Simulation Divide “time” into slices Update information in whole circuit at each

slice Used by SPICE

Allows detailed modeling of current and voltage

Computationally intensive and slow

Don’t need this level of detail for most digital logic simulation

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Digital Simulation Could update every signal on input change

Could update just the full path on input change

Don’t even need to do that much work!

00110

1

1

11

00010

0

1

11

1 0

00110

1

1

11

00010

01

1

1 01

11

1 1

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Event-Driven Simulation When an input to the simulating circuit

changes, put it on a “changed” list Loop while the “changed” list isn’t empty:

Remove a signal from the “changed” list For each sink of the signal

Recompute its new output(s) For any output(s) that have changed value, add that

signal to the “changed” list

When the “changed” list is empty, keep simulation results until next input change

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Simulation Update only if changed

Some circuits are very large Updating every signal => very slow simulation Event-driven simulation is much faster!

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1

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1 01

1 1

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Simulation of Verilog Need to verify your design

“Unit Under Test” (UUT)

Use a “testbench”! Special Verilog module with no ports Generates or routes inputs to the UUT Outputs information about the results

Stim

ulu

s

UUT

Inputs InputsOutputs Outputs

UUTOR

Testbench Testbench

(Response)(Response)

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Simulation Example

adder4b

a[3:0]

b[3:0]sum[3:0]

c_out

4

4

c_in

4

module adder4b (sum, c_out, a, b, c_in);input [3:0] a, b;input c_in;output [3:0] sum;output c_out;assign {c_out, sum} = a + b + c_in;

endmodule

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Simulation Example

Testbenches frequently namedt_<UUT name>

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adder4b(UUT)

a[3:0]

b[3:0]sum[3:0]

c_out

4

4

c_in

4

t_adder4b

Example

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`timescale 1ns /100ps // time_unit/time_precisionmodule t_adder4b; reg[8:0] stim; // inputs to UUT are regs

wire[3:0] S; // outputs of UUT are wires wire C_out;

// instantiate UUTadder4b(S, C_out, stim[8:5], stim[4:1], stim[0]);

// stimulus generationinitial begin

stim = 9'b000000000; // at 0 ns #10 stim = 9'b111100001; // at 10 ns #10 stim = 9'b000011111; // at 20 ns #10 stim = 9'b111100010; // at 30 ns #10 stim = 9'b000111110; // at 40 ns #10 $stop; // at 50 ns – stops

simulationend

endmodule

all inputs grouped into single vector (not required)

see “response” to each of these input vectors

UUT

Behav.Verilog:“do this once”

timing control for simulation

not an apostrophe!



Verilog Shortcuts Concatenating Vectors Arrays of Instances


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Timing Controls For Simulation Can put “delays” in a Verilog design

Gates, wires, even behavioral statements!

SIMULATION Used to approximate “real” operation while

simulating Used to control testbench

SYNTHESIS Synthesis tool IGNORES these timing controls

Cannot tell a gate to wait 1.5 nanoseconds! Delay is a result of physical properties!

The only timing that can be (easily) controlled is on a clock-cycle basis Can tell synthesizer to attempt to meet cycle-time

restriction 15

No Delay vs. Unit Delay When no timing controls specified: no delay

Unrealistic – even electrons take time to move OUT is updated at same time A and/or B change:

and(OUT, A, B)

Unit delay often used Not accurate either, but closer… “Depth” of circuit does affect speed! Easier to see how changes propagate through

circuit OUT is updated 1 “unit” after A and/or B change:

and #1 A0(OUT, A, B);

#0 delay – Don’t use this.16

Unit Delay Example

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A

BC

Z

T A B C Y ZT A B C Y Z

0123456789101112131415

012345678910111213141516

0 0 0 0 00 0 1 0 00 1 0 0 00 1 1 1 11 0 0 0 11 0 1 0 11 1 0 0 11 1 1 1 10 0 0 0 00 0 1 0 00 1 0 0 00 1 1 1 11 0 0 0 11 0 1 0 11 1 0 0 11 1 1 0 1

0 1 0 x x0 1 0 0 x0 1 0 0 00 1 1 0 00 1 1 1 00 1 1 1 11 0 0 1 11 0 0 0 11 1 1 0 11 1 1 1 11 0 0 1 11 0 0 0 10 1 0 0 10 1 0 0 00 1 1 0 00 1 1 1 00 1 1 1 1

Y No DelayUnit Delay

No Delay:Y and Z change at same “time” as A, B, and C!

Unit Delay:Y changes 1 unit after B, C

Unit Delay:Z changes 1 unit after A, Y

Types Of Delays Inertial Delay (Gates)

Suppresses pulses shorter than delay amount In reality, gates need to have inputs held a certain

time before output is accurate This models that behavior

Transport Delay (Nets) “Time of flight” from source to sink Short pulses transmitted

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Delay Examples wire #5 net_1; // 5 unit transport delay

and #4 (z_out, x_in, y_in); // 4 unit inertial delay assign #3 z_out = a & b; // 3 unit inertial delay

wire #2 z_out; // 2 unit transport delay

and #3 (z_out, x_in, y_in); // 3 for gate, 2 for wire

wire #3 c; // 3 unit transport delay

assign #5 c = a & b; // 5 for assign, 3 for wire

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Delays In Testbenches Most common use in class

A single testbench will test many possibilities Want to examine each case separately Spread them out over “time”

Use to generate a clock signal Example later in lecture

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Testbench Basics Instantiate the unit being tested (UUT) Provide input to that unit

Usually a number of different input combinations!

Watch the “results” (outputs of UUT) Can watch ModelSim Wave window… Can print out information to the screen or to a file

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Print Test Information A number of system calls to output info

$monitor Give a list of nets and variables to monitor Output the given values every time a one of them

changes

$display, $strobe Output a value at a specific time during simulation

Can use formatting strings with these commands

Also have system calls that write to files

Only have meaning in simulation System calls are ignored in synthesis

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Output String Formatting Formatting string

%h, %H hex %d, %D decimal %o, %O octal %b, %B binary %t time

$monitor(“%t: %b %h %h %h %b\n”,$time, c_out, sum, a, b, c_in);

Can get more details from Verilog standard

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Output Example

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wire[3:0] S; // outputs of UUT are wires wire C4;

// instantiate UUTadder4b(S, C4, stim[8:5], stim[4:1], stim[0]);// monitor statementinitial $monitor($time, C4, S, stim[8:5], stim[4:1], stim[0]);// stimulus generationinitial begin


simulationend

endmodule

All values will run together; easier to read with formatting string

Output Example

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wire[3:0] S; // outputs of UUT are wires wire C4;

// instantiate UUTadder4b(S, C4, stim[8:5], stim[4:1], stim[0]);// monitor statementinitial $monitor(“%t %b %d %d %d %b”,

$time, C4, S, stim[8:5], stim[4:1], stim[0]);// stimulus generationinitial begin


simulationend

endmodule

Formatted with spacesbetween values, vectorsshown as decimal

Exhaustive Testing For combinational designs with few inputs Test ALL combinations of inputs to verify

output Could enumerate all test vectors, but don’t…

Generate them using a “for” loop!reg [4:0] x;initial begin

for (x = 0; x < 16; x = x + 1) #5 // need a delay here!

end

Need to use “reg” type for x. Why? It’s a variable assigned a value in a behavioral

block

What would happen without the delay?27

Why Loop Vector Has Extra Bit Want to test all vectors 0000 to 1111

reg [3:0] x;initial begin

for (x = 0; x < 16; x = x + 1) #5 // need a delay here!

end If x is 4 bits, it only gets up to 1111 => 15

1100 => 1101 => 1110 => 1111 => 0000 => 0001

x is never >= 16… so loop goes forever!

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Exhaustive Example: UUT

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module Comp_4_str(A_gt_B, A_lt_B, A_eq_B, A, B);

output A_gt_B, A_lt_B, A_eq_B;input [3:0] A, B;

// Code to compare A to B and set outputs// A_gt_B, A_lt_B, A_eq_B accordingly

endmodule

Exhaustive Example: Testbench

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module t_Comp_4_str();wire A_gt_B, A_lt_B, A_eq_B;reg [4:0] A, B; // sized to prevent loop wrap

aroundwire [3:0] A_bus, B_bus;assign A_stim = A[3:0]; // display only 4 bit valuesassign B_stim = B[3:0];

Comp_4_str M1 (A_gt_B, A_lt_B, A_eq_B, A_stim, B_stim); // UUT

initial $monitor(“%t A: %h B: %h AgtB: %b AltB: %b AeqB: %b”, $time, A_stim, B_stim, A_gt_B, A_lt_B, A_eq_B);

initial #2000 $finish; // end simulation, quit program

initial begin#5 for (A = 0; A < 16; A = A + 1) begin // exhaustive test of valid inputs

for (B = 0; B < 16; B = B + 1) begin #5; // may want to test x’s and z’s

end // first for end // second forend // initialendmodule

note multiple initial blocks

Generating Clocks Hard way:

initial begin #5 clk = 0; #5 clk = 1; #5 clk = 0; … (repeat hundreds of times)end

Better way:initial begin clk = 0; forever #5 clk = ~clk;end

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FSM Testing Response to input vector depends on state For each state:

Check all transitions For Moore, check output at each state For Mealy, check output for each transition This includes any transitions back to same state!

Can be time consuming to traverse FSM repeatedly…

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Example : Gray Code Counter Write a testbench to test a 3-bit gray code

counter.

module gray_counter(out, clk, rst);

In this module, rst is synchronous It is an input to the combinational next state logic

Initially reset the counter and then test all states, but do not test reset in each state

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Solution : Gray Code Counter – Test1

module t1_gray_counter();wire [2:0] out;reg clk, rst;

gray_counter GC(out, clk, rst); // UUT

initial $monitor(“%t out: %b rst: %b ”,$time, out, rst); // clk not

displayed initial #100 $stop; // end simulation

initial begin clk = 0; forever #5 clk = ~clk; // What is the clock period?

end initial begin

rst = 1; #10 rst = 0; // When does rst change relative to clock?

end // initialendmodule

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Be careful not to change your inputs on the active clock edge of your flip-flops!

Simulation: Gray Code Counter – Test1 # 0 out: xxx rst: 1 // reset system# 5 out: 000 rst: 1 // first positive edge# 10 out: 000 rst: 0 // release reset# 15 out: 001 rst: 0 // next positive edge# 25 out: 011 rst: 0# 35 out: 010 rst: 0# 45 out: 110 rst: 0# 55 out: 111 rst: 0# 65 out: 101 rst: 0# 75 out: 100 rst: 0# 85 out: 000 rst: 0# 95 out: 001 rst: 0

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Force/Release In Testbenches Allows you to “override” value FOR

SIMULATION Does NOT apply to hardware

Can’t tell the synthesis tools “when you get here, make this value become 3’d5”

Synthesizer won’t allow force…release How does this help testing?

Pinpoint bug by controlling other signals Can use with FSMs to override state

Force to a state Test all edges/outputs for that state Force the next state to be tested, and repeat

Can also use simulator GUI to force values36

Force/Release Example

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assign y = a & b;assign z = y | c; initial begin a = 0; b = 0; c = 0; #5 a = 0; b = 1; c = 0; #5 force y = 1; #5 b = 0; #5 release y; #5 $stop;end

t a b c y z0 0 0 0 0 05 0 1 0 0 010 0 1 0 1 115 0 0 0 1 120 0 0 0 0 0

Example : Gray Code Counter – Test2 Write a testbench to exhaustively test a 3-bit

gray code counter.

module gray_counter(out, clk, rst);

Initially reset the counter and then test all states, then test reset in each state.

Remember that in this example, rst is a synchronous reset.

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Example : Gray Code Counter – Test2module t2_gray_counter();

wire [2:0] out;reg clk, rst;

gray_counter GC(out, clk, rst); // UUT

initial $monitor(“%t out: %b rst: %b ”, $time, out, rst); initial #300 $finish;initial begin clk = 0; forever #5 clk = ~clk; end initial begin rst = 1; #10 rst = 0;

#90 rst = 1; force GC.ns = 3'b001; #10 release GC.ns;

#10 force GC.ns = 3'b011; #10 release GC.ns;

#10 force GC.ns = 3'b010; #10 release GC.ns; // In SIMULATION, can access internal signals of submodules // This violation of our “black box” model is only used in testbenches

… endendmodule 39

Simulation: Gray Code Counter – Test2

# 0 out: xxx rst: 1# 5 out: 000 rst: 1# 10 out: 000 rst: 0# 15 out: 001 rst: 0# 25 out: 011 rst: 0# 35 out: 010 rst: 0# 45 out: 110 rst: 0# 55 out: 111 rst: 0# 65 out: 101 rst: 0# 75 out: 100 rst: 0# 85 out: 000 rst: 0# 95 out: 001 rst: 0

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# 100 out: 001 rst: 1

# 105 out: 000 rst: 1

// at #115 out = 000# 125 out: 001 rst:

1# 135 out: 000 rst:

1# 145 out: 011 rst:

1# 155 out: 000 rst:

1# 165 out: 010 rst:

1# 175 out: 000 rst:

1# 185 out: 110 rst:

1# 195 out: 000 rst:

1# 205 out: 111 rst:

1

# 215 out: 000 rst: 1

# 225 out: 101 rst: 1

# 235 out: 000 rst: 1

# 245 out: 100 rst: 1

# 255 out: 000 rst: 1

Review Questions What are the two ways to declare module

ports? What is the difference between transport and

inertial delay? When is each used? What does it mean to exhaustively test a

design? Why are force/release statements useful? How do you generate a clock with a period of

16 time units?

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RTL Verilog Higher-level of description than structural

Don’t always need to specify each individual gate Can take advantage of operators

Less abstract than behavioral Doesn’t look as much like software Less complex timing control makes it easier to

understand Lacks some power in describing sequential logic

Very easy to synthesize Supported by even primitive synthesizers

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Continuous Assignment Implies structural hardware

assign <LHS> = <RHS expression>; Example

wire out, a; //LHS must be a netreg b; //RHS is not restrictedassign out = a & b;

If RHS result changes, LHS updated with new value Automatically updates (“continuous”) Just like the output of a hardware circuit!

Used to model combinational logic44

Full Adder: RTL Note use of operators

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module fadd_rtl (A, B, CI, S, CO) ;

input A, B, CI ;output S, CO ;

// use continuous assignmentsassign S = A ^ B ^ CI;assign C0 = (A & B) | (A & CI) | (B & CI);

endmodule

S

CO

A

B

CI

fa_rtl

Continuous Assignment LHS Can assign values to:

Scalar nets Vector nets Single bits of vector nets Part-selects of vector nets Concatenation of any of the above

Examples:assign out[7:4] = a[3:0] | b[7:4];assign val[3] = c & d;assign {a, b} = stimulus[15:0];

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Continuous Assignment RHS Operators:

Arithmetic, Logical, Relational, Equality, Bitwise, Reduction, Shift, Concatenation, Replication, Conditional

Same set as used in Behavioral Verilog

Can also be a pass-through!assign a = stimulus[16:9];assign b = stimulus[8:1];assign cin = stimulus[0];

Note: “aliasing” is only in one direction Cannot give ‘a’ a new value elsewhere to set

stimulus[16:9]!

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Example: adder4b

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adder4b

a[3:0]

b[3:0]sum[3:0]

c_out

4

4

c_in

4

module adder4b (sum, c_out, a, b, c_in);input [3:0] a, b;input c_in;output [3:0] sum;output c_out;assign {c_out, sum} = a + b + c_in;

endmodule

Can Often Replace Primitive Arrays Module/Instance Array:

module array_of_xor (output [3:0] y, input [3:0] a, b);

xor Xarray [3:0] (y, a, b); // instantiates 4 xor gates endmodule

Continuous Assignmentmodule xor_4bit (output [3:0] y, input [3:0] a, b);

assign y = a ^ b; // instantiates 4 xor gates endmodule

Can’t replace Flip Flops No edge-triggering in continuous assignments! Behavioral Verilog usually needed to create FFs.

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Operators: Arithmetic Much easier than structural!

* multiply ** exponent/ divide % modulus+ add - subtract

Some of these may not synthesize! ( /, **, % )

Also have unary operators +/- (pos/neg) Understand bitwidth of operations!

Can affect sign of result Is affected by bitwidth of BOTH sides

wire [5:0] SUM;assign SUM = a[3:0] + b[4:0]; 50

Example: Unsigned MAC Unit

Design a multiply-accumulate (MAC) unit that computesZ[7:0] = A[3:0]*B[3:0] + C[7:0]

It sets overflow to one if the result cannot be represented using 8 bits.

module mac(output Z [7:0], output overflow, input [3:0] A, B, input [7:0] C);

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Solution: Unsigned MAC Unit

module mac(output Z [7:0], output overflow, input [3:0] A, B, input [7:0] C); wire [8:0] P; assign P = A*B + C; assign Z = P[7:0]; assign overflow = P[8]; endmodule

Alternative method:

module mac(output Z [7:0], output overflow, input [3:0] A, B, input [7:0] C); assign {overflow, Z} = A*B + C;endmodule

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Operators Shift (<<, >>) Relational (<, >, <=, >=) Equality (==, !=, ===, !==)

===, !== test x’s, z’s! ONLY USE FOR SIMULATION!

Logical Operators (&&, ||, !) Build clause for if statement or conditional

expression Returns single bit values

Bitwise Operators (&, |, ^, ~) Applies bit-by-bit!

Watch ~ vs !, | vs. ||, and & vs. &&53

Example: ComparatorComplete the following module using three continuous assignment statements.

module compare_4bit(output A_lt_B, A_gt_B, A_eq_B, input [3:0] A, B);

endmodule

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Operators Reduction (&, |, ^)

Unary!&(4’b0111), |(3’b010), ^(12’h502)

Parentheses ( () ) Use to make calculations clear!

Concatenation ( {} ) Assembles vectors

Replication ( {{}} )// a is a 4-bit vector with the value of b// as the value of each bit

wire [3:0] a = {4{b}};// same as a = {b,b,b,b}

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Operators: Conditional Can do an “if else” assignment in continuous assign

<clause> ? <T exp> : <F exp> Examples:

assign mux_out = sel ? in1 : in0;assign and2 = a ? b : 0;assign xor2 = in1 ? ~in2 : in2;assign triVal = sel ? in : 1’bz;

Can nest the conditionals!assign trimux = trisel ? (muxsel ? a : b) : 1’bz;

Frequently used for tristate, muxing Also used for complex combinational logic USE PARENTHESES WHEN NESTING!!!

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Review Questions Create 6 parallel AND gates with a delay of 4

time units, inputs X[5:0] and Y[7:2], and outputs Z[1:6] …using instance arrays. Call the array AND_array …using a single continuous assignment statement

What do each of the following evaluate to?(assume values are unsigned)

4’b1000 * 4’b0100 4’b1101 & 4’b1001(^ 4’b1011) + 4’b0011 4’b1101 && 4’b1001

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ece 551 digital design and synthesis lecture 2 structural verilog wrap-up timing controls for...

Documents

simulation of verilog

simulation update

digital simulation

revisited simulation

simulation results

adder4b slide

simulation example testbenches

input port