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Efficient Migration of Verilog Testbenches to 'UVM' Keeping the Funct http://www.slideshare.net/DVClub/efficient-migration-of-verilog-testb...

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Efficient Migration of Verilog Testbenches to'UVM' Keeping the Functionality Intact

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1. TMEfficient Migration ofEfficient Migration of VerilogVerilogTestbenchesTestbenches toUVM keepingto UVM keepingthe functionality intact:the functionality intact:Dos andDos andDontsDontsMehul Kumar & Nitin GoelDate 22 Dec 20112. Agenda Need for Migration Conversion of Sequential, Combinatorial and Continousassignments Conversion of forces & releasesConversion of Inout portsConversion of UI fromAPIsConversion of monitor eventsTM 2Conversion of monitor eventsEstablishing coherencybetween converted code with verilog counterpartConclusion3. Why is this migration needed? Increase in design complexity More than 100 IPs per SoCReuse of legacy IP Avoid hybrid testbenches Newer components in the latest methodologyTM 3Newer components in the latest methodology Environment bring up Complex to scale Maintain

4. Verilog Testbench and its equivalent UVMTestbenchTM 45. Converting always sequential logic, alwayscombinatorial logic and Continuous assignmentsTM5 Combinatorial and sequential blocks are converted to task Sequential block non-blockingassignments are changed to blocking Continuous assignments mapped to functions returning

values.A simple script is utilized to perform the conversionnaming of tasks could be edited lateron.6. How the Verilog event behavior is compensated whenall assignment types have been transformedtoblocking?Events executed in order: Active events Inactive events (#0 delayassignments) NonBlocking assignments Monitor eventsIn one time step all events areTM 6handled by Simulator7. apb_interface :apb_master class:Dynamics of SystemVerilog code in terms of theevents andfunctional mapping of Verilog behaviorTM 7Two events are declared inside the APB interfacemaster_nba_evt (non-blocking event) master_act_evt (Active event).Active event blocks theexecution of the following: Waiting for posedge of clock Generation of Non-Blocking event.Amain task is used to synchronize code flow for APB master classNote the "->>" being differentfrom active eventtrigger "->"8. Event synchronization between code execution and regionexecutionTM 8Step 1: Active Eventexecution of line " ->apb_if.master_act_evnt; Generate trigger master_nba_evntAll thecombinatorial converted tasks executedThe code jumps to the wait of the sequential blocktrigger.#Step2: NBA event "master_nba_evt" is triggered in the NBA region"assign_current_state"task is executedBlocking assignment of "present_state" variable is scheduled for #Step3.#Step3:Blocking assignment for present_state is done . Repeat #Step1.Verilog code transitions infollowing manner:#Step1: Change in wire triggers always block and next_state is assigned.#Step2:NBA assignment of present_state is done#Step3: Repeat #Step1

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9. Timing Diagram to explain Verilog and System Verilogcode flowTM 9In Verilog at simulatortimestep 4 pending_transaction wire has a change in value Triggers the always block to decide thenext_state handled in active region of timestep5. Assigned to present_state variable in NBAregion of timestep6 falling after the posedge of PCLK. In SystemVerilog act_evt gets triggers inactive region of timestep5 before the posedge of the PCLK. next_state assignment is done in thesame timestep in active region nba_evt gets triggered in the NBA region of timestep6 falling afterthe posedge of PCLK present_state assignment is scheduled to be done in active region of timestep7. At timestep7 both code shows value of next_state deposited on present_state variable10. Conversion of Force & ReleasesTM 10 A mux based logic is implemented inside the interfaceoutput signal a_o A mux select signal force_a_at_x force value at the wire a when the select is 1else actual a_o valueFunctionality is similar to Verilog11. Conversion of Inout PortsTM 11A Verilog inout pin bifurcated : output_enable outputinputUVM driver class implements these three ports instead of one inout pin.When the output isnot selected a highz is driven12. Conversion of User Interface from APIsAPI of Verilog driver addr, data , strb and writeasargumentsAPI removedSequence item class is utilized Testcase only needs to randomize onesequenceitem instead of calling separate APIs for eachfunctionality to be executed by the driverTM12functionality to be executed by the driver13. Monitor :: Event Base -> Object Base reporting viaAnalysis PortsTM 13 event data type is

triggered on occurrence of a particular condition. UVM monitor class an analysis port of type ofapb_transaction is created write method of the analysis port is called to publish the eventinformation. All events are stored inside TLM fifo to be processed by subscriber (scoreboard).Conversion mapping is direct triggering event modified to a write method call14. How to establish that the ported UVM testbench isconforming with Verilog testbench?No LECkind of tool to check the conformity between two differentforms of same testbench. A Verilogproven assertion/protocol checker plugged in UVM convertedtestbench Testcases were run toachieve 100% DUT code coverageTM 1415. Benefits of the approach Cycle time reduction. a reduction in cycle time of 30%-50%(approx.),UVM provides additional benefits Layered testbench enabling reuse RandomizationCoverage driven Verification.UVM RAL provides the automated register check testcasesTM 1516. Some Facts from a Typical IP Testbench environmentportingS.No. Data Points VerilogTestbench UVM Testbench1. Number Of Tests 550 352 Randomization No Yes3 Reusability ofStimulus No YesTM 163 Reusability of Stimulus No Yes4 Scalability of Testbench NoYes5Approximate Lines Of Codeper testcase>225

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