Download - EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrow’s Technology Today
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EZ-COURSEWAREEZ-COURSEWARE
State-of-the-Art Teaching ToolsState-of-the-Art Teaching Tools
From AMSFrom AMS
Teaching Tomorrow’s Teaching Tomorrow’s Technology TodayTechnology Today
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80486 and Pentium
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80486 Microprocessor Family
• 80486 Microprocessor– Introduced in 1989– High Integration
• On-chip 8K Code and Data cache• Floating Point Unit• Paged, Virtual Memory Management
– 168-pin PGA package– Multiprocessor Support
• Multiprocessor Instructions• Cache Consistency Protocols
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Internal Architecture of the 80486
• Complex Reduced-Instruction-Set Computer (CRISC)• RISC integer core
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Real-Mode Software Model
• the same as that shown for the 80386
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Protected-Mode Software Architecture
AC: Alignment-Check flag When this bit is set, an alignment check is performed during all memory accesses at privilege level 3. If an unaligned access takes place, exception 17 occurs.
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Control Registers• AM : alignment mask -- If this is switched to 0, the alignment check is
masked out.• NE : Numeric Error• CD : cache disable• NW : not write-through• WP : write protect
• PCD : page-level cache disable• PWT : page-level write transparent
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System-Control Instruction Set
+ a flush bus cycle
+ a write-back bus cycle
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Page Directory and Page Table Entries
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Hardware Architecture of the 80486
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Signal Interfaces
Pseudo-lock
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On-Chip Cache of the 80486SX
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Pentium Processor• Pentium Processor
– 32-bit Microprocessor• 32-bit addressing• 64-bit Data Bus
– Superscalar architecture• Two pipelined integer units• Capable of under one clock per instruction• Pipelined Floating Point Unit
– Separate Code and Data Caches• 8K Code, 8K Write Back Data• 2-way 32-byte line size• MESI cache consistency protocol
– Advance Design Features• Branch Prediction
– 237-pin PGA
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Internal Architecture of the Pentium Processors
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Pentium Processor• Pipeline and Instruction Flow
– 5 stage pipelinePF : prefetchD1 : Instruction decodeD2 : Address GenerationEX : Execute -ALU and Cache AccessWB : Write Back
Intel 486 Pentium I1 I3I2 I4
I1 I3I2 I4
I1 I3I2 I4
I1 I3I2 I4
I1 I3I2 I4
PF
D1
D2
EX
WB
I1
I2
I5
I6
I7
I8
I3
I4
I1
I2
I5
I6
I7
I8
I3
I4
I1
I2
I5
I6
I7
I8
I3
I4
I1
I2
I5
I6
I7
I8
I3
I4
I1
I2
I5
I6
I7
I8
I3
I4
PF
D1
D2
EX
WB
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Pentium Processor– “U”, “V” pipes - “pairing”
• U : any instruction• V : ‘simple instructions” as defined in the ‘Pairing” rules
PF : instructions on chip cache or memory -> prefetch buffers prefetch buffers - two independent pairs of line size(32
bytes)D1 : two parallel decodersD2 : address generation for operand fetch
EX : ALU operations and data cache accessWB : modify processor state ; complete execution
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Branch Prediction• Branch Prediction
– Branch Target Buffer– The processor accesses the BTB with the address of the instruction in
the D1 stageexample)inner_loop :
mov byte ptr flag[edx], al PF D1 D2 EX WB
add edx, ecx PF D1 D2 EX WB cmp edx, FALSE PF D1 D2 EX WB
jle inner_loop PF
– 486 : 6 clocks Pentium : 2 clocks with branch prediction
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EFLAGS
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Control Registers of the Pentium Processor
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Enhancements to the Instruction Set
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Hardware Architecture
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Memory Subsystem
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Organization of the DRAM Array
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RAS/CAS address MUX
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Data Bus Transceiver Circuitry
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On-Chip Cache
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On-chip cache operating mode
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