experimental characterization of power vdmos transistors in commutation and a derived model for...

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 4, NO. 3, JULY 1989 37 1

Experimental Characterization of Power VDMOS Transistors in Commutation and a Derived

Model for Computer-Aided Design M. INES CASTRO SIMAS, MEMBER, IEEE, MOISES SIMOES PIEDADE,

AND J. COSTA FREIRE, MEMBER, IEEE

Abstract-MOS transistors have been developed in order to achieve high power levels. The structure of these devices is somewhat different from that of the classical low power MOSFET, and as a consequence the classical models are not suited for the new power devices. An experimental method is presented for the characterization of power MOS transistors in commutation that does not need any technological parameter. The method is based on the time domain analysis of the performance in commutation of the MOS transistor when constant currents are injected into Its terminals. The analysis of the time domain waveforms and the knowledge of the internal structure of the MOS devices are sufficient for the evaluation of the transistor capacitances. It is then possible to introduce a simple large-signal model for power MOSFET’s that is particularly suited to the analysis of circuits using the MOS transistor in commutation (e.g., switching power converters or high efficiency power amplifiers). We also present the model implementation in the Spice 2 program. The comparison between the results obtained experimentally with several circuits and by computer simulation confirms the accuracy of the proposed method.

INTRODUCTION ETAL-oxide-semiconductor (MOS) devices have M been widely used for over two decades in low power

applications, especially in large-scale integration (LSI) and very large-scale integration (VLSI) circuits. In the last few years MOS transistors rated for high power levels have been developed. These devices present several ad- vantages over bipolar transistors in power circuits [ 11, [2].

In order to increase current densities, MOS power transistors are designed as vertical current flow devices. A high resistivity epitaxial layer (epidrain) is introduced in series with the drain region of the transistor in order to increase the drain-source breakdown voltage.

The ever increasing switching frequency of semiconductor devices in new power processing topologies needs a good characterization of the power MOS transistor, namely the accurate evaluation of its internal capacitances. In a low frequency switching mode power circuit, the effects of the transistor switching times and internal capacitances are negligible. In this case the transistor can be modeled as a resistor in the “on-state” and as an open

Manuscript received September 1988; revised May 1989. This paper was partially presented at the IEEE 1988 Power Electronics Specialists Conference, Kyoto, Japan.

The authors are with the Electrical and Computer Engineering Depart- ment, Technical University of Lisbon, 1096 Lisbon, Portugal.

IEEE Log Number 8930382.

circuit in the “off-state,” and the transitions between those two states can be taken as instantaneous. In a high frequency switching mode power circuit the switching times and the internal capacitances are very important, because they limit the power efficiency and the maximum frequency of operation of the circuit [3], [4].

The accurate characterization of MOSFET internal capacitances is of fundamental importance in the design of the new high frequency resonant or quasi-resonant power converters because these capacitances determine the tun- ing and the timing of these circuits.

Since manufacturers do not give all the necessary MOS- FET characteristics, high frequency power designers need to develop meaningful measurement methods in order to model power transistors.

Accurate models for low power MOS devices are widely referenced in the literature [SI. However these models are unsuitable for power MOS transistors. Other modeling techniques recently proposed [6] are based on a very accurate physical model of the transistor that needs technological parameter values that are not usually available to circuit designers.

This paper presents an experimental method for the characterization of power MOS transistors, with special emphasis on the internal capacitances [7]. The method is based on device operation under gate and drain constant current conditions. These conditions have been suggested by a previous study of transistor physical behavior in the different regions of operation (off, triode, and saturation). The method leads to a simplified model, the parameters of which are easly obtained by external measurements only. The model was implemented in the Spice program, by means of auxiliary circuits [8]. The achieved model accurately represents the switching performance of MOS- FET devices; this is confirmed by good agreement between computer simulation and experimental results, not only for constant current driving and load conditions, used in the modeling technique, but also for voltage driving and loading with resistive or inductive circuits. This is mainly due to the strong connection between the experimental method of characterization proposed and MOS- FET physical behavior.

In order to show the wide applicability of the model we

0885-8993/89/0700-037 1$01 .OO 0 1989 IEEE

312 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 4, NO. 3, JULY 1989

also present a comparison of experimental and simulation results obtained with the Spice program for a quasi-resonant high frequency converter using a MOSFET that was characterized and modeled by the proposed method.

THE VDMOS TRANSISTOR CELL The structure of a VDMOS transistor cell, and its

equivalent circuit are shown in Fig. 1. Since the nonlin- earities of the internal capacitances have an important effect on the commutation behavior of power MOS transistors, it is desirable to develop a model that emphasizes these effects. We will start by presenting the physical meaning of the intemal capacitances in order to define their dependence on the circuit voltages.

The gate-source, gate-epidrain and gate-substrate over- lap capacitances are represented by constant values CGso, CcDo, and CGBo, respectively, which are electrostatically defined. The capacitance of the reverse-biased pn- junc- tion, substrate bulk-epidrain, is represented by Cds.' This capacitance is a highly nonlinear function of the substrate bulk-epidrain voltage vBE. When that junction is forward biased, its current becomes an important fraction of the drain current, and the effect of the capacitance can be neg- leted. The capacitances and C, are associated with induced depletion regions, which are formed between the silicon surface and the bulk. We assume that these regions are identical to the one that is formed in a one-sided pn junction.

For gate-source and gate-epidrain voltages higher than the threshold voltage VT, a channel is formed on the substrate under the oxide, between the source and the epidrain. In these conditions the gate-substrate capacitance may be modeled by two lumped capacitances CGs and CGD that depend on the applied voltages. The capacitances CcDo and C&pj are associated in series and represent the MOS gate-epidrain capacitance. Its threshold voltage VTEpI, is almost nil, due to the weak doping of the epidrain region.

The resistor RA represents the access resistance of the epidrain, and its effect is negligible for a great number of applications [9]. The resistor RD represents the drift resistance of the epidrain bulk region. This element is especially important for high voltage devices, since the epidrain is larger. For transistors with a high density of cells a quasi-saturation region may be present, due to the inter- cell junction field-effect transistor (JFET) effect [ 101 or due to current density saturation of the epidrain [ 111. In both cases the resistance RD becomes nonlinear. The current generator iD represents the control of the channel conductivity by the voltages applied to their terminals ( vGS and uAs).

We emphasize that the capacitances CGDO through cd,j and CGBo through c d are of the MOS type and have a

'We assign upper case subscripts to capacitances associated with the MOS structure, which are electrostatically defined, and lower case subscripts to capacitances associated with the depletion regions of pn junctions or induced by gate voltages, between silicon surface and bulk.

, 0 sub- cds '

................................................................................... -1

n+ drain

SIB (b)

Fig. I . (a) Cross section of VDMOS transistor showing capacitive effects (b) Circuit model.

voltage dependence that is only significant in a limited voltage range (Fig. 2) [12];

The gate-channel lumped capacitances CGs and CGD are dependent on the channel configuration, for which three cases are usually considered: of, saturation, and triode. The regions of operation which determine transistor performance during commutation, are the off and saturation regions for which the capacitances remain almost constant 1121, [W.

Thus, a piecewise linear model for input capacitance

= + (CGBO ) -k

and feedback capacitance

CGDT = (CGDO through cdepi ) + CGD

may be introduced. All power transistor samples tested were free of quasi-

saturation, or a slight quasi-saturation effect is noticed, near the safe operating area limits. Thus, we will assume that R D is constant. However, the quasi-saturation effect can be easily added, if necessary. The power MOSFET transfer characteristic iD( vGS ) in the saturation region is almost linear, which is due to short channel effects (typ- ically the channel length is about 1 pm). Therefore, a current-voltage equation conditioned by these effects is

CASTRO SIMAS er al . : POWER VDMOS TRANSISTORS IN COMMUTATION CAD 313

CT occumulotion

Fig. 2. MOS capacitance as function of applied voltage U,: for n substrate, U< = uMOs; forp substrate, U , = vSOM.

assumed for the current generator iD. The channel length modulation effect, due to the epidrain low doping concen- tration, is not significant and will be neglected.

PIECEWISE MODEL During commutation a MOS transistor goes through

three different regions of operation, according to the values of the applied voltages.

OFF Region For vGS < V , and VGA < V,, there is no channel, and

iD = 0. Thus, C G D = CGs = 0, and the substrate under the gate is undepleted or has a narrow depletion region, which means that c d is high and CGB, is dominant in the series. For uGE I VTEp,, there is an inversion layer in the epidrain under the oxide, which leads to a large depletion region. The associated capacitance c d e p ; is small, and dominates in the series which includes C G D o . For vGE > VTEp1, an accumulation layer exists under the oxide, and CGDO dominates over c d e p ; . There is an abrupt transition between these two situations because the epidrain is weakly doped.

Fig. 3 shows the simplified version of the circuit of Fig. l(b), for the off region, considering the following two cases of drain pdarization. 1) uGE I VTEp,, which is the usual situation in switching power converters with high drain-source voltage in the off state. 2) uGE > VTEp,, cor- responding to drain-source voltages near zero, which is usual in voltage mode resonant converters.

Triode Region For vGS > V , an inversion region is formed on the sub-

strate surface-the transistor channel-which is a low resistivity path for current flow. The channel conductivity is a function of the voltages applied to its terminals and to the gate, and we may write [14]

where

is the gate-source effective voltage, Po is a constant, a function of the MOS physical and geometrical structure

'GSS ' 3 'GAS 'T . "

Fig. 3. Equivalent circuit of VDMOS transistor operating in off-state.

( P O = p, - Cox - W / L ) , and 0 and V,, are the channel mobility reduction coefficients, due to the transverse and longitudinal electric fields. By increasing uAS, the electric field in the channel increases. For uAS = uASs, the charge carriers drift velocity reaches its saturation value at the channel drain end, and for uAS > vASs the channel current is no longer dependent on uAs. The triode region is de-

The channel acts as a shield between CGBo and cd . This last capacitance can be considered short-circuited, and CGBo is then represented by the two lumped capacitances C G D and CGs . In the model we represent this behavior by forcing c d = 0, and CGs + C G D = CGBo.

In these conditions of operation, the equivalent circuit of the VDMOS transistor (Fig. l(b)), can be simplified for the triode region, as shown in Fig. 4.

Saturation Region Beyond the limit of the triode region uAs > uAss the

drain current becomes constant and according to (1) we may write [14]

fined by V A S I v A S S .

where the saturation region onset voltage uASS is given by

(4) JV = + - uGS -k

For short channel devices ( V,, is not >> U & ) , vAss < U & , and the onset of saturation is attained before the usually considered pinch-off voltage. Thus, we will have, in saturation, either the contribution of both CGs and C G D

(before pinch-off) or only CGs ( C G D = 0, after pinch-off), which will be in this case almost equal to CGBo.

Considering, as in the off region, two cases for the drain polarization, we can simplify the circuit of Fig. l(b) for the saturation region, as shown in Fig. 5 . For all regions we have assumed for c d s the c( U ) equation of a reverse- biased junction (Figs. 3-5). When the MOS transistor is operating with a negative vDS voltage, the substrate bulk- epidrain junction is forward biased, and its current becomes an important percentage of the drain current. If necessary, this behavior can be modeled by the pn diode classical I ( V ) equation.

In Fig. 6, we present, in conclusion, the capacitances CGsT and CGDT, of the piecewise model, as a function of the uGS voltage. The boundary conditions are a function of V,, VTEp, and V,, (through uASs).

I E !EE TRANSACTIONS ON POWER ELECTRONICS, VOL. 4, NO. 3, JULY 1989

1 S=B Fig. 4. Equivalent circuit of VDMOS transistor operating in triode region.

Fig. 5 . Equivalent circuit of VDMOS transistor operating in saturation region.

c 4 = c G D O t

1 = CGSO + CGBO

Fig. 6. C,, and C,;u, as function of t i t i s .

EXPERIMENTAL CHARACTERIZATION To find the V,, VLo, Po, 0 and RD values, we use mea-

surements at the terminals, namely of the dc output and transfer characteristics. From these characteristics we fol- low a procedure similar to the one presented elsewhere [14], [15]. The threshold VT may be obtained from the transconductance versus gate-source voltage, gm ( vGs ). By derivation of the quadratic expression iD( uGS ) ( l ) , for U& = uGs - VT = 0, we obtain the linear relationship:

g m = diD/d~Gs = Po ( uGs - V , ) ( 5 ) that becomes zero for vGS = V,.

It is possible to verify that RDsON(u&) - U & , where RDsoN has its usual meaning, varies linearly with U& for high values of this voltage:

RDsoN * ubs = 1/60 + (RD + e / P o ) & s . (6) The values of 1 / P o and ( RD + e / P o ) are obtained from this straight line. To quantify the critical voltages of the mobility degradation, VLo and 1 / e , we fit the relationship iDS( U& ) ( l ) , to experimental data, using the minimum of

Fig. 7 . Test circuit for MOSFET transistor in commutation.

the standard deviation criterion. For the obtained values 1 / e and Po, and by substitution in ( RD + t9/Po) already known, we find RD. For medium and high voltage transistors ( VDS,,, > 300 V ) RD >> O/po, thus the effect of transistor channel resistance is neglected and RDSON = RD.

For the substrate bulk-epidrain junction, the reverse saturation current Is, is obtained by measuring the drain current with the transistor off ( v G s = 0 ) and applying a highly negative vDs voltage. To reduce the effect of the series drain resistance RD and increase the MOS transistor capacitance effects, the experimental characterization of the piecewise capacitances CGS , and CGD, is based on the injection of pulsed constant currents into the gate ( I F ) and drain ( I L ) terminals. For this purpose, a test circuit was designed (Fig. 7, [7]). The values of the currents, IF and ZL, may be adjusted to the specific characteristics of the transistor under test (TUT). An auxiliary transistor (AUX) is used as a current source load IL being adjusted by a potentiometer on the gate circuit. The pulsed gate current level IF is dependent on the 8-bit word that, through a digital to analog converter (DAC), commands a push-pull driver. The commutation frequency is defined by the square-wave input voltage U , (Fig. 7). The iG and iD waveforms generated by the circuit of Fig. 7 are represented in Fig. 8(a).

With such a drive and load currents, during off-on transition, the operating point of the transistor moves in the output plane i D ( v D s ) , as shown in Fig. 8(b). The TUT operates, between points A and B, with constant u D s ( uDs = VDD) because the auxiliary transistor is in the triode region; between B and C the TUT operates with constant uGS, v G S ( I L ) = V,, and between C and D operates with a low and almost constant uDS. In Fig. 8(c) we present the time evolution of the gate-source and drain-source voltages and the drain current of the TUT. The observa- tion of these waveforms leads to the consideration of three main regions, with well defined subregions, where the capacitive effects present a constant behavior, which sup- ports our piecewise model. The values of the capacitances CGsTand CGD, for each linear segment, as defined in Fig. 3 to Fig. 5 , and represented in Fig. 6, are obtained from these curves, remembering, that for constant current I

C = I A t / A v . (7) In the first region ( R l ) the TUT is commutating be-

tween the off state ( VGS < V , ) and the constant current

CASTRO SlMAS et al.: POWER VDMOS TRANSISTORS IN COMMUTATION CAD 315

WE

"as

Fig. 9. Epidrain threshold voltage calculation.

SR13 I SR21

(C) Fig. 8 . OFF-ON commutation behavior of MOS power transistor under

constant gate and drain currents. (a) Drive and load equivalent circuit. (b) Evolution of operating point. (c) Waveforms of Z J ~ ~ ( ? ) , uDS( 1). and M i ) .

drive ( iD = ZL), with vDS constant (Fig. 8(b) - A + B ). Therefore the input capacitance GIN, obtained from the vGS(r) slope is equal to CGsT + CGDT. Two linear subregions (SR11 and SR13) with a small transition region (SR12) can be considered. From SR11 (TUT off point A ) we may have CI + C3 = CIN (SRll), and from SR13 (TUT off-on - A + B ) Cz + C3 = C/N (SR13).

In the second region (R2) the MOS transistor operates in the saturation mode, with a constant current, io = IL (Fig. 8(b) - B + C). For MOS power transistors the channel length modulation effect is negligible due to the epidrain buffer effect. Thus, for constant load current we can consider vGS constant, the feedback capacitance CR = CGDT will be charged by IF and can be obtained from the vDs( t ) slope. In this region vDs( t ) shows two well defined asymptotic subregions (SR21 and SR22); the transition between them is a function of the threshold voltage of the gate-epidrain MOS diode, VTEpI (Fig. 5 ) . Within the first subregion CR (SR2 1 ) = C3 and within the second region CR(SR22) = C,.

The last region (R3) is the transistor triode region, and vDs remains constant again ( vDS = ZLRDSON - C + D). Thus, we may write C,N (R3) = CGS, + CGDT = CZ + C,, which can be calculated from the vGS( r ) slope.

In conclusion, we have obtained five equations for five parameters ( C , through C, ) as follows:

CI + C3 = CIN(SR1l)

c, + c3 = C/~(sR13)

where

and

The parameters CDso and n, are obtained by fitting the Cds equation (Figs. 3, 4, or 5 ) , to the experimental characteristic Cds ( vEs ), which can be obtained by measuring the output capacitance CO,, = Cds + C G D T , for vGS = 0.

For the definition of the boundaries of the regions and subregions, it is improtant to know, besides the threshold voltage VT already found, the threshold voltage of the epidrain VTEp,. The voltage V, (Fig. 8(c)) is, for a given current It, the voltage vDS of the knee point of the asymp- totes of the vDs( t ) curve, which corresponds to vGE = VTEp,. Thus, the threshold voltage of the epidrain VTEp, may be calculated from VF and Vx as shown in Fig. 9.

MODEL IMPLEMENTATION ON SPICE The model developed above was implemented on the

Spice program, which is the most commonly used for circuit analysis, and it is available in different versions for mainframe or personal computers.

As we emphasized above, the MOS transistor model is essentially capacitive, with the capacitances changing abruptly between different operating states of the transistor. The Spice program is not able to model this behavior. It only accepts capacitance values that are either constant

376 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 4, NO. 3, JULY 1989

or polynomially dependent on the applied voltages. Since the abrupt changes are not accurately represented by polynomials, a method was developed that makes use of auxiliary transistors that connect constant capacitances. These auxiliary transistors are modeled in such a way as to operate like “ideal” switches. In order to maintain charge continuity, the capacitance charge is forced to remain constant when the change of connection takes place.

We shall now describe the implementation of the model on Spice.

Static Model For the introduction of the current generator iD on Spice,

we consider MOSFET model level three ( LEVEL = 3 ), internally defined by the program [16]. The current generator is defined by the equations

VGS > vT, AS vASS

IDss = iD(vAs = ass), V A S > ass- (11)

The parameters in these equations are related with those introduced in (1) and (2):

I KP * W / L = Po

(12) WO = v,

THETA = e VMAX L / U O = VLo.

Since we have more parameters on the Spice model than in ours, we may assume the SPICE default values for U0 and KP and the typical value for VMAX [12].

The Spice model includes other elements besides the current generator, iD. It is important to reduce, or even cancel, their influence by giving fictitious values to some of these parameters. The oxide thickness, tax, is made very high (TOX = 1 ), to allow the nonlinear capacitances of the internal model to be neglected; the leakage current of the parasitic diode of epidrain (pn-n+) internally available Is is made very small (IS = 0). The parasitic diode pn-n’ is modeled externally by a diode pn, and thus it is not affected by the values previously defined. The epidrain drift resistance R D is associated in series with the drain of the LEVEL3 MOS transistor that introduces the current generator.

Dynamic Model The CdJ capacitance is implemented by means of a pn

diode model for which CJO = CDso, N = n and IS = I s . For the bulk function contact potential, BV, we assume the Spice default value, BV = 0.8 V. As referred above,

CGST

r”l lOOK

S

(b)

VGS < VT VGS 2 VT VGE c VTEPI VTEPI 5 VGE c VT VGE 2 VT

CGST = CGSO+CGBO = C1 CGST = CGSO+CGS = Cp CGDT = Cdepi = C3

CGDT = CGDO = C4 CGDT = CGDO+CGD = C5

+ M1 ON: M2 OFF + M1 OFF; M2 ON + M3, M5 OFF; M4. M6 ON + M4, M5 OFF; M3. M6 ON + M3, M5 ON; M4, M6 OFF

(C) Fig. IO. Spice implementation. (a) C,,,. (b) C,,,. (c) Voltage depen-

dence shown in Fig. 6, by means of auxiliary MOS switches.

the capacitances CGsT and CGD, (Fig. 6) were introduced with the help of auxiliary transistors acting as ideal switches. In Fig. 10 we present the complete auxiliary circuit, for the implementation of these nonlinear capacitances. Between gate and source (GS) and between gate and epidrain (GE), the minimum capacitance value is al- ways connected ( C, for C,,, and C3 for CGDT). The voltage at the terminals of the incremental capacitances (C, - C2 for CGST, and C4 - C, or C, - C, for CGD,) when disconnected from the circuit, does not change, in order to insure charge continuity. Following Fig. 10, transistors M1 - M2, M3 - M4, and M5 - M6 are driven by two UGS voltages, which are 180” out of phase, in order to assume such continuity. In accordance with the dependence of CGs, on vGS(TUT) Fig. 6, M1 is switched on and M2 switched off, when uGs(TUT) becomes greater than V,. In accordance with the dependence of CGDT on uGs(TUT) Fig. 6, M3 is switched on and M4 switched off, when uGs(TUT) becomes greater than VTEpI + uAS, i.e., V G ~ > VTEp,, and M5 is switched on and M6 switched off when vGs( TUT) becomes greater than V , + vAs, i.e., uGE > V,. This behavior is synthesized in Fig. lO(c). The CGsT and CGD, critical voltages are multiplied by a factor k before driving the switches’ gates Fig. 10, in order to reduce commutation transitions. The auxiliary transistors bulk substrate voltage V,, should be main- tained at a sufficiently negative value (Fig. lo), in order to avoid the direct polarization of the gate-substrate and gate-drain junctions. Their parameters have the Spice default values, with the exception of KP, which is made

CASTRO SIMAS el al.: POWER VDMOS TRANSISTORS IN COMMUTATION CAD 311

TABLE I

equal to one in order to reduce the RDsoN (the spice default values are applicable to VLSI transistors that are much faster than power transistors).

EXPERIMENTAL RESULTS Table I presents the Spice model parameters obtained

by following the method above described, for the BUZ54 transistor.

The validation of the proposed modeling technique is achieved by comparing experimental and simulated data for different circuits. The values of the capacitances of the model were obtained by external measurements for constant pulsed current drive and load conditions. Therefore one of the circuits tested was the BUZ54 with such drive and load conditions (Fig. 11). Two other cases were considered, which are related to common power electronics circuits: voltage drive with resistive load, inverter, Fig. 12; and voltage drive with inductive load, motor drive, Fig. 13. In all three cases, the results obtained show a good agreement between the simulation and the experimental curves.

For a final test, a high frequency power converter was designed and simulated on Spice,. The circuit chosen was a voltage-made quasi-resonant Cuk converter [ 171, Fig. 14(a), operating at a switching frequency of 5.5 MHz. The converter uses a Schottky diode 31DQ06 and a MOS transistor IRF732 with static and dynamic model parameters listed in Table 11. In this example the circuit operation is strongly dependent on the transistor characteristics, namely the values of its capacitances. In Fig. 14(b) the computer simulation and the experimental results are presented. It can be seen that the proposed modeling technique leads to results that agree very well with experimental results.

CONCLUSION In this paper we have presented a method for the char-

acterization of power MOS transistors that is exclusively based on external electrical measurements and is thus very useful for circuit designers. The resistance and transconductance parameters of the model are obtained from dc measurements, and the capacitive parameters are obtained from measurements with pulsed constant-current drive.

The model was implemented on the SPICE 2 simulator and has led to a good agreement between experimental and simulation results, not only for the parameter extrac- tion conditions, but also for voltage driven conditions with resistive and inductive load. Therefore, the model is well suited to the simulation of power converters and high ef-

i i i . 7

I-

Fig. 1 1 . Comparison between experiment and simulation for constant current drive (IF = 1 4 , IL = 3 A ) .

. . . . . . . . . .

. .

. . . .

. . . . : : . . : : i ! . .

c

. . : . - . . .

1 ; r r : I . _

I ! i ! . . . .

Fig. 12. Comparison between experiment and simulation for voltage drive and resistive load (V, = 10 V, RL = 17 0 ) .

I ! - . -EXP . . . .

t . . . . . I i

1; tj ... n

gate

Fig. 13. Comparison between experiment and simulation for voltage gate drive and inductive load (V, = 10 V, RL = 17 Q, LL = 190 pH).

ficiency power amplifiers. This was also proved by the close agreement between experimental and simulation results obtained with a circuit, the operation of which is strongly dependent on transistor characteristics-a voltage-mode, quasi-resonant, high-frequency Cuk converter.

experimental characterization of power vdmos transistors in commutation and a derived model for...

Documents