7 mixed signal soc design

教育部顧問室「超大型積體電路與系統設計」教育改進計畫

SOC聯盟編製

Mixed Signal in SOCMixed Signal in SOC

Department of Electrical EngineeringDepartment of Electrical EngineeringNational Cheng Kung University, National Cheng Kung University, TainanTainan, Taiwan, R.O.C., Taiwan, R.O.C.

Jhing-Fa WangJhingJhing--FaFa WangWang

Ch.7

教育部顧問室「超大型積體電路與系統設計」教育改進計畫

SOC聯盟編製

Outline

1. Introduction 1.1 System in the Real World1.2 Benefit of Mixed signal design1.3 Challenge of Analog/Digital Integration

2. Design Flow2.1 Introduce to Verilog-A 2.2 Tool used in Mixed signal coding & simulation2.3 Feature work in Mixed signal design for EDA Tool

3. Substrate noise couple in Mixed signal design3.1 Source of substrate noise3.2 Current Technique in prevention of substrate noise3.3 Future Research in substrate noise

4. Conclusion

教育部顧問室「超大型積體電路與系統設計」教育改進計畫S

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1.1System in the Real World


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Conventional design in Mixed-signal system


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AAn age of SOCn age of SOC

w Recently ,the requirement of the mobile device is raising ,the demand of Low power、small area and Real time is strict

w SOC is the solution to the all


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1.2 Benefit of Mixed signal design

w Push the limited of system performance Reduce I/O driving loadsExploit design space between blocks

w Push the limited of power dissipationReduce parasitic loadsReduce I/O driving currents

w Reduce the system size


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1.3 Challenge of Analog/Digital Integration

w High design complexityCapacity and efficiency of EDA toolDifferent design knowledge

w Increasing process complexity w Substrate noise coupling prevention


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2. Mixed signal design flow

2.1 Introduce to Verilog-A 2.2 Tool used in mixed signal coding & simulation2.3 Feature work in Mixed signal design for EDA

Tool


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Conventional mixed signal design toolConventional mixed signal design tool

CircuitSwitch

Gate

Behavioral

Verilog HDL

SPICE

Analog Digital

Lower

Higher

Description Domain

AbstractionLevel

Because of lacking in analog behavior language “Verilog-A”, can’t do system function simulation


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CircuitSwitch

Gate

Behavioral

Verilog HDLVerilog-A

Analog Digital

Lower

Higher

Description Domain

AbstractionLevel

Verilog-A play a major rote In system simulation

Novel mixed signal design toolNovel mixed signal design tool


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Benefits of system simulationBenefits of system simulation

♦ Greater understanding of the system architecture with rapid optimization by previewing trade-off and discarding unworkable ideas early.

♦ Can better develop simulation and test strategies

♦ Supports partitioning and budgeting analysis.

♦ Block specifications can be driven by the system simulation.

♦ Supports concurrent designs with multiple engineers where the circuit blocks and system can proceed in parallel.

♦ Can quickly adopt late changes into the design with minimum impact.


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Verilog-A

w An extension of the Verilog language to describe analog/mixed signal system modelsw To be compatible with Verilogw An OVI(Open Veriog international) Standardw An multidiscipline language that models electrical,

mechanical, fluid dynamic, and thermodynamic systemsw Can be used for supporting Top-down design


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TopTop--Down Design MethodologyDown Design Methodology

Transistor-LevelCircuit Design starts at the System-Level and works down to the Circuit Block and Transistor-Levels using a combination ofbehavioral models and transistor-level simulations

Circuit Block-Level

Top Chip-Level

System-Leve

l

Synthesis

(SPW, Matlab)

System-Level

Source from Robert A. Mullen with Cadence.


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Analog/Mixed Signal Description Language

MicrowaveAnalogDigitalSystem

HSPICE

VHDL ’93

Verilog ’95 Verilog_A ’96

Verilog-AMS ‘98

VHDL-AMS ’99 RF extension


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Verilog-A


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Veriolg-A Modeling Approaches


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2.2 Tool used in Mixed signal coding & simulation

Digital Analog

System System

Gate Circuit

Verilog-AMSVerilog-AVerilog

Mixed-Signal Verilog Simulation Verilog-AMS approved by OVI in August 1998

Source from Robert A. Mullen with Cadence.


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Design Flow

Without synthesis

Without standard cell library


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Mixed signal simulation flow


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Creating Analog block and symbol


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Integrating Design Using Composer


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Adding Simulation Input


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Analog Stimuli

w The Analog Stimulus can be added either with circuit component in analogLib or with spectre AHDL stimulus format

•Edit a behavioral for the block•Create Symbol view•Add the symbol in top schematic view


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Digital Stimulus

1. Create a behavioral view for the stimulus block2. Define the stimulus module3. Add verilog command to force input signal 4. Create a symbol view for the block5. Add the symbol into top schematic view


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Set block partition


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Define detail interface element


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Analog to digital interface


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Digital to analog interface


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Created netlist(analog)


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Create netlist(digital)


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Submit the simulation


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Run log file


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Layout integration and verification for mixed signal design

w Most of the issues follow the cell-based design approach


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Layout integration flow

Must built a black box for analog part

Analog is a black box with I/O informationCreate boundary

of layout


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Abstract generation

w Place and route tool needs pin information for block routingw The manual layout contains only geometry

information, need to define pin location and information for P&Rw The pin and boundary information are defined in

abstract view w After Abstract generation, a LEF file will be

generated for Silicon Ensemble Verilog in


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Module declaration

w In order for P&R tools to route the connect between analog and digital blocks, the analog must be in verilog netlist and connected

w Since there might not be any Verilog statement that can model the analog block , the analog block contains only I/O port information

w Must be enabled Don’t touch when synthesis


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Top level verilog netlist integration

w The final chip must contain I/O pads, these I/O information were also provided by verilog netlist


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Some matters needing to attention in mixed signal layout(1/2)

1. Prevent noise coupling: the noise come from device itself, power supply, cross talk, substrate coupling, etc. The methods to suppress are adding chock between power supply and bias in circuits, and using shielding method in critical path

2. Placement: Analog block is better placed in corner of chip, to reduce the connection with digital black

3. Device matching: the level of major are like analog design


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Some matters needing to attention in mixed signal layout(2/2)

4. Pad placement: power ground pad must be separated, because analog circuit need stable power source

5. Guard ring: It is regarded as the collector of transistor can collect the minority carrier in substrate, and used around the sensitive circuits

6. Parasitic effect: the level of major are like analog design


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2.3 Feature work in Mixed signal design for EDA Tool

1.1. Analog SynthesizerAnalog Synthesizern Analog building blocks are more complex and variedn Analog synthesis is in its infancyn Will take years to have an impact, if it ever does

2.2. Circuit level simulatorCircuit level simulator3.3. Substrate noise simulatorSubstrate noise simulator


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3. Substrate noise couple in Mixed signal design

3.1 Source of substrate noise3.2 Current Technique in prevention of substrate

noise3.3 Future Research in substrate noise


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3.1 Source of substrate noise


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Source of substrate noise


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Substrate Model

w Lb a bond wire that exhibits an unwanted inductance

w The large voltage excursions at the drain of M are coupled to the substrate through Cdb2


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3.2 Current Technique in prevention of substrate noise

1. Different operation should be used throughout the circuit, making the analog section less sensitive to common-mode noise

2. Digital signal and clocks should be distributed in complementary form

3. Critical operations, e.g., sampling a signal or transferring charge from one capacitance to another, should be performed well after clock transitions

4. The inductance of the bond wire connected to the substrate should be minimized

5. Op amps using a PMOS differential input are preferred


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other consideration in prevention of substrate noise

1. Connecting the substrate to GNDA is preferred2. What benefit do I get by splitting my power supply?3. What immunity do I gain by backside plating?4. How wide should my guard ring be?5. What is the most sensitive part ?6. I have 5 isolation structures

--which is optimal for this design ？


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Connecting the substrate to GNDA

is preferred

Connecting the substrate to GNDA is preferred, because it ensures the analog ground voltage and the substrate potential vary in unison


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Example(1/2)

FFSBv φφγ 22(VV t0t −++=


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Example(2/2)


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Splitting powerSplitting power


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Backside GroundingBackside Grounding


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NNoise increases with frequencyoise increases with frequency


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WWhat is the most sensitive part ?hat is the most sensitive part ?


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Differential Input Pair


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Feedback Circuit


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3.3 Future Research in substrate noise

1. More exact model for substrate noise 2. Good design technique to suppress substrate noise3. Good isolation technique to prevent substrate

noise


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4.Conclision

w Mixed-signal design( integration of analog and digital) is necessary for cost down and low powerw EDA tool is still imperfect for mixed-signal design w Substrate noise is already a major problem and will

remain so for some time


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ReferencesReferences

w Behzad Razavi，Design of Analog CMOS Integrated Circuits ，Los Angeles :MCGraw-Hill,2001

w 姜信欽，劃時代的產業革新單晶片系統(SoC)最新技術與應用， Sept. 7, 2000w CIC訓練課程，Mixed-Signal Simulation Training Manual，July-2001w Philippe Duchene，Substrate Noise Analysis and Solution with Substratestorm，2001

Simplex Solution.Inc

w Geodge Gielen，Analog Silicon Compiler for Mixed-Signal ASICS

7 mixed signal soc design

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