continuous time and switched capacitor...

F. Maloberti

:

Design of CMOS Analog Integrated Circuits -

”Continuous Time and Switched Capacitor Filters” 8/1

D

ESIGN

OF

CMOS A

NALOG

I

NTEGRATED

C

IRCUITS

Franco Maloberti

Integrated Microsistems LaboratoryUniversity of Pavia

Continuous Time and SwitchedCapacitor Filters

F. Maloberti

:



OUTLINE

Electrical Filters

Single op-amp realization

Cascade and multiple loop feedback

Switched capacitor technique

Biquadratic SC filters

SC N-path filters

Finite gain and bandwidth effects

Layout consideration

Noise

F. Maloberti

:



ELECTRICAL FILTERS

Electrical filters is an interconnection network of electrical components which operates a modification of the frequency spectrum of an applied electrical signal.

The network is linear and time invariant.

F

ILTER

DESIGN

PROCEDURE

:

•

Filter specifications

•

Design of the network that implements the specifications

•

Component values evaluation

F. Maloberti

:



Filter specification:

Is usually defined by a mask which specifies the range of allowed fre-quency responses.

The frequency range is divided into:

•

Pass band

•

Stop band

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AAAAAAAAAAAAAAAAAA

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AAAAAAAAAA

AAAAAA0 dB

Pass band Stop band

F. Maloberti

:



Usually, they are specified:

•

Ripple in the pass band

•

Attenuation in the stop band

Specification of the phase response:

•

Usually linear phase response

Type of filters:

•

Low pass, low pass notch

•

High pass, high pass notch

•

Band pass, band reject

•

All pass

Φ f( ) k f f0–( )=

F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/6

Networks:

Filter specifications are met with linear networks which determine atransfer function of the form:

Pm(s) and Qn(s) are polynomial of order m and n respectively. The ze-ros of Pm(s) are the zeros of the transfer function. The zeros of Qn(s)are the poles of the transfer function. Always n ≥ m.

The number of poles gives the order of the filter.

• The ripple in the pass-band and the transition between the

stop-band and the pass-band determine the order of the filter

H s( )Pm s( )Qn s( )----------------=


• Transmission zeros in the

stop-band help in getting

a sharper transition

• Very elementary specifications are met with first order or second

order filters.

First order:

Second order filter or biquadratic (biquad) filter:

|H||H|

f f

R

C

C

R

in out in out

LOW PASS HIGH PASS

HLP1

1 sRC+----------------------=

HHPsRC

1 sRC+----------------------=


Low pass response:

High pass response:

Low pass notch response:

High pass notch response:

H s( ) k

s2 sωz

Qz------- ωZ

2+ +

s2 sω0

Q0------- ω0

2+ +

---------------------------------------⋅p0 sp1 s2p2+ +

s2 sω0

Q0------- ω0

2+ +

----------------------------------------= =

ωz ∞ k p0 ωz2⁄( ) p0→→ 1 p1 0 p2 0= = =

p0 1 p1 0 p2 0 ωz 0= = = =

p0 0 ω2 ω1>=


Band pass response:

All pass response:

p1 0 ω2 ωp<=

p0 0 p1 kωz

Qz------- p2 0= = =

p0 ω02 p1

ω0

Q0------- p2– 1= = =


Active realization of biquadratic transfer functions:

Eliminating V1 it results:

Vin

Z1

Z2

Z3

-

+

_

+

-1

R1

R2

C2

V1

V0

C1

s– C1V1 Y1Vin Y3V0+=

sC2 G2+( )V0 Y2Vin G3V1+=


• Note that, for stability reasons, the inverter and a dumping (R2 or

dissipative Z3) are requested around the loop

• The admittances Y1, Y2 and Y3 have usually the form Y = G+sC

V0

Vin--------

sC1Y2 G1Y1–

sC1 sC2 G2+( ) G1Y3+-------------------------------------------------------------=

V in

Z1

Z2

Z3

+

+

-1

R1

R2

C2

V1

V0

C1

_

_

s– C1V1 Y1Vin Y3V0+=

sC2 G2+(– )V0 Y2Vin G1V1+=

V0

Vin--------

sC1Y2 G1Y1–

sC1 sC2 G2+( ) G1Y3+-------------------------------------------------------------=


SINGLE OP-AMP REALIZATION Sallen and Key filter:

VinZ Z + Vout

Z'

Z'2

1

1 2

_

H s( )Vout s( )Vin s( )-------------------

Z′1Z′

2

Z1 Z2 Z′2+ +( )Z′

1 Z1Z2+-----------------------------------------------------------------= =


For low pass response:

For maximally flat response: ; ;

Key features:• The op-amp is in buffer connection, input swing must be equal to the

output swing.

• In the pass-band no current flows on the resistances (even if they

are non linear, non harmonic distortion results).

Vin

_

+ Vout

R R

C1

C2

Z1 Z2 R= = Z′1

1sC1----------=

Z′2

1sC2----------=

H s( ) 1

1 2sRC2 s2R2C1C2+ +---------------------------------------------------------------=

Z1 2 2⁄= C1 2C2= fp1

2πRC 2------------------------=


Rauch filter

VinZ Z _

+

Vout

Z'1

1 2

Z' 2

Z 3

H s( )Vout s( )

Vin s( )--------------------- 1Z1Z3-------

Z2Z ′2-------- 1

Z1Z ′1--------

Z1Z2-------

Z1Z3-------+ + +

+

---------------------------------------------------------------------------–= =


For low pass response:

For maximally flat response:

;

Vin-

+

Vou

R1 R2

3

C2

C1

Z1 R1= Z2 R2= Z3 R3=

Z′1

1sC1----------= Z′

21

sC2----------=

H s( ) 1R1

R3------- sC2 R1 R2

R1R2

R3--------------+ +

s2R1R2C1C2+ +

------------------------------------------------------------------------------------------------------------------–=

R1 R3 2R2 2R= = = C1 4C2 4C= =

fp1

4πRC 2------------------------=


Key features:

• The op-amp has the non inverting input referred to the ground.

• In the pass-band there is a current flowing into the resistors.

Low pass Sallen and Key filter with real op-amp:

A real op-amp used in CMOS monolithic S&K filter is a transconductanceop-amp

Vin

-

+

VoutR R

2C

Cgm vi

vi

R0 C0


With the above equivalent scheme:

The transfer function has two zeros and three poles.If k = Rgm >> 1 the zeros are practically complex conjugates and are lo-cated at

The extra-pole is real and is located around the GBW of the op-amp.

H s( )1 2sC gm⁄ 2s2RC2 gm⁄+ +

α sβ s2γ s3δ+ + +------------------------------------------------------------------------=

α 1 1A0------+= β 2RC

R0C0 2R0C 4RC+ +

A0-------------------------------------------------------+=

γ 2R2C2 1A0------ 4RR0C C C0+( ) 2R2C2

+( )+= δ 2R2C2

C0--------------gm⋅= A0 gmR0=

ω0 gm 2RC2⁄ ωp k= =


A low value of k = Rgm deter-mines a shift of the poles of theS & K filter with respect to thedesigned position

-60

-50

-40

-30

-20

-10

0

10

log f

1

23

f T1 f T3f T2 1: f /f = 100 T p

2: f /f = 20 T p

3: f /f = 4 T p

K= 40

0 20 40 60 80 10040

50

60

70

80

90

100K=100

K=10

K=3

f /fT p

norm

aliz

ed m

odul

e of

pol

es (%

)


Design criteria:

• Use an op-amp with fT > 20 fp

• Use resistances R > 40/gm

0 20 40 60 80 1000,6

0,7

0,8

0,9

f /fT p

K=100

K=10

K=3Q

fact

or (n

omin

al v

alue

0.7

07)


Low pass Rauch filter with real op-amp:

The transfer function has one zero and three poles.

The zero is far away from fp if A0 >> 1

Vin_

+

Vout

2R R

2R

C

4C

gm vi R0C0

H s( )1– s R R0+( )C A0 1+( )⁄+

α sβ s2γ s3δ+ + +----------------------------------------------------------------------=

α 1 4A0 1–----------------+=

β 4RC2R0C0 R0C 13RC+ +

A0 1–-----------------------------------------------------------+=

γ 8R2C2 6RR0CC0 2RR0C2 18R2C2+ +

A0 1–-------------------------------------------------------------------------------------+= δ 8

R2R0C0C2

A0 1–-----------------------------gm⋅= A0 gmR0=


The extra-pole is around the unity gain frequency of the op-amp

The two other poles are shifted with respect to the designed location

-80

-60

-40

-20

0

20

log(f)G

ain

(dB

)

1

23

1: f /f = 100 T p

2: f /f = 20 T p

3: f /f = 4 T p

K= 40

0 20 40 60 80 10080

90

100K=100

K=10

K=3

f /fT p

odule of poles (%

)

norm

aliz

ed m

odul

e of

pol

es (

%)

f /fT p

nominal value 0.707)

K=100K=10

K=3

0 20 40 60 80 1000,5

0,6

0,7

0,8

Q fa

ctor

(no

min

al v

alue

0.7

07)


Effect of the integrated resistors:

R

Y

Y P Y P

Y sC R⁄sRCsinh

----------------------------=

YP Y sRC 1–( )cosh( )=

-60

-50

-40

-30

-20

-10

0

10

1

2

3

1: f /f = 100 T p

2: f /f = 20 T p

3: f /f = 4 T p

K= 40

log(f)

Gai

n (

dB

)

-60

-50

-40

-30

-20

-10

0

10

1

2

3

1: f /f = 100 T p

2: f /f = 20 T p

3: f /f = 4 T p

K= 40

log(f)

Gai

n (

dB

)


HIGH ORDER FILTERSThere are several way to realize high order ( > 2 ) filters. We will con-sider:

Cascade realization

Multiple loop feedback

Cascade realization:

Consists in the cascade connection of isolated biquad sections.Hi(s) is the biquad transfer function.

vin

RS

RLH (s)

1H (s)

2H (s)

N

Zin,1 Zout,1 Zout,2 Zout,NZin,2 Zin,N


For getting isolation it must be:

A given specification is met with a rational transfer function:

szi and spi are the zeros and the poles of F(s) (real or complex conju-gate)

Rs Zin 1, Zout i, Zin i 1+, Zout N, RL«««

H s( )Vout s( )Vin s( )------------------- Hi s( )

i 1=

N

∏= =

F s( )a0 a1s a2s2 ... a+ msm

+ + +

b0 b1s b2s2 ... b+ nsn+ + +

-------------------------------------------------------------------------am

bn-------

s szi–( )i 1=

m

∏

s spi–( )i 1=

m

∏------------------------------⋅= =


Design problem: group together pole and zero pairs (pole-zero pairing): it affects the dynamic range and the sensitivity.

Unfortunately there are not general and consistent rules for the pole-zero pairing in order to minimize the sensitivity.

Two opposite approaches are suggested in the literature:

• Pair the high-Q poles with far away zeros

• Pair the high-Q poles with closed zeros

The only solution is to try different pairing and to compare them with Monte Carlo analysis.

For order > 6 the cascade design is inherently more sensitive to component variation than multiple-loop feedback realizations.


MULTIPLE LOOP FEEDBACK REALIZATIONS

Several topologies:

• Follow the leader feedback (FLF)

• Inverse follow the leader (IFLF)

• Generalize follow the leader feedback (GFLF)

• Primary resonator block (PRB)

• Leapfrog feedback (LF)

• Modified leapfrog feedback (MLF)

• Coupled biquad (CB)

• Minimum sensitivity feedback(MSF)


LEAPFROG TOPOLOGY Simulate passive ladder networks, via signal flow graph

Vin

RS

C1 C3 C5

L2 L4

R6

I0

I4I2

V1 V3 V5 Vout

I6

I01

Rs------ Vin V1–( )=

V11

sC1---------- I0 I2–( )=

I21

sL2--------- V1 V3–( )=


If we multiply each current by an arbitrary resistance R, we define new“dummy” voltage variables

V31

sC3---------- I2 I4–( )=

I41

sL4--------- V3 V5–( )=

V51

sC5---------- I4 I6–( )=

I61

R6-------V5=

Vout V5=

V0 RI0= V2 RI2= V4 RI4= V6 RI6=


The equations becomes:

V0RRs------ Vin V1–( )=

V11

sRC1--------------- V0 V2–( )=

V2R

sL2--------- V1 V3–( )=

V31

sRC3--------------- V2 V4–( )=

V4R

sL4--------- V3 V5–( )=

V51

sRC5--------------- V4 V6–( )=

V6RR6-------V5=


The original set of equations and the modified one can be repre-sented with the signal flow graphs:

1/Rs 1/sC1 1/sC3 1/sC51/sL2 1/sL4

+ _ + + +

+ _ + _ + _

1/R6

Vin V1 V5V3

I6I4I 2I0

R/Rs 1/s 1/s 1/s 1/s

+ _ + + _ +

+ _ + _ + _

R/R6

Vin V1 V5V3

V6V4V2Vs

t4t3 t51/s

___

t1 t1

_


Scaling of the flow graph:

Variable transformation Scaling by constants

1/sL2

+ _

_ +

V1 V3

I2

R/sL2

+ _

1/R +1/R

V1 V3

V2

1/sC3

1V3

I2

1/sRC3

V3

V2I4 V4+ _ + _

_ + _ +

_

1/s

1V3

V2

k/s

V3

V2V4 V4+1/k 1/k

_ + _ +

t3 t3

1/s

1V3

V2

1/s

V3

V2V4 V4+_

_ + _ +

t3 t3

+ _

+ _

_

_


The scaling of the flow graph is used in order to obtain realizable ac-tive implementations

• Inverting

integrators

• Inverters

• Summators

Interconnection ofsecond order loops(R ≈ Rs ≈ R6)

R/Rs 1/s 1/s 1/s 1/s

+ _ _ _ _ _ _

+ + + + + +

R/R6

Vin V1 V5V3

V6V4V2Vs

t1 t4t3 t51/s t2_ _ _ _ _ _

t1 t

2

t3 t

4

t5

1 1 1 1

1 1 1 1 1 1

1

-1 -1 -1

in

out

_ _

_ _


The scaling is also useful for dynamic range optimization:

V1 is too small

V2 is too high

Result: all the op-amp saturate (at different frequency) with the sameinput level.

Perform a SPICE simulation of the active (or passive) network in order to determine the scaling factors.

H1

Hout

H2

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f

Gai

n (d

B)

V1 K1V1→

V2 V1 K2⁄→


If the passive prototype has transmission zeros at the finite (elliptic filters), it hasthe form (low pass).

Before to describe the network and sketch the flow diagram it is worth to removethe bridging capacitors C2 and C4 through the use of the Thevenin’s theorem

Vin

RS

C1 C3 C5

L2 L4

R6

V1 V3 V5

Vout

C2 C4

C1 C3

L2V1 V3

C2

C1 + C2 C3 + C2

L2V1 V3

+ +

V3a1 V1a2

a1 =C2 /(C1 +C2 ) a2 =C2 /(C3 +C2 )


Similar modification follows if C4 is removed

The equations concerning the state variables V1, V3 and V5 change:

C1’ = C1 + C2

C3’ = C2 + C3 + C4

C5’ = C4 + C5

Vin

RS

C2+C3+C4

L2 L4

R6

V1 V3 V5 Vout

C1+C2

+

V3a1

C4+C5

+

V3a4a2

+

a1 =C2 /(C1+C2 ) a2 =C2 /(C3+C2)

a3 =C4 /(C3+C4 ) a4 =C4 /(C5 +C4)

V1+a3 V5

V11

sC ′1------------ Is I2–( )

V3C2

C1--------------+=

V31

sC ′3------------ I2 I4–( )

V1C2

C1 C3+--------------------

V5C4

C3 C4+--------------------+ +=

V51

sC ′5------------ I4 I6–( )

V3C4

C5--------------+=


After scalings, aimed to the active realization:

R/Rs 1/s 1/s 1/s 1/s

+ _ _ _ _ _ _

+ + + + + +

R/R6

Vin V1V5

V3

V6V4V2Vs

t1 t4t3 t51/s t2_ _ _ _ _ _

t1

t2

t3 t

4

t5

1 1 1 1

1 1 1 1 1 1

1

-1 -1 -1

in

out

a1

a2

a3

a4

_ _

_ _


SWITCHED CAPACITOR TECHNIQUE

An active filter is made of op-amps, resistors and capacitors.

The accuracy of the filter is determined by the accuracy of the realized time costants since the capacitors and resitors are realized by uncorrelated technological steps

In CMOS technology ; ; hence , unacceptable for most of the applications

Hybrid realization with functional trimming

δττ-----

2 δRR

------- 2 δC

C-------

2+=

δR R⁄ 40%≈ δC C⁄ 30%≈ δττ----- 50%≈


Problems for a fully integrated realization• Accuracy

• Values of capacitors and resistors: for 70 nm oxide thickness 1 pF --

> 2000 µ2; 10 pF is a large capacitance. To get τ = 10-4 sec R = 107

Ω

The above problems are solved by the use of simulated resistorsmade of switches and capacitors.

MOS technology is suitable because:

Offset free switches

Good capacitors

Satisfactory op-amps


Simple SC structures

∆Q = C1 (V1 - V2) every ∆t = T

1

2

Φ1 2

I

AAA

AAA

AAAA

AAAA

1

2

C1

C1

I

T

T

V1 V2

V1 V2

Φ

ΦΦ

Φ

Φ


The two SC structures are(on average) equivalent to a resistor

If the SC structures are used to get an equivalent time constant τeq = ReqC2it results:

AAA

AAAAAAAA

I

V1 V2

T

t

I

∆Q i∆tV1 V2–

R-------------------T= =

ReqT

C1-------=

τeq TC2

C1-------=


• Its accuracy depends on the clock and on the capacitor matching

accuracy

• If τeq=40 T C2 = 40 C1 (acceptable spread) regardless of the value of τeq

A more complex SC structure:

The charge is transferred twice per clock period T or we assume asclock period half of the period of phases Φ1 and Φ2.

Φ1V1

Φ2

V2Φ2

Φ1

∆Q 2C1 V1 V2–( )=


SC INTEGRATOR

Starting from the continuous-time circuit of the Integrator, we can ob-tain a SC integrator by replacing the continuous-time resistor with theequivalent resistances as follows:

+

_

R1

C2


Φ1 Φ2+

_

C1

C2

+

_

C1

C2

+

_

C2

C 1

Φ1

Φ1

Φ1

Φ2

Φ2

Φ2

Φ2

Φ1

Φ1

Φ1


We consider the samples of the input and of the output taken at the same times nT (the end of the sampling period).

• Structure 1:

taking the z-transform:

• Structure 2:


Vout n 1+( )T[ ] Vout nT( )C1

C2-------Vin nT( )–=

Vout z( )Vin z( )-------------------

C1

C2------- 1

z 1–------------⋅–=


C2-------Vin n( 1 )T ]+–=


• Structure 3:


Remember that for the continuous-time integrator:

Comparing the sampled-data and continuous-time transfer functions we get:

Vout z( )Vin z( )-------------------

C1

C2------- z

z 1–------------⋅–=


C2------- Vin n 1+( )T[ ] Vin nT( )+ –=

Vout z( )Vin z( )-------------------

C1

C2------- z 1+

z 1–------------⋅–=

Vout s( )Vin s( )------------------- 1

sR1C2------------------–=


• Structure 1:

FE approximation

• Structure 2:

BE approximation

• Structure 3:

Bilinear approximation

It does not exist a simple SC integrator which implement the LD approximation.

Note: the cascade of a FE integrator and a BE integrator is equivalent to the cascade of two LD integrators.

R1T

C1------- s

1T--- z 1–( )→→

R1T

C1------- s

1T--- z 1–( )

z-----------------→→

R1T

2C1---------- s

2T--- z 1–( )

z 1+( )-----------------→→


The key point is to introduce a full period delay from the input to the output

The same result is got with:

Φ1 Φ2

+

_

Φ2Φ1 +

_

C2

C1

C1

C2'

'

Φ1 Φ2

+

_Φ2 Φ1

+

_

C2

C1

C2

'

'

C1


STRAY INSENSITIVE STRUCTUREThe considered SC integrators are sensitive to parasitics.

Toggle structure:

• The top plate parasitic capacitance Ct,1

is in parallel with C1

• It is not negligible with respect to C1

and it is non linear

• The top plate parasitic capacitance Ct,1

acts as a toggle structure

Φ1 Φ2C1

Ct,1 Cb,1

Φ1

Φ2C1

Ct,1 Cb,1


Bilinear resistor:• Both the parasitic

capacitances Ct,1, Cb,1 act

as toggle structures. Their

values are different (of a

factor ≈ 10) and they are

non linear.

• Stray insensitivity can be

got for the first two

structures if one terminal is

switched between points at

the same voltage.

Φ1

Φ1

Φ2

Φ2

C1

Ct,1

Cb,1

C1

Φ1Φ2

Φ1Φ2

Virtualground

C1

Φ1Φ2

VirtualgroundΦ2

Φ1


• The right-side parasitic capacitor is switched between the virtual

ground and ground (note: even in DC Vv.g. must equal Vground)

• The left side capacitor is connected, during phase 1, to a voltage

(or equivalent) source.

• The charge injected into virtual ground is important, not the one

furnished by the input source.

• Structure A is equivalent to the toggle structure, but the injected

charge has opposite sign.

• Equivalent negative resistance allows to implement non inverting

integrators.

• It is possible to easily realize a stray insensitive bilinear resistor

with fully differential configuration.


SC BIQUADRATIC FILTERSConsider a (continuous-time) biquadratic transfer function

If the bilinear transformation is applied, it results a z-biquadratic trans-fer function

where the coefficients are:

H s( )p0 sp1 s2p2+ +

s2 sω0

Q0------- ω0

2+ +

----------------------------------------=

H s( )a0 za1 z2a2+ +

b0 zb1 z2b2+ +----------------------------------------=

a0 p02T---p1–

4

T2------p2+=


a1 2p08

T2------p2–=

a2 p02T---p1

4

T2------p2+ +=

b0 ω02 2

T---

ω0

Q------– 4

T2------+=

b1 2ω02 8

T2------–=

b2 ω02 2

T---

ω0

Q------ 4

T2------+ +=


All the stable z-biquadratic transfer functions are realized by the topology:

AAAAAAA

AAAAAAA

AAAAAAA

+

-

+

-

G

D

E

C

A

B

F

I

J

H

1

F1

F2

Vin

t

V01V02


Features:

Loop of two integrators one inverting and the other noninverting.

Damping around the loop provided by capacitor F or (and) capacitor E (usually only E or F are included in the network).

Two outputs available V0,1 V0,2.

Denominator of the transfer function determined by the capacitors along the loop (A, B, C, D, E, F).

Transmission zeros (numerator) realized by the capacitors (G, H, I, J).

Input signal sampled during Φ1 and held for a full clock period

Charge injected into the virtual ground during Φ1.


Minimum switch configuration:

C2

C1

Cn

C2

C1

Cn

+

_

+

_

GD

E

C

AB

F

I

J

H

1


Charge conservation equations:

DV0,1(n+1) = DV0,1(n) - GVin(n+1) + HVin(n) - CV0,2(n+1) - E[V0,2(n+1) - V0,2(n)]

(B + F)V0,2(n+1) = BV0,2(n) + AV0,1(n) - IVin(n+1) + JVin(n)

Taking the z-transform and solving, it results:

• 10 Capacitors

• 6 Equations a0, a1, a2, b0, b1, b2

• Dynamic range optimization

H1

V0 1,Vin

----------- IC IE GF– GB–+( )z2 FH BH BG JC– JE– IE–+ +( )z EJ BH–( )+ +

DB DF+( )z2 AC AE 2DB– DF–+( )z DB AE–( )+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------= =

H2

V0 2,Vin

----------- DIz2 AG DI– DJ–( )z DJ AH–( )+ +

DB DF+( )z2 AC AE 2DB– DF–+( )z DB AE–( )+ +-------------------------------------------------------------------------------------------------------------------------------------------= =


• Scaling for minimum total capacitance in the groups of

capacitors connected to the virtual ground of the op-amp1 and

the op-amp2.

• Since there are 9 conditions, one capacitor can be set equal to

zero

E = 0 “F type”

F = 0 “E type”

Firstly the 6 equations are satisfied. Later capacitors D and Aare adjusted in order to optimize the dynamic range. Finally allthe capacitor connected to the virtual ground of the op-amp arenormalized to the smaller of the group.


Scaling for minimum total capacitance

Assume that C3 is the smallest capacitance of the group. In order to makeminimum the total capacitance C3 must be reduced to the smallest value al-lowed by the technology (Cmin)

• Multiply all the capacitors of the group by

+

_

C2

C1

C3

C4

Cn

kCmin

C3------------=


• All these design steps can be performed with a suitable computer

program

Equivalences for input structures:

G

H

G-H

H

G

H-G

G

for G>H

for G=H

for G<H


SC LADDER FILTERSOrchard’s observationDoubly-terminated LC ladder network that are designed to effect max-imum power transfer from source to load over the filter passband fea-ture very low sensitivities to value component variation.

Syntesis of SC Ladder Filters:

Symple approach

• Replace every resistance Ri in an active ladder structure with

a switched capacitor Ci = T/Ri.

• Use a full clock period delay along all the two integrator loop (it

results automatically verified in single ended schemes).

It results an LD equivalent, except for the terminations.


Quasi LD transformation:

Prewarp the specifications using sin(ωT/2)

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DESIRED SPECIFICATION

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PREWARPED SPECIFICATION

sin( pb T/2) sin( sb T/2)


Effect of the terminations:

if R1 = T/ C1 and R3 = T/C3 we get:

+

_

R1

R

C2_

+

_

C2C1

C3

HDI s( )R3

sC2R1R3 R1+---------------------------------------= HDI s( )

C1

sTC2 C3+----------------------------=

Vout n 1+( ) C2 C3+( ) Vout n( )C2 C1Vin n( )+=


Taking the z-transform we get:

along the unity circle z=ejωT

The half clock period delay will be used in the cascaded integrator inorder to get the LD transformation

• The termination is complex and frequency dependent.

• The integrating capacitor C2 must be replaced by C2 + C3/2.

zVout C2 C3+( ) C2Vout C1Vin+=

HDI z( )C1

C2 z 1–( ) zC3+-----------------------------------------

C1z 1 2⁄–

C2 z1 2⁄ z 1 2⁄––( ) z1 2⁄ C3+

---------------------------------------------------------------------= =

HDI ejωT( )C1e j– ωT 2⁄

C2 ejωT 2⁄ e j– ωT 2⁄–( ) ejωT 2⁄ C3+

-------------------------------------------------------------------------------------C1e j– ωT 2⁄

2j C2 C3+( ) ωT2

-------- C3ωT2

--------cos+sin---------------------------------------------------------------------------------= =


Complex termination:

Note: the output voltage changes during Φ

Taking the z-transform:

+

_

C2C1

C3

F1

Vout n 1+( )C2 Vout n( )C2

2

C2 C3+-------------------- C1Vin n( )+=

zVoutC2 Vout C2

C2C3

C2 C3+--------------------–

C1Vin+=


along the unity circle z=ejωT

• The imaginary part of the contribution of the termination is

negative

• The integrating capacitor must be replaced by

HDI z( )C1

C2 z 1–( )C2C3

C2 C3+--------------------+

----------------------------------------------------C1z 1 2⁄–

C2 z1 2⁄ z 1 2⁄––( ) z 1– 2⁄ C2C3

C2 C3+--------------------+

-------------------------------------------------------------------------------------= =

HDI ejωT( )C1e j– ωT 2⁄

2j C212---

C2C3

C2 C3+--------------------–

ωT2

--------C2C3

C2 C3+-------------------- ωT

2--------cos+sin

----------------------------------------------------------------------------------------------------------------=

C2 C212---

C2C3

C2 C3+--------------------–


Example: 5th order filter

Passive prototype

Flow diagram

SC implementa-tion

Vin

RS

C1 C3 C5

L2 L4

R6

IS

I4I2

V1 V3 V5 Vout

I6

R/Rs 1/s 1/s 1/s 1/s

+ _ _ _ _ _ _

+ + + + + +

R/R6

Vin V1 V5V3

V6V4V2Vs

τ1 τ4τ3 τ51/s τ2_ _ _ _ _ _

_

_ _

_+-

+-

+-

+-

+-

1 1

1

1 1 11 1

1

1 1

τ1T

τ3T

τ2T

τ4T

τ5T


EXACT DESIGN OF SC LADDER FILTERS A continuous-time network is exactly transformed into a sampled-

data network through the mapping z = exp(sT).

We can assume that an exact transformation is realized even through the LDI or the bilinear mapping, provided that the required pre-warping is made.

The exact LD design of ladder filter is not possible because of the error given by terminations.

The exact bilinear design is realizable through a suitable scaling.

Let us define the complex variables:

γ 12--- z1 2⁄ z 1 2⁄–

–( ) 12--- esT 2⁄ e sT 2⁄–

–( ) sT2---

sinh= = =

µ 12--- z1 2⁄ z 1 2⁄–

+( ) 12--- esT 2⁄ e sT 2⁄–

+( ) sT2---

cosh= = =


They are related by the relationships:

Note: the γ plane is the LDI plane and the λ plane is the bilinear plane (2/Tnormalized to 1)

To implement an exact LD equivalent s should be replaced by γ

To implement an exact bilinear equivalent s should be replaced by λ

Unfortunately, SC circuits having transfer function of the form 1/λ can not be realized in stray-insensitive form

Solution: suitable scaling of the ladder network (or equivalently the flow diagram): if we divide all impedance of a network by the same scaling factor, the transfer function remains unchanged

λ z 1–z 1+------------ z1 2⁄ z 1 2⁄–

–

z1 2⁄ z 1 2⁄–+

------------------------------- sT2---

tanh= = =

λ γ µ⁄= µ2 1 γ2+= z1 2⁄ µ γ+=


Scaling of bilinear elements by µ:

Scaling changes:

• A resistor into a frequency dependent element

• A bilinear capacitor into an LD capacitor

• A bilinear inductance into parallel of L - LD inductance with a 1/L

- LD capacitor

RRµ----→

1λC------- 1

µλC-----------→ 1

γC-------=

λLλLµ------→ λµL

µ2---------- γL

1 γ2+

--------------- 11γL------ γ

L---+

----------------= = =


Consider a 5th order elliptic filter (bilinear)

After scaling by µ

Vin

RS

1/λC1 1/λC3 1/λC5

RL

Vout

1/λC2 1/λC4

λL2 λL4

Vin

RS/µ

1/λC1 1/λC3 1/λC5

λ/L2 λ/L4

RL/µ

Vout

1/λC2 1/λC4

L2 /γ L4 /γ


After the elimination of the bridging capacitors

Vin

RS

1/γC’1 1/γC’3 1/γC’5

RL

VoutγL2 γL4/µ

/µ

V3α1 V3α4V1+α2V5α3

C1, C1 C2 1 L2⁄+ +=

C3, C2 C3 C4 1 L2 1 L4⁄+⁄+ + +=

C5, C4 C5 1 L4⁄+ +=

α1 C2 1 L2⁄+( ) C1 C2 1 L2⁄+ +( )⁄= α3 C4 1 L4⁄+( ) C3 C4 1 L4⁄+ +( )⁄=

α2 C2 1 L2⁄+( ) C3 C2 1 L2⁄+ +( )⁄= α3 C4 1 L4⁄+( ) C5 C4 1 L4⁄+ +( )⁄=


The network is the same as an LD equivalent ladder filter with the ex-ception of the frequency dependent terminations

γC1 V1 α1V3–( ) µRs------ Vin V1–( ) I2–=

γC5 V5 α4V3–( ) I4µ

RL-------– V5=

V1

µRs------Vin γ C2

1L2------+

V3 I2–+

γC1µ

Rs------+

--------------------------------------------------------------------=

V5

I4 γ C41L4------+

V3+

γC5µ

RL-------+

----------------------------------------------=


After the dimensional scaling by R, (βs = R/Rs, βe = R/RL)

If we remember the z-transfer function of the dumped integrator

V1

βsµVin γτ2V3 V2–+

γτ1 βsµ+-----------------------------------------------------=

V5

V4 γτ4V3+

γτ3 βeµ+-----------------------------=

+

_

C2C1

C3


The denominators can be realizedThe only design problem come from the input βs µ Vin

It is necessary to inject two samples per period TSimple solution (stray sensitive)

HDI z( )C1z 1 2⁄–

C2 z1 2⁄ z 1 2⁄––( ) C3z1 2⁄

+---------------------------------------------------------------------

C1 µ γ–( )2C2γ C3 γ µ+( )+---------------------------------------------

C1 µ γ–( )2C2 C3+( )γ C3µ+

-------------------------------------------------= = =

µVin12--- z1 2⁄ z 1 2⁄–

–( )Vin=

Φ1 Φ2

F1Φ2Φ2

Φ1

C/2

C/2


Stray insensitive solution:

Use of a S/H:

Φ1

Φ2Φ2Φ1

C/2

C

Φ2

Φ1

Φ2Φ2Φ1

C/2

Φ1

Φ2

C/2

Φ1Φ2

_

+


SWITCHED CAPACITOR N-PATH FILTERS Narrow-band (high Q) filters can not be realized with conventional

design techniques

Required gain A0 ≈ 200 Qmax; Qpole ≈ (ω0 + B/2)/2|σ|

Sensitivities to finite gain and capacitance variation proportional to Qmax

σ

jω

××

×

××

×

××


Solution with N-path circuits; are a number of identical low pass filters multiplexed at the input and the output

Sampling period of the input signal: T; sampling period in each LP filter: NT

Φ1

Φ2

Φ1

Φ2

LP Φ1

LP

ΦNLP ΦN

Φ2

ΦN

Φ3

2

1

0

1

2

_

_


In the z-domain

Vini t( ) Vin t( )δ t nT– iT–( )

n ∞–=

+∞

∑=

Vin NP, t( ) Vini t( )

i 1=

N

∑=

VoutNP t( ) Vouti t( )

i 1=

N

∑=

NP z( )Vout,NP z( )Vin NP, z( )----------------------------

Vini z( )HLP z( )

i 1=

N

∑

Vini z( )

i 1=

N

∑---------------------------------------------= =

HNP z( ) HLP z( )=


The z-transfer function of the N-path and the one of the low pass arethe same, but the sampling frequencies are one N times the other

The N-path filter realizes the transformation

In the transfer function of the low pass filter.

The gain requirement and the sensitivities are the one posed by the low-pass filter specifications

Implementation:

First order prototype:

zLP es NT( ) e( sT )N

zN= = =

z zN→

+

_

C2

C1

C


Parallel implementation:

Note that the op-amp work onlyduring a small period. They canbe multiplexed.

+

-

C2

C1

C

+

-

C2

C1

C

+

-

C2

C1

C

1

2

N N

2

1

Φ1

Φ2

ΦN

Φ3

+

-Φ1

Φ2

C2

AAAA

ΦΝ

Φ

Φ

C(1)

C(2)

C(N)

Φ2

Φ3

Φ1

Φ


In order to have same LP transfer function all the integrating capaci-tors C(1), C(2), ..., C(n) must be matched. This requirement is over-came with the analog RAM-type scheme.

+

_

Φ1

C2

AAAA

ΦΝ

Φ

Φ

C

C

C

Φ'1

Φ

Φ1'

ΦΝ'

ΦΦ

Φ'1

Φ'2

Φ'2

Analog RAM


Or better:

Problem:Clock feedthrough noise appears at 1/TSolutions:

• Pseudo N-path with circulating memory

• Use of high-pass prototype and z –>z-N transformations

+

_Φ

C

ΦΦ

Φ

Φ Φ+

Φ

Φ

C

C

ΦN

Φ2

Φ3

Φ1

Φ

Φ2

Φ1

Analog RAM

C

C2

C1


FINITE GAIN AND BANDWIDTH EFFECT

If the op-amp has finite gain A0 the “virtual ground” voltage is V0/A0

z-transforming:

+

_

C2

C1

C2V0 n 1+( ) 1 1A0------+

C2V0 n( ) 1 1A0------+

C1 Vin n 1+( )V0 n 1+( )

A0-------------------------+–=

H z( )Vo z( )Vin z( )----------------

C1z

C2 1 1A0------+

z 1–( )C1

A0-------z+

----------------------------------------------------------------–= =


Comparing H(z) with the transfer function with

Substituting z = esT, on the imaginary axis

Magnitude error

Phase error

A0 ∞→

Hid z( )C1z

C2 z 1–( )------------------------–=

H z( )Hid z( )

1 1A0-------+

C1

C2A0--------------- z

z 1–------------+

----------------------------------------------------------Hid z( )

1 1A0-------+

C1

C2A0--------------- 1

z 1–------------ 1

2--- 1

2---+ +

+

-----------------------------------------------------------------------------------Hid z( )

1 1A0------- 1

2---

C1C2A0---------------+ +

C1

2C2A0-------------------z 1+

z 1–------------+

----------------------------------------------------------------------------------------= = =

H ejωT( )Hid ejωT( )

1 1A0-------

C12C2A0------------------- j

C12C2A0 ωT 2⁄( )tan---------------------------------------------------–+ +

-----------------------------------------------------------------------------------------------------Hid ejωT( )

1 m ω( )– jθ ω( )–-------------------------------------------= =

m ω( ) 1A0------ 1

C12C2-----------+

–=

θ ω( )C1

2C2A0 ωT 2⁄( )tan------------------------------------------------

C1

C2A0ωT-----------------------≅=


For the noninverting integrator

z-transforming and solving

Same magnitude and phase error result

+

_

C2

C1

C2V0 n 1+( ) 1 1A0------+

C2V0 n( ) 1 1A0------+

C1 Vin n( )V0 n 1+( )

A0-------------------------++=

H z( )Vo z( )Vin z( )----------------

C1

C2 1 1A0------+

z 1–( )C1

A0-------z+

----------------------------------------------------------------= =


Effect of the finite bandwidth:

+

_

C2

+

_

C2

C1

Coutgm vi gm vi

e-t/τ1e-t/τ

time time

inpulse response inpulse response

C2 =10 C1

τ 1ω0------ τ1 τ

C1 C2+

C2--------------------= =


Since the charge is injected when the capacitor C1 is connected to the virtual ground, during this phase the output will display a considerable transient.

During the phase when C1 is disconnected a residual transient is performed by the output. This transient does not correspond to any charge transfer into C2 (off course).

If T/2 is comparable with τ1 or τ2 we have two effects:

1 Incomplete charge

transfer

2 Virtual ground voltage

shift, which totally (in real

situations) disappears

during the successive

half clock period

Vout

timeAA

F1 F2

value before thechargeinjection

immediately after the closure of the switch

the virtual ground is not settled

error due to theincorrect charge transfer

ideal response

AA

Virtualgroundvoltage


• If we sample the output during Φ2 we have only a magnitude

error

• If we sample the output during Φ1 we have an additional voltage

error that will be “forgotten”. It corresponds to a phase error

For inverting and non inverting integrators:

+

_

C2

C1

Φ2Φ1

Φ2Φ1 Φ2

m ω( ) e

C2C1 C2+---------------------ω0T 2⁄–

1C2

C1 C2+-------------------- ωTcos–=

θ ω( ) e

C2C1 C2+---------------------ω0T 2⁄–

ωTsin=


Reduction of the finite gain effect:

The effect of the finite gain can be reduced with techniques based on principles that similar to the autozero used in comparators.

The virtual ground voltage must be sampled and held without changing the output voltage.

+

_

C2

C1

Φ2Φ1

Φ2 Φ1Φ2

m ω( ) 1C2

C1 C2+--------------------–

e

C2C1 C2+---------------------ω0T 2⁄–

=

θ ω( ) 0≅


During the S/H of the virtual ground voltage the integrating capacitor must be disconnected in order to preserve its stored charge.

A simple unity gain closed loop connection destroys the output dependent virtual ground voltage.

A slave capacitor Cs previously charged to the output voltage helps in solving the problem

+

_

C2

Φ2

Φ1

Φ1

Φ1

Φ2

+

_

C2

Φ2

Φ1

Φ1

Φ1

Cs


The output voltage changesonly of the global offset (if Cs isnot required to integrate chargeduring Φ2)

Three solutions:

Cs is required to discharge the injecting capacitor C1 to the global input offset.

Cs is required to discharge an extra-capacitor C2, which, during Φ1 acts as a battery, creating a virtual ground at the node N.

+

_

C2

Φ2

Φ1

Φ1

Φ1

Cs

Φ1 Φ2

C1

+

_

CI

Φ 1

Φ1

Φ1

C1

Φ2 Φ2

C2

Φ2

Φ1

N

Cs


The slave capacitor Cs is precharged at (Vout-Vin). During Φ2 if C1 = Cs the charge redistribution between C1 and Cs is such that Vout does not change.

Notes:

• The parasitic capacitance of the node A acts as a toggle SC

which inject charge into the small Cs during Φ2.

• Only inverting integrator

+

_

C2

Φ1

Φ1

Cs

Φ1

Φ2

C1

Φ1

Φ2

A


• Magnitude error is reflected into a frequency error

• Phase error is reflected into a Q error

Same circuit solutions can be applied do SC amplifiers andconverters.

Circuit Magnitude error Phase error

#1 ++ =

#2 = +

#3 = ++


FULLY DIFFERENTIAL CIRCUITS

Fully differential configurations reduce the clock feedthrough noise and increase the dynamic range.

They allow an increase design flexibility

Simple integrator (inverting and non inverting)

+

_

C2

C1

Φ1

Φ2Φ2

Φ1Φ2

(Φ2)

(Φ1)


Immediate sampling (inverting and non inverting) integrator:

Delayed sampling (inverting and non inverting) integrator:

Φ1

+

_

Φ1Φ2Φ2

Φ1Φ1Φ2Φ2

Vin

-Vin

-Vin

Vin

Φ1

Φ1

Φ1

+

_

Φ1Φ2Φ2

Φ1Φ1Φ2Φ2

Vin

-Vin

-Vin

VinΦ2

Φ2


It is possible to reduce the op-amp finite bandwidth dependence by the use of delayed sampling inverting and non inverting integrators along a second order loop.

Φ1

+

Φ1Φ2Φ2

Φ1Φ1Φ2Φ2

Φ2 Φ2

Φ2Φ2

Φ1 Φ1

Φ1 Φ1

+_

_


The peaking in the frequency response due to the phase error is strongly reduced

It is easy to realize bilinear integrators

Φ1

+

Φ1

Φ2

Φ1

Φ1 Φ2

Vin

Vin

Φ2

Φ2

C2C1

C2

C1

_

_


LAYOUT CONSIDERATIONS IN SC CIRCUITSA SC circuit is the interconnection of

• Op-amp

• Switches

• Capacitors

We have different lines of interconnections:• Signal

• Bias

• Clock

General rules:• Separate as far as possible, clock lines and signal lines

• Top plate of capacitors connected to virtual ground

• Maximum area switch and, when possible, only one transistor to

realize the switch (minimum clock feedthrough)


FLOOR PLANING FOR SINGLE ENDED CIRCUITS

Choose the dimension of the capacitor’s array in order to fit the op-amps dimension

Input and output of the op-amps in the proper position

CLOCKS

SWITCHES

CAPACITORS

SIGNAL + BIAS

OP-AMPS

BIAS

AN

AL

OG

DIG

ITA

L


FLOOR PLANING FOR DIFFERENTIAL CIRCUITS

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CLOCKS

SWITCHES

CAPACITORS

SIGNAL + BIAS

OP-AMPS

AN

AL

OG

DIG

ITA

L

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CLOCKS

SWITCHES

CAPACITORS


SWITCHES LAYOUT

CAPACITOR LAYOUT Use parallel connection of

unity capacitors

The residual capacitance must have the same perimeter/area ratio as the unity capacitors

Common centroid only if is effectively necessary

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NOISE IN SC CIRCUITSThe noise sources in a SC network are:

• Clock feedthrough noise

• Noise coupled from power supply lines and substrate

• kT/C noise

• Noise generators of the op-amp

The first two sources are the same as in mixed analog-digital circuits.

kT/C noise:

Consider the simple network:

In the “on” state the switch can bemodeled with a noisy resitor

vin

CS1


Noise equivalent circuit:

The white spectrum of the “on” resistance is shaped by the low passaction of the RonC filter.The noise voltage across the capacitor C has spectrum:

4kTR fCS1

on

R on

Sn,c vn c,2 4kTRon H f( ) 2∆f

4kTRon∆f

1 2πfRonC( )2+

-----------------------------------------= = =


When the switch is turned “off” the noise voltage vn,c is sampled andheld onto C

The folding of the spectrum in band-base gives a white spectrum.AAAAA

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f

S

fAAAAAAAAAAAA

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f CK/2

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It power (the dashed area) is equal to the integral of Sn,c

Procedure for the noise calculation in SC networks:

Assume all the noise sources uncorrelated

Neglect the direct coupling input-output

Consider, in the sampled-data domain, the contribution to the output of each noise source (SC structures + op-amps)

Superpose quadratically all the contributions

vn c,2 4kTRon∆f

1 2πfRonC( )2+

-----------------------------------------0

∞

∫ df4kT2πC----------- xatan( )0

∞ kTC-------= = =


Low-frequency noise reduction techniques:

Chopper-stabilization technique

Correlated double sampling

A 1

continuous time and switched capacitor...

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