cad for nano cmos analog design

8/14/2019 CAD for Nano CMOS Analog Design

1/42

CAD for Nano CMOS

Analog DesignSoumya Pandit

Institute of Radio Physics and Electronics

University of Calcutta

Contact: [email protected]


2/42

02.06.09 2

Outline Introduction

Design Complexity: Design Productivity Gap

Silicon Complexity: Nano CMOS Challenges

Frontiers of Analog CAD Researches Performance modeling techniques

Analog circuit synthesis

Topology design

Conclusion


3/42

02.06.09 3

Growth of Electronics

Evolution of the cost of a single

transistor [Source: Intel]

Evolution of transistor sizes and

number/die [Source: Intel]


4/42

02.06.09 4

Design Complexity [ITRS-01,03,07

] Increasing number of functionality: SOC

Processors Memory

Logic Analog

New signal processing algorithms and system architectures.

Larger design team: often requires different kind of expertknowledge

Silicon complexity: Nano CMOS challenges


5/42

Analog Components Inputs of a system: Sensing circuits, signal conditioning/

Outputs of a system: Receiving circuits.

Data Converters.

Time/Frequency Synchronizers.

High-performance digital circuits

02.06.09 5


6/42

02.06.09 6

Time-to-market Time required to get a product from the concept to the

marketplace.


7/42

02.06.09 7

Design Gap

Cost of design is the greatest threat to continuation of semiconductor roadmap

[ITRS2007]


8/42

02.06.09 8

Silicon Complexity [ITRS 2007

] Refers to the impact of process scaling and the introduction

of new materials or device/interconnect architectures.

Non-ideal scaling of device parasitics and supply/threshold

voltages. Coupled high-frequency devices and interconnects.

Process variability.

Manufacturing variability.

Decreased reliability.


9/42

02.06.09 9

Design Technology Includes conception, implementation and validation of

microelectronics-based systems.

Elements of DT includes

Tools: EDA tools Libraries: Standard cells, reusability

Process characterization

Structured methodologies

The role of DT is to enable profits and growth of thesemiconductor industry via cost-effective production of

designs that fully exploit manufacturing capability.


10/42

02.06.09 10

EDA A CAD resource is a sophisticated, computerized workstationand software used to design IC chips. CAD tools

CAD methodologies

Reduce design time and manage design complexity

In digital VLSI circuit design, EDA tools are enoughmatured. Fully automated process from behavioral description to tape out.

Lack of robust analog CAD tools SPICE circuit simulator

Layout editing environments


11/42

02.06.09 11

Design Effort


12/42

02.06.09 12

Conventional AMS Design flowElectrical Synthesis

Physical Synthesis

Verification

Fabrication

Testing

Schematic

Layout

Chip

Specifications

Yield/Process data

Feedback


13/42

02.06.09 13

Top-Down AMS Design [IEEE.Proc 2000

]

Cell Layout

System Layout

Simulation Verification


ForwardProgress

BacktrackingandRedesign

System Design

Cell Design



Architectural Design Simulation Verification

System Concept

FabricationTesting


14/42

02.06.09 14

Hierarchical Analog Design

Level i

Topology Selection

SpecificationTranslation

Verification

Level i + 1

Verification

Extraction

Layout Generation

Redesign

Specifications at level i Layout at level i

Specifications at level i + 1 Layout at level i + 1


15/42

02.06.09 15

Illustration Gain

A1

Gain

-1

S1

S2

D

C

EN

B

Analog Switch

TransferFcn

Gain

A2

Clock

VxVout

Functional Description (SFG) of the System

OTA

Voltage

Amplifier

Gm1,Gm2

OTAInverter

Gm3,

Gm4

OTAFilterGm5,

Gm6, CL

OTA

Voltage

Amplifier

Gm7,Gm8

CMOSSwitch

Optimal High-level Topology of the System

High Level TopologyGeneration /Selection

Behavioral

Verification

High-Level Specification Translation

Specification parameters (voltage gain, bandwidth , output impedance etc )

of all synthesizable component -blocks (voltage amplifier , inverter, filter)

Clock

System Specs

Vx

Vout


16/42

02.06.0916

Optimization-based Strategy

No

New values ofthe designvariables

Designspecifications

OK ?

Solution

Yes

OptimizationAlgorithm

Equation-based

Simulation-based

Initialize designvariables

Performanceevaluation

Cost functioncomputation


17/42

02.06.0917

Hierarchical Modeling(IEEE Proc.2007)

In any hierarchical approach behavioral models/performancemodels are the bridge between different level in the hierarchy,

both top-down and/or bottom-up.

A model is a conceptual representation of a system that youwant to realize (specification model) or that you have realized(implementation model).

Characteristics of good model Reasonable accuracy

Fast to compute Low Construction time

Behavioral models: Simulation and Verification.

Parameterized Models: Synthesis and Optimization


18/42

02.06.0918

Illustration


19/42

02.06.0919

Utility in Hierarchical Analog Design

Gain

A1

Gain-1

S1

S2

D

C

EN

B

Analog Switch

TransferFcn

Gain

A2

Clock

VxVout

Functional Description (SFG) of the System

OTA

Voltage

Amplifier

Gm1,Gm2

OTAInverter

Gm3,

Gm4

OTAFilter

Gm5,Gm6, CL

OTA

Voltage

Amplifier

Gm7,Gm8

CMOS

Switch

Optimal High-level Topology of the System

High Level TopologyGeneration/Selection

Behavioral

Verification

High-Level Specification Translation

Specification parameters (voltage gain, bandwidth, output impedance etc )of all synthesizable component -blocks (voltage amplifier , inverter, filter)

Clock

System Specs

Vx

Vou

t


20/42

02.06.0920

Polynomial Approximation Simplest approximation for a weakly non-linear characteristic.

Least squares error optimization


21/42

02.06.0921

Piecewise Approximation Piecewise linear approximation

Represent non-linear functions by piecewise linear segments.

Linear approximation of non-linear curve over small regions.

Dimensionality problem for multi-dimensional curves. Piecewise polynomial approximation

Approximates the non-linear function in each piecewise region by a

polynomial.

Each piecewise polynomial region is reduced using a model order

reduction technique.

Reduced models are stitched together with scalar weight functions.


22/42

02.06.0922

PWP Illustration [Roychowdhury 2003]


23/42

02.06.0923

Validation


24/42

02.06.0924

Parameterized Models Analog performances as functions of specification parameters

of the circuit.

Used for analog circuit synthesis.

Two approaches Template-based approach.

Regression-based approach


25/42

02.06.0925

Posynomial approach [Gielen 2003]


26/42

02.06.0926

Contd..


27/42

02.06.0927

Template-Free Approach


28/42

02.06.0928

CAFFEINE [McConaghy 2005,..] No requirement of a-priori from designer.

Model itself evolves as part of GP optimization process.

Model complexity and accuracy tackled by a multi-objective

optimization problem.


29/42

02.06.0929

Accuracy Complexity Trade-off


30/42

02.06.0930

LS-SVM- based Approach [Pandit 2009]


31/42

02.06.0931

Contd..


32/42

02.06.0932

Analog Circuit Sizing


33/42

02.06.0933

OPAMP Synthesis [Wolfe 2003]


34/42

02.06.0934

High-Level Sizing [Pandit PhD Thesis]


35/42

02.06.0935

Topology Design [Martens 2008] Selection before or after sizing

Set of candidate topologies.

Each topology is optimized and the best is selected.

A particular topology is selected based upon designers experience orsome tool and then the selected topology is optimized.

Selection during sizing Generic topology template-based approach

Topology parameters related to performances and the generated

topology is optimized for performances.

Top-down topology generation. Starts from functional description of the system.


36/42

02.06.0936

Selection & Sizing [Medeiro 1994]


37/42

02.06.0937

Template-based Approach [Tang 2006]

Generic Template

Selected topologies

Optimization Parameters

Power

Sensitivity

Hardware complexity


38/42

02.06.0938

Top-Down Approach [Pandit PhD Thesis]

Transfer function

model, desiredspecifications

Generation of new functionaltopology

State space model generation

Implementation style specificoptimal topology generation

Seed functional topology

Specs met ?

Behavioral simulation

Optimal component-level topology

No

Yes

Specs met in presence ofnon-idealities ?

No

Yes

Performance estimation

Continuous time

modulator system.

Generated

topology optimized

for sensitivity,

relative power

consumption and

hardware complexity.


39/42

02.06.0939

Topology Generation

1/s

f1

b2

b3

u(t) y(n)

DAC

1/s 1/s 1/s

f2 f3 f4


40/42

02.06.0940

Results


41/42

02.06.0941

Summary Analog CAD tools are essential to cope up with the increased

system design complexity and time-to-market factors.

Nano-scale CMOS design poses additional challenges onautomated analog design.

Structured hierarchical analog design is the required designmethodology.

Hierarchical modeling of analog behavior and performancesplay an important role in implementing hierarchical design

methodology. Automated analog sizing and topology generation are two

important steps of analog design automation.


42/42

42

cad for nano cmos analog design

Documents