~

0

9

4 ISBN 019511644-5

The Oxford Series in Electrical and Com puler EngineeringAdel S. Sedra Series Editor

Allen and Holberg, CMOS Analog Circuit Design, 2nd Edition Bobrow, Elementary Linear Circuit Analysis, 2nd Edi1ion Bobrow, Fundamentals of Electrical Engineering, 2nd EditionBurns and Roberts, An Introduction to Mixed-Signal/CTest and Measurement CampbeU, The Science and Engineering of Microelectronic Fabrication, 2nd Edition Chen, Analog & Digital Control System Design Chen, Linear System Theory and Design, 3rd Edition Chen, System andSig11al Analysis, 2nd Edition Chen, Digital Signal Processing Comer, Digital Logic and State Machine Design, 3rd Edition Cooper and McGillem, Probabilistic Methods of Signal and System Analysis, 3rd Edition DeCarlo and Lin, Linear Circuit Analysis, 2nd Edition Dimitrijev, Understanding Semiconductor Devices Fortney, Principles of Elef:tmnics: Analog & Digital Franco, Electric Circuits Fundamental.s Granzow, Digital Transmi,fsion Line.r Guru and Hiziroglu, Electric Machinery and Transformers, 3rd Edition Hoole and Hoole, A Modem Short Course in Engineering Electromo.gnetics Jones, Introduction to Optical Fiber Communication Systems Krein. Elements of Power Electronics Kuo, Digital Control Systems, 3rd Edition Lathl, Modern Digital and Aru~log Communications Systems, Jrd Edition Lathi, Signal Processing and Linear Systems Lathl, Linear Systems and Sigru~ls Martin, Digital integrated Circuit Design McGillem and Cooper, Continuous and Discrete Signal and System Analysis, 3rd Edition Miner, Lines and Elecrromagnetic Fields for Engineers Parhami, Computer Arithmetic Roberts and Sedra, SPICE. 2nd Edition Roulston, An Introduction to the Physics of Semiconduc:tor Devices Sadiku, Elements ofElectroma1fnetics, 3rd Edition Santina, Stubberud, and Hostetter, Digital Control System Design, 2nd Edition Sarma, Introduction to Electrical Engineering Schaumann and Van Valkenburg, Design ofAnalog Filters Schwarz, Elec:tmmagnetics for Engineers Schwarz and Oldham, ElectricCil Engineering: An Introduction, 2nd Edition Sedra and Smith, Microelectronic Circuits, 4th Edition Stefani, Savant, Shahian, and Hostetter, Design of Feedback Conrrol Systems, 4th E.dition VanValkenburg, Analog Filter Design Warner and Grung, Semiconductor Device li:lectronics Warner and Grung, MOSFET Theory and Design Wolovich,Automo.ric Control Systems Yariv, Optical Electronics in Modem Communications. 5th Edition

CMOS Analog C~rcuit Des~gnSecond Edition

Phillip E. AllenGeorgia Institute of Technology

Douglas R. HolbergCygnal Integrated Products, Inc.

New York Oxford OXFORD UNIVERSITY PRESS

2002

tontentsPreface xiii Chapter 1 Introduction and Background 11.11.2 1.3Analog Integrated-Circuit Design Analog Signal Processing 9 10 1 6 Notation, Symbology, and Terminology

1.4

Example of Analog VLSl Mixed-Signal Circuit Design

1.5

Summary 15Problems References

1617

Chapter 2 CHOS Technologq 182.1 UBasic MOS Semiconductor Fabrication ProcessesTtte pn Junction 29

19

2.3 H 2.5 2.6 a.7

The MOS TransistorPassive Components

36 43 48

Other Considerations of CMOS Technology Integrated Circuit Layout 55Summary 66

Problems References

68 70

viti

CONTENTS

''

..73

Cbnpter 3 CMOS Device Hodeling 723.13.2 3.3 3.4U USimple MOS Large-Signal Model (SPICE LEVEL I) Other MOS Large-Signal Model Parameters Small-Signal Model for the MOS Transistor Computer Simulation Models Subthreshold MOS Model Summary Problems References 109 92

7987

97 99

SPICE Simulation of MOS Circuits

3.7

110112

Chapter 4 Rnalog CMOS Sub circuits 1134.1 4.2 4.3MOS Switch

113

MOS Diode/Active Resistor Current Sinks and Sources Current Mirrors 134

124126 143

u

4.S

Current and Voltage References Bandgap Reference Summary Problems References 153

u4.7

159159 166

Chapter 5 CMOS Amplifiers 167S.l S.2 5.3 5.4 S.S 5.&Inverters 168 1 BO 199 211 218 229 Differential Amplifiers Cascade Amplifiers Current Amplifiers Output Amplifiers

High-Gain Amplifier Architectures

Contents

1x

S.7

Summary

232 233 242

Problems References

Chapter G CMOS Operational Amplifiers 2436.1 &.2 G.3 6.4 6.6 6.7G.BDesign of CMOS Op Amps Compensation of Op Amps 244 253 269 286

Design of Two-Stage Op Amps

Power-Supply Rejection Ratio of Two-Stage Op Amps Simulation and Measurement of Op Amps Macromodels for Op AmpsSummary 310

&.S Cascade Op Amps 293323

341 342

Problems

References 349

Chapter 7 High-Performance CMOS Op Hmps 3517.1 7.2 7.3 7.4 7.5 7.6 7.7Buffered Op Amps 352 368 384 High-Speed/Frequency Op AmpsDifferential-Output Op Amps

Micropower Op Amps Low-Noise Op Amps Low-Voltage Op AmpsSummary

393 402 415

432 437

Problems 433 References

Chapter 8 Comparators 4398.1 8.2Characterization of a Comparator 439 1\vo-Stage, Open-Loop Comparators 445

x

CONTENTS

8.3 8.1 8.5 8.6 8.7

Other Open-Loop Comparators Discrete-Time Comparators High-Speed Comparators Summary Problems References

461 464

Improving the Performance of Open-Loop Comparators 475 483

488488 491

Chapter 9 Switched Capacitor Circuits 4929.1 9.2USwitched Capacitor Circuits 493 507 520 532 544 Switched Capacitor Amplifiers Switched Capacitor Integrators

9.49.5

.z-Domain Models of Two-Phase Switched Capacitor Circuits First-Order Switched Capacitor Circuits Switched Capacitor Filters Summary Problems References 600 600 611 561

9.69.7 9.8

Second-Order Switched Capacitor Circuits 550

Chapter 10 Digital-Analog and Analog-Digital Converters 6121~.1 Introduction and Characterization of Digital-Analog Converters

613 635 652

10.2

Parallel Digital-Analog Converters Serial Digital-Analog Converters Serial Analog-Digital Converters

623 647665

lU10.4 10.5 10.6 10.7JU.!

Extending the Resolution of Parallel Digital-Analog Converters Introduction and Characterization of Analog-Digital Converters Medium-Speed Analog-Digital Converters Oversampling Converters 698 667

1~.8 High-Speed Analog-Digital Converters

682

Contents

xl

10.10

Summary Problems References

713 715 729 733

HppendiX A HppendiX 8 HppendiX C Index

Circuit Analysis for Analog Circuit Design CMOS Device Characterization 744 Time and Frequency Domain Relationships for Second-Order Systems 768

777

PREFACE

The objective of the second edition of this book continues to be to teach the design of CMOS analog circuits. The teaching of design reaches far beyond giving examples of circuits and showing analysis methods. It includes the necessary fundamentals and background but must apply them in a hierarchical manner that the novice can understand. Probably of most importance is to teach the concepts of designing analog integrated circuits in the context of CMOS technology. These concept.~ enable the reader to understand the operation of an analog CMOS circuit and to know how to change its performance. With today's computer-oriented thinking, it is vital to maintain personal control of a design, to know what to expect, and to discern when simulation results may be misleading. As integrated circuits become more complex, it is crucial to know "how the circuit works." Simulating a circuit without the understanding of bow it works can lead to disastrous results. How does the reader acquire the knowledge of how a circuit works? The answer to this question bas been the driving motivation of the second edition of this text. There are several important steps in this process. The first is to learn to analyze the circuit. This analysis should produce simple results that can be understood and reapplied in different circumStances. The second is to view analog integrated circuit design from a hierarchical viewpoint. This means that the designer is able to visualize how subcircuits are used to form circuits, how simple circuits are used to build complex circuits, and so forth. The third step is to set forth procedures that will help the new designer come up with working designs. This has resulted in the inclusion of many "design recipes," which became popular with the first edition and have been expanded in the second edition. It is important that the designer realize that there are simply three outputs of the electrical design of CMOS analog circuits. They are ( 1) a schematic of the circuit. (2) de currents, and (3) WIL ratios. Most design ftows or ''recipes" can be organized around these three outputs very easily. Fifteen years ago, it was not clear what importance CMOS technology would have on analog circuits. However. it has become very clear that CMOS technology has become the technology of choice for analog circuit design in a mixed-signal environment. This "choice" is not necessarily that of the designer but of industry trends that want to use standard technologies to implement analog circuits along with digital circuits. As a result, the first edition of CMOS Analog Circuit Design fulfilled a need for a text in this area before there were any other texts on this subject. It has found extensive use in industry and has been used in classrooms all over the world. Like the first edition, the second edition has also chosen not to in elude BIT technology. The wisdom of this choice will be seen as the years progress. The second edition has been developed with the goal of extending the strengths of the first edition, namely in the area of analog circuit design insight and concept'!.xlll

lilY

PREFACEThe second edition has been a long time in coming but has resulted in a unique blending of industry and academia. This blending ba~ occurred over the past 15 years in short courses taught by the first author. Over 50 shon courses have been taught from the first edition to over 1500 engineers aU over the world. In these short courses, the engineers demanded to understand the concepts and insight to designing analog CMOS circuits, and much of the response to these demands ha~ been included in the second edition. In addition to the industrial input to the second edition. the authors have taught this material at Georgia Institute of Technology and the University of Texa.~ at Austin over the past 10-15 year.;. This experience ha.~ provided insight that has been included in the second edition from the viewpoint of students and their questions. Also. the academic application of this material has resulted in a large body of problem.~ that have been given as test.~ and have now been included in the second edition. The first edition had 335 problems. The second edition has over 500 problems, and most of those are new to the second edition. The audience for the second edition is essentially the same as for the first edition. The first edition was very useful to those beginning a career in CMOS analog design-many of whom have communicated to the authors that the text has been a ready reference in their daily work. The second edition should continue to be of value to both new and experienced engineers in industry. The principles and concepts discussed should never become outdated even though technology changes. The second audience is the classroom. The output of qualified students to enter the field of analog CMOS design has not met the demand from industry. Our hope is that the second edition will provide both instructors and students with a tool that will help fulfi II this demand. In order to help facilitate this objective, both authors maintain websites lhal pennit the downloading of short course lecture slides, short course schedules and dates, class notes, and problems and solutions in pdf format. More information can be found at www.aicdesign.org (P.E. Allen) and www.holberg.org (D.R. Holberg). These Nites are continually updated, and the reader or instructor is invited to mak.e use of the information and teaching aides contained on these sites. The second edition has received extensive changes. These changes include the moving of Chapter 4 of the first edition to Appendix B of the second edition. The comparator chapter of the first edition was before the op amp chapters and has been moved to after the op amp chapters. In the 15 years since th-e first edition, the comparator has become more like a sense amplifier and less like an op amp without compensation. A DUljor change has been the incorporation of Chapter 9 on switched capacitor circuits. There are two reasons for this. Switched capacitors are very important in analog circuits and systems design, and this information is needed for many of the analog-digital and digital-analog converters of Chapter 10. Chapter 11 of the first edition has been dropped. There were plans to replace it with a chapter on analog systems including phase-locked loops and VCOs, but time did not allow this to be realized. The problems of the second edition are organized into sections and have been designed to reinforce and extend the concepts and principles associated with a particular topic. The bierachical organization of tile second edition is illustrated in Table 1.1-2. Chapter l presents the material necessary to introduce CMOS analog circuit design. This chapter gives an overview of the subject of CMOS analog circuit design, defines notation and convention, mak~ a brief survey of analog signal processing, and gives an example of analog CMOS design with emphasis on the hierarchial aspect of the design. Chapters 2 and 3 form the basis for analog CMOS design by covering the subjects of CMOS technology and modeling. Chapter 2 reviews CMOS technology as applied to MOS devices, pn junctions. passive components compatible with CMOS technology, and other component.~ such ali the lateral and substrate

Preface

xv

:,,. ' .

BJT and latchup. This chapter also includes a section on the impact of integrated circuit layout. This portion of the text shows that the physical design of the integrated circuit is as important as the electrical design, and many good electrical designs can be ruined by poor physical design or layout. Chapter 3 introduces the key subject of modeling, which is used throughout the remainder of the text to predict the performance of CMOS circuits. The focus of this chapter is to introduce a model that is good enough to predict the perfonnance of a CMOS circuit to within ::t10% to 20% and will allow the designer insight and understanding. Computer simulation can be used to more exactly model the circuits but will not give any direct insight or understanding of the circuit. The models in this chapter include the MOSFET large-signal and small-signal models, including frequency dependence. In addition, how to model the noise and temperature dependence of MOSFETs and compatible passive elements is shown. This chapter also discusses computer simulation models. This topic is far too complex for the scope of this book, but some of the basic ideas are presented so that the reader can appreciate computer simulation models. Other models for the subthreshold operation are presented along with how to use SPICE for computer simulation of MOSFET circuits. Chapters 4 and 5 represent the topics of subcircuits and amplifiers that will be used to design more complex analog circuits, such as an op amp. Chapter 4 covers the use of the MOSFET as a switch followed by the MOS diode or active resistor. The key subcircuiL~ of current sinks/sources and current mirrors are presented next. The.o;e subcircuits permit the illustration of important design concepts such as negative feedback, design tradeotfs, and matching principles. Finally, this chapter presents independent voltage and current references and the bandgap voltage reference. These references attempt to provide a voltage or current that is independent of power supply and temperature. Chapter 5 develops various rypes of amplilien;. These amplifiers are characterized from their large-signal and small-signal performance, including noise Wid bandwidth where appropriate. The categories of amplifiers include the inverter, differential. cascode. current, and output amplifiers. The last section discusses how high-gain amplifien; could be implemented from the amplifier blocks of this chapter. Chapters 6, 7, and 8 represent examples of complex analog circuits. Chapter 6 introduces the design of a simple two-stage op amp. This op amp is used to develop the principles of compensation necessary for the op amp to- be u.o;eful. The two-stage op amp is used to formally present methods of designing this type of analog circuit. This chapter also examine., the design of the cascode op amps. particularly the folded-cascode op amp. This chapter concludes with a discussion of techniques to measure and/or simulate op amps and macromodels. Macromodels can be used to more efficiently simulate op amps at higher levels of abstraction. Chapter 7 presents the subject of high-performance op amps. In this chapter various performances of the simple op amp are optimized, quite often at the expense of other performance aspects. The topics include buffered output op amps, high-frequency op amps, differentialoutput op amps, low-power op amps, low-noise op amps, and low-voltage op amps. Chapter 8 presents the open-loop comparator, which is an op amp without compensation. This is followed by methods of designing this type of comparator for linear or slewing responses. Methods of improving the performance of open-loop comparators, including autozeroing and hysteresis, are presented. Finally, this chapter describes regenerative comparators and how they can be combined with low-gain, high-speed amplifiers to achieve comparators with a very short propagation time delay. Chapters 9 and 10 focus on analog systems. Chapter 9 is completely new and pre.or, or rms valoe of the signal

Lowercase UppercaseLoowercasc:

UppercaseUppercase Lowercase

a..q. Q.

.,.

Upperctie

Lowerc8Stl

Figure 1.2-1 shows how the definitions in Table 1.2-1 would be applied to a periodic signal superimposed upon a de value. This notation will be of help when modeling the devices. For example, consider the portion of the MOS model that relates the drain-source current to the various terminal voltages. This model will be developed in tenns of the total instantaneous variables (in). For bia.~ing purposes, the de variables (JIJ) will be used; for small-signal analysis, the ac variables (id) will be used; and finally, the small-signal frequency discussion will use the complex variable (/d). The second item to be discussed here is what symbols are used for the various components. (Most of these symbols will already be familiar to the reader. However, inconsistencies exist about the MOS symbol shown in Fig. 1.2-2.) The symbols shown in Figs. 1.2-2(a) and 1.2-2(b) are used for enhancement-mode MOS transistors when the substrate or bulk (8) is connected to the appropriate supply. Most often, the appropriate supply is the most positive one for p-channel transistors and the most negative one for n-channel transistors. Although the transistor operation will be explained later, the terminals are called drain (D), gate (G), and source (S). If the bulk is not connected to the appropriate supply, then the symbols shown in Figs. J.2-2(c) and 1.2-2(d) are used for the enhancement-mode MOS transistors. It will be important to know where the bulk of the MOS transistor is connected when it is used in circuits. Figure 1.2-3 shows another set of symbols that should be defined. Figure 1.2-3(a) represents a differential-input operational amplifier or, in some instances, a comparator, which may bave a gain approaching that of the operation.al amplifier. Figures 1.2-3(b) and 1.2-3(c) represent an independent voltage and current source. respectively. Sometimes, the battery symbol is used instead of Fig. 1.2-3(b). Finally, Figs. 1.2-3(d) through 1.2-3(g) represent the four types of ideal controlled sources. Figure L.2-3(d) is a voltage-controlled voltage source (VCVS), Fig. 1.2-3(e) is a voltage-controlled current source (VCCS), Fig. 1.2-3(f) is a current-controlled voltage source (CCVS}, and Fig. 1.2-3(g) is a current-controlled current source (CCCS). The gains of each of these controlled sources are given by the symbols Aw Gm, R,, and A 1 (for the VCVS, VCCS, CCVS. and CCCS, respectively).Figure 1.1-1 Notation for signals.

I

8

INTRODUCTION AND BACKGROUND

FiKUJ'I! 1.2-1 MOS device symbols. (a) Enhancement n-channel transistor with bulk connected to most negative supply. {b) Enhancement p-channel transistor with bulk connected to most positive sup-ply. (c), (d) Same as (a) and (b) except bulk connection is not constrained tn respective supply.

(ll)0

(cl

+

(d)

vo~---c(e)

/2

~l'E :J~L(0

(&I

Figure l.l-3 (a) Symbol for an operational amplifier. (b) Independent voltage source. (c) Jndependent current source. (d) Voltagecontrolled voltage source (VCVS). (e) Voltage-controlled current source (VCCS). (f) Currentcontrolled voltage sow-ce (CCVS). (g) CUJ'I"Cnt-controlled current source (CCCS).

1.3

Analog Signal Processing

9

U RNRLOG SIGNRL PROCESSINGBefore beginning an in-depth study of analog circuit design. it is worthwhile to consider the application of such circuits. The general subject of analog signal processing includes most of the circuits and systems that will be presented in this text. Figure 1.3-1 shows a simple block diagram of a typical signal-processing system. In the past, such a signal-processing system required multiple integrated circuits with considerable additional passive components. However, the advent of analog sampled-data techniques and MOS technology has made viable the design of a general !iignal processor using both analog and digital techniques on a single integrated circuit [2]. The first step in the design of an analog signal-processing system is to examine the spec, ifications and decide what part of the system should be analog and what part should be digital. In most cases, the input signal is analog. It could be a speech signal, a sensor output, a radar return, and so forth. The first block of Fig. 1.3-1 is a preprocessing block. Typically, this block will consist of filters, an automatic-gain-control circuit. and an analog-to-digital converter (ADC or A/D). Often. very strict speed and accuracy requirements are placed on the components in this block. The next block of the analog signal processor is a digital signal processor. The advantages of performing signal processing in the digital domain are numerous. One advantage is due to the fact that digital circuitry is easily implemented in tbe smallest geometry processes available, providing a cost and speed advantage. Another advantage relates to the additional degrees of freedom available in digital signal processing (e.g., linear-phase filters). Additional advantages lie in the ability to easily program digital devices. Finally. it may be necessary to have an analog output. In tbis case, a postprocessing block is necessary. It will typically contain a digital-to..analog convener (DAC or DlA). amplification, and filtering. In a signal-processing system, one important system consideration is the bandwidth of the signal to be processed. A graph of the operating frequency of a variety of signals is given in Fig. 1.3-2. At the low end are seismic signals, which do not extend much below t Hz because of the absorption characteristics of the earth. At the other extreme are microwave signals. These are not used much above 30 GHz because of the difficulties in performing even the simplest forms of signal processing at higher frequencies. To address any particular application area illustrated in Fig I .3-2 a technology that can support the required signal bandwidth must be used. Figure 1.3-3 illustrates the speed capabilities of the various process technologies available today. Bandwidth requirements and speed are not the only considerations when deciding which technology to use for an integrated circuit (IC) addressing an application area. Other considerations are cost and integration. The clear treod today is to use CMOS digital combined with CMOS analog (as needed) whenever possible because significant integration can be achieved, thus providing highly reliable compact system solutions.

Analog inpul

--.

Preprocessing (fillcring and AID conversion)Analog

+I

I I

Digilal signalprocessor

+I I I

I I

Postprocessing Analog (D/A conversion ~OUipllt and fillc:riog)Analog

Digillll

Figure 1.3-1 A typical signal-processing system block diagram.

10

INTRODUCllON AND BACKGROUNDFigure l.J-2 Frequency of signals used in signal-processing applications.

Vidop,S.i mic

~~ rii~:

S011

RadarAM-F ~ radlc TV

A idi

Tele ommu licollon

Micro

"""HIOG

l

10

100

IlL

lOlL

J(XIk

IM

JOM lOOM

10

100

Signol Fnoquency (lbl

1.4 EXHMPLE OF RHHLUG YLSI MIXED-SIGHRL CIRCUIT DESIGNAnalog circuit design methodology is best illustrated by example. Figure 1.4-1 shows the

block diagram of a fully integrated digital read/write channel for disk-drive recording applications. The device employs partial response maximum likelihood (PRML) sequence detection when reading data to enhance bit-error-rate versus signal-to-noise ratio performance. The device supports data rates up to 64 Mbits/s and is fabricated in a 0.8 IJ.M double-metal CMOS

process.In a typical application. this IC receives a fully differential analog signal from an external

preamplifier, which senses magnetic transilions on a spinning disk-drive platter. This differential read pulse ls first amplified by a variable gain amplifier (VGA) under control of a realtime digital gain-control loop. After amplification, the signal is passed to a seven-pole twozero equiripple-phase low-pass filter. The zeros of the filter are real and symmetrical about the imaginary axis. The locations of the zeros relative to the locations of the poles are programmable and are designed to boost filter gain at high frequencies and thus narrow the width of the read pulse,Figure l.J-3 Frequencies that

can be proces5ed by present-dayiCMO

technologies.Bi plar an Ina BiJ>Olrdigi~

logic

~M

~usc

s digi

llol!ic

li!osru aloOptical

buA10

100

U.

Jillte

Figure 2.3-1 Physical structure of an n-channel and p-channe1transistor in an o-well technology.

:.

and source and are separated by a distance L (referred to as the device length). At the surface between the drain and source lies a gate electrode that is separated from the silicon by a thin dielectric material (silicon dioxide). Similarly, the a-channel transistor is formed by two heavily doped o+ regions within a lightly doped p- substrate. It, too, has a gate on the surface between the drain and source separated from dle silicon by a thin dielectric material

(silicon dioxide). Essentially, both types of transistors are four-tenninal devices as shown inFig. 1.2-2(c,d). The B terminal is the bulk, or substrate, which contains the drain and source diffusions. For an n-well process, the p-bulk connection is common throughout the integrated circuit and is connected to Vss (the most negative supply). Mulliple n-wells can be tilbricated on a single circuit, and they can be connected to different potentials in various ways depending on the application. Figure 2.3-2 shows an n-channel transistor with all four terminals connected to ground. At equilibrium, the p- substrate and the n + source and drain form a pn junction. Therefore, a depletion region exists between the n+ source and drain and the p- substrate. Since the source and drain are separated by back-to-back pn junctions, the resistance between the source and drain is very high (> 1012 fl). The gate and the substrate of the MOS transistor form the parallel plates of a capacitor with the Si02 as the dielectric. This capacitance divided by the area

p substrak:

Figure 2.3-2 Cross section of an n-channel transistor with all tenninals grounded.

J8

CMOS TECHNOLOGY of the gate is designated as Cu~ * When a positive potential is applied to the gate with respect to the source a depletion region is fonned under the gate resulting from boles being pushed away from the silicon-silicon dioxide interface. The depletion region consists of fixed ions that have a negative charge. Using one-dimensional analysis, the charge density, p, of the depletion region is given by

P"" q(-N,)Applying the point form of Gauss's law, the electric field resulting from this charge is E(x)

(2.3-1)

=

Je

-dx

P

:=

f

-qN,., -qN, --dx = - - x + CSsJ BsJ

(2.3-2)

where Cis the constant of integration. The constant. C, is determined by evaluating E(x) at the edges of the depletion region (x = 0 at the Si-Si02 interface; x = xd at the boundary of the depletion region in the bulk).E(O) =

Eo = - - 0 + C = C

-qN.., esi

(2.3-3)

(2.3-4)

(2.3-5) This gives an expression for E{x):E(x)

qN, = es;

(xd - x)

(2.3-6)

Applying the relationship between potential and electric field yields (2.3-7) Integrating both sides of Eq. (2.3-7) with appropriate limits of integration gives

"'J'dt/> = - fz"qN, (xd Bst"' 0

x) dx =

(2.3-8)

"The symbol C normally bas units of farads; however, in the field of MOS devices it often has units of farads per unit area (e.g., F/m2).

2.3

The MOS Transistor

39

qNAx~ -- =2ssl

tPs - tPF

(2.3-9)

where rpp is the equilibrium electrostatic potential (Fermi potential) in the semiconductor, rPsis the surface potential of lbe semiconductor, and xd is the thickness of lbe depletion region. For a p-type semiconductor, rPF is given as (2.3-10)

and for ann-type semiconductor tPF is given as(2.3-11)

Equation (2.3-9) can be solved for x4 assuming that lt/J, -

rp~ ~

0 to get (2.3-12)

The immobile charge due to acceptor ions that have been stripped of lbeir mobile holes is

given byQ=-qN,.,h

(2.3-13)

Substituting Eq. (2.3-12) into Eq. (2.3-13} gives(2.3-14)

When the gate voltage reaches a value called the threshold voltage, designated as Vr. the substrate underneath the gate becomes invened; that is, it changes from a p-type to an n-type semiconductor. Consequently, ann-type channel exists between the source and drain that allows carriers to ftow. In order to achieve this inversion, lbe surface potential must increase from its original negative value (rp, = 1/Jp), to zero (t/1., = 0). and then to a positive value (1/J, = -rpp). The value of gate-source voltage necessary to -cause this change in surface potential is defined as the threshold voltage, Vr. This condition is known as strong inversion. Then-channel transistor in this condition is illustrated in Fig. 2.3-3. With the substrate at ground potential, the charge stored in the depletion region between the channel under the gate and the substrate is given by Eq. (2.3-14), where q,, has been replaced by -rp,to account for the fact that vas= VrThis charge QbO is wrinen as(2.3-15)

If a reverse-bias voltage v8 s is applied across the pn junction, Bq. (2.3-15) becomes(2.3-16)

-40

CMOS TECHNOLOGY

FOX

FOXy=.O

------/{lnvct1ed chat1nelp- substrate

!-- WyJ---!y !

-: :-dy:y=L

~

y.+-dy

Figure 2.3-3 Cross section of llll n-channel transistor with small Y~:~s lllldVG$

>

V7'

An expression for the threshold voltage can be developed by breaking it down into several components. First, !:he tenn* tbus must be included to represent the difference in the work functions between the gate material and bulk silicon in the channel region. The tenn tPMs is given bytPMs

= tPF (substrate) -

q,, (gate)

(2.3-17)

where ,P,(metal) = 0.6 V. Second, a gate voltage of [ (Q~o/C.,,)) is required to change the surface potential and offset the depletion-layer charge Qb Lastly, !:here is always an undesired positive charge Q., present in the interface between the oxide and the bulk silicon, This charge is due to impurities and imperfections at the interface and must be compensated by a gate voltage of -(b,JC0 ,. Thus, the thre.hold voltage for the MOS transistor can be expressed as

-zq,,..-

Vr = 4Ms

+

(

-2(/IF--

C.,.

Qh) + (-Q. .) -C.,,(2.3-18)

The threshold voltage can be rewritten as

(2.3-19) whereV 7ll=. ..MS-

2~F

-

C OX

Qw

Q,. -C""

{2.3-20}

Historically. this term has been referred to as the metalfOsilicon work: function. We will continue the tradition even when the gate terminal is something other than melal (e.g., polysilicon).

2.3 The MOS Transistor TABLE 2.3-1 Signs for the Quantities in the Threshold Voltage Equation Parameter~t.iS

41

n-Channel (p-Type Substrate)

p-Channel (n Type Substrate)

..,

Metal a+ Si gate p+ Si gate

+

+

a60o a.Q..Vsa

+++

+ +

'(

+

and the body factor, body-effect coefficient, or bulk-threshold parameter -y is defined as (2.321) The signs of the above analysis can become very confusing. Table 2.31 attempts to clarify any confusion that might arise [25].

CALCULATION OF THE THRESHOLD VOLTAGE Find the thre.~hold voltage and body factor -y for an n-channel transistor with an n + silicon gate if t0 , = 200 A, NA = 3 X 10 16 em - 3 , gate doping, N0 = 4 X 10 19 em - 3 , and if the number of positively charged ions at the oxide-silicon interface per area is 10 10 em - 2

&taMII.J.MFrom Bq. (2.3-10), rPF(subslrate} is given as3 X 10 ) tPp(substrate) = -0.0259 In ( = -0.377 V 1.45 X 1010 The equilibrium electrostatic potential for the n + polysilicon gate is found from Eq. (2.3-11) as16

.p,(gate)

= 0.0259ln (

4 X 10 ) = 0.563 V 1.45 X 10 10

19

Equation (2.3-17) gives .PMs asrflp(substrate) - q,,(gate) = -0.940 V

een to double approximately every 5 C increase as illustrated in the following eltample. CALCULATION OF THE REVERSE DIODE CURRENT TEMPERATURE DEPENDENCE AND TC, Assume that the temperature is 300 K (room temperature) and calclJiate the reverse diode current change and the TCI'l for a 5 C increase.

SolutionThe TCFcan be calculated from Eq. (2.5-12) asTCF

= 0.01 + 0.155 = 0.165

Since the TCF is change per unit of temperature the reverse cUITent will increase by a factor of 1.165 for every kelvin (or QC) change in temperature. Multiplying by 1.165 five times gives an increase of approximately 2. This implies that the reverse saturation cUITent will approximately double for every 5 C temperature increase. Experimentally, the reverse current doubles for every 8 C increase in temperature because the reverse cUITent is in part leakage CUITent.

54

CMOS TECHNOLOGY

The forward-biased pn-junction diode current is given by (2.5-13) Differentiating this expre....~ion with respect to temperarure and assuming that the diode voltage is a constant (v0 = V0 ) gives

-=-----lo tiT I. tfi' T V,

din

lo dl,

1 Vo .

(2.5-14)

The fractional temperature coefficient for io results from Eq. (2.5-14) as(2.5-15)If V0 is assumed to be 0.6 V, then the fractional temperature coefficient is equal to 0.01 + (0.155- 0.077) = 0.0879. It can be seen that the forward diode current will double for ap-

proximately a 10 C increase in temperature. The above analysis for the forward-biased pn-junction diode assumed that the diode voltage v0 was held constant. If the forward current is held constant (i0 = /0 ), then the fractional temperature coefficient of the forward diode voltage can be found. from Eq. (2.5-13) we can solve for v0 to get

v0

~ V,ln (;,)3V, _ ~.GOT T

(2.5-16)

Differentiating Eq. (2.5-16) with respect to temperature gives

dvo = vtfr

0 _

V.I

T

(.!. dl,) = I. tiT

V1> _

T

= _ (Voo- Vo) _ 3V,T T

(2.5-17)

Assuming that v0 = V0 = 0.6 V, the temperature dependence of the forward diode voltage at room temperature is approximately -2.3 mV/C. Another limitation of CMOS components is noise. Noise is a phenomenon caused by small fluctuations of the analog signal within the components themselves. Noise results from the fact that eleclrical charge is not continuous but the re..vn5), where Vos is the actual drain-source voltage and not v05 (sat). The saturation region model modified to include channel length modulation is given in Eq. (3.1-18):0 < (vGs - Vr) :S Vos

(3.1-18)

3.1

Simple MOS Large-Signal Model !SPICE LEVEL 1)

77

--I

~---------- v

G5

-V.

T

=1.00

I

Vw VT

I

0.75

' '

o.so0.2S 0----------------- vli3"-Vr =O.SO VG.II>-VT

Cutoff Jqlion

v G5

o.s

1.0

Figure 3.13 Output characteristics of tbe MOS device.

"

,.-:--- valii- v,2.02.S

v.T

=0.00

vllSI(VGlQ-Y.,.l

The output characteristics of the MOS transistor can be developed from Eqs. (3.1-14}, (3.1-16), and (3.1-18). Figure 3.1-3 shows these characteristics plotted on a normalized basis. These curves have been normalized to the upper curve, where Va.ru is defined as the value of v0 :; that causes a drain current of I 00 in the saturation region. The entire characteristic is developed by extending the solid curves of Pig. 3.1-2 horizontally to the right from the maximum points. The solid curves of Fig. 3.13 correspond to>.= 0. If A 4:-0, then the curves are the dashed lines. Another important characteristic of the MOS transistor can be obtained by plotting i" versus Vcs using Eq. (3.1-18). Figure 3.1-4 shows this result. This characteristic of the MOS transistor is called the transconductance characteristic. We note that the transconductance characteristic in the saturation region can be obtained from Fig. 3.1-3 by drawing a vertical line to the right of the parabolic dashed line and plotting values of i0 versus v0 s. Figure 3.1-4 is also useful for illu.~trating the effect of the source-bulk voltage, v58 As the value of Vs8 increases,

Flgun:! 3.1-4 Transconduclance characteristic of the MOS transistor as a function of the source-bulk voltage, l'ss-

0

78

CMOS DEVICE MODELING

the value of Vr increases for the enhancement, n-channel devices (for a p-channel device, IVrl increases as v88 increases). V7 also increases positively for !hen-channel depletion device, but since V7 is negative, the value of Vr approaches zero from the negative side. If vs8 is large enough, Vr will actually become positive and the depletion device becomes an enhancement device. Since the MOS transistor is a bidirectional device, determining which physical node is the drain and which the source may seem arbitrary. This is not really the case. For an n-channel transistor, the source is always at the lower potential of the two nodes. For the p-channel transistor, the source is always at the higher potential. It is obvious that the drain and source designations are not constrained to a given node of a transistor but can switch back and forth depending on the tenninlll voltage~ applied to the tranSistor. A circuit version of the large-signal model of the MOS transistor consists of a current source connected between the drain and wurce terminals. that depends on the drain, source, gate, and bulk terminal voltages defined by the simple model described in this section. This simple model has five electrical and process parameters that completely define it. These parameters are K', Vr. 'Y X and 2411' The subscript n or p will be used when the parameter refers to an n-channel or p-channel device, respectively. They constitute the LEVEL 1 model parameters of SPICE fS]. 'JYpical values for these model parameters are given ill Table 3.1-2. The function of the large-signal model is to solve for the drain current given the terminal voltages of the MOS device. An example will help to illustrate this as well as show how the model is applied to the p-channel device.

APPLICATION OF THE SIMPLE MOS LARGE-SIGNAL MODELAssume that the transistors in Fig. 3.1-1 have a W/L ratio of 5 jLm/l !Lffi and that the largesignal model parameters are those given in Table 3.1-2. If the drain, gate, source, and bulk voltages of the n-channel transistor are 3 V, 2 V, 0 V, and 0 V, respectively, find the drain current Repeat for the p-channel transistor if the drain. gate, source, and bulk voltages are -3 V, -2 V, 0 V. and 0 V. respectively.

We must first determine in which region the transistor is operating. Equation (3.1-15) gives v 05 (sat} as 2 V - 0. 7 V == 1.3 V. Since vD.5 is 3 V, the n-channel transistor is in the saturation region. Using Eq. (3.1-18) and the values from Table 3.1-2, we haveJn =

.

K/.W 2L (vas 110

2 VTN) {1

+ XN vos)2

=

x w-6(5 jLm)l(ljLm)

(2- 0.7) (I

+ 0.04 X 3) =

520 !LA

Evaluation of Eq. (3.1-15) for the p-channel transistor is given asllso{sat)"" Vsa-

IVrPI = 2 V- 0.7 V =

1.3 V

3.2

Other MOS Large-Signal Model Parameters

79

Since vso is 3 V, the p-channel transistor is also in the saturation region, and Eq. (3.1-17) is applicable. ThedraincurrentofFig. 3. [-l(b) can befoundusingthe values fromTable3.1-2as

lo = -u-D2 (1 + )...,vso)0.7)2(1

x~~:~IJ.m) (2Vus =

+

0.05 X 3)

= 24311-A(3.1-19)

It is often useful to describe vas in terms of i/) in saturation as shown below:Vr +

vu;;ifJ

This expression illustrates that there are two components to vGs--an amount to invert the channel plus an additional amount to suppon the desired drain current. This second component is often referred to in the literature as VoN Thus VoN can be defined as (3.1-20) The term VoN should be recognized as the term for saturation voltage Vns (sat). They can be used interchangeably.

3.2 OTHER MOS LHRGE-SIGNHL MODEL PHRHMETERSThe large-signal model also includes several other characteristics such as the source/drain bulk junctions, source/drain ohmic resistances, various capacitors, and noise. The complete version of the large-signal model is given in Fig. 3.2-1. The diodes of Fig. 3.2-1 represent the pn junctions between the source and substrate and the drain and substrate. For proper transistor operation, th~-e diodes must always be reverse biased. Their purpose in the de model is primarily to model leakage currents. These currents are expressed as180

.

= 1, exp

[ (qvso) - 1 ] kT

(3.2-1)

and (3.2-2) where I, is the reverse saturation cUI'!'ent of a pn junction, q is the charge of an electron, k is Boltzmann's constant. and Tis temperature in kelvin units. The resistors r0 and rs represent the ohmic resistance of the drain and source, respectively. 'JYpically, these resistors may be 50-100 fi* and can often be ignored at low drain currents.For silicilk process, lhese resislallces will be much leiiS-on the order of 5-l 0 n.

80

CMOS DEVICE MODELING

Figure 3.2-1 Complete large-signal model for theMOS II'lll1sistor.

G

B

sThe capacitors of Fig. 3.2-1 can be separated into three types. The first type jncludes capacitors C80 and C85 , which are a.'!sociated with the back-bia.'!ed depletion region between the drain and substrate and the source and substrate. The second type includes capacitors Cc;0 , Cas. and Ca~~o which are all common to the gate and are dependent on the operating condition of the transistor. The third type includes parasitic capacitors, which are independent of the operating conditions. The dc;pletion capacitors are a function of the voltage across the pnjunction. The expression of this junction-depletion capacitance is divided into two regions to account for the high injection effects. The first is given as

Vsx Cax = (CJ) (AX) [ I - PB ]where

-MJ

vex

s (FC)(PB)

(3.2-3)

X= DforC80 orX = SforCBS

AX = area of the source (X = S) or drain (X = D)CJ = zero-bias (v8 x = 0) junction capacitance (per unit area)

qes;Nsua 2PB PB = bulk junction potential [same as and C08 as a function of Va.s with Vos constant and V63 = 0.

3.2

Other MOS Large-Signal Model Parameters

8S

and C08 is approximately equal to C1 + 2C5 As v0 s approaches Vr from the off region. a thin depletion layer is formed, creating a large value of C4 Since C4 is in series with C2, Httle effect is observed. As vas increases, this depletion region widens, causing C4 to decrease andreducing Cell When Vc;s = VT, an inversion layer is formed that prevents further decreases of c4 (and thus C08). C., C2, and C3 constitute Cas and CoD The problem is how to allocate C2 to Cas and Cav The approach used is to assume in saturation that approximately two-thirds of C2 belongs to Cas and none to C00. This i~;, of course, an approximation. However, it ha.~ been found to give reasonably good results. Figure 3.2-7 shows how Cas and C00 change values in going from the off to the saturation region. Finally, when v08 is greater than v08 + Vr; the MOS device enters the nonsaturated region. [n this case, the channel extends from the drain to the source and C2 is simply divided evenly between Cav and Ccs as shown in Fig. 3.2-7. As a consequence of the above considerations, we shall use the following formulas for the charge-storage capacitances of the MOS device in the indicated regions.

Off(3.2-9a)(3.2-9b}

(3.2-9 are defined as. g,. = iHo(evaluated at the. qutescent pomt )

-a\Ius

(3.3-3) (3.3-4)

8mb.r

iJio . = -- (evaluated at the qutescent pomt) iJvss

and8dl = -,.-(evaluated at the qwescent pomt)a~

.

.

(3.3-5)

""ns

3.3. Small-Signal Model for the MOS Transistor

89

The values of these small-signal parameters depend on which region the quiescent point occurs in. For example, in the saturated region g., can be found from Eq. (3.1-18) as (3.3-6) which emphasizes the dependence of the small-signal parameters on the large-signal operating conditions. The small-signal channel transconductance due to v58 is found by rewriting Eq. {3.3-4) as (3.3-7) Using Eq. (3.1-2) and noting that atD/iJVr = -aiofavas. we get*1'

(3.3-8)

This transconductance will become important in our small-signal analysis of the MOS transistor when the ac value of the source-bulk potential v.., is not zero. The small-signal channel conductance, gd, {g0 ), is given as (3.3-9)

The channel conductance will be dependent on L through )., which is inversely proportional to L. We have assumed the MOS transistor is in saturation for the results given by Eqs. (3.3-6), (3.3-8), and (3.3-9). The important dependence of the small-signal parameters on the large-signal model parameters and de voltages and current~ is illustrated in Thble 3.3-1. In this table we see that the three small-signal model parameters of g,. Kmm. and Kd have several alternate fonns. An example of the typical values of the small-signal model parameters follows.

TYPICAL VALUES OF SMALL-SIGNAL MODEL PARAMETERSFind the values of Km Km~n. and R.u using the large-signal model parameters in Table 3.1-2 for both an n-channel and a p-channel device if the de value of the magnitude of the drain current is 50 f.LA and the magnitude of the de value of the source-bulk voltage is 2 V. Assume that tbe WIL ratio is 1 j.~.m/1 tJ.rn.

Note that absolute signs are used for V88 in order to prevent g- from becoming infinite. However, in a few rare cases the soiii'CHulk junction is forward biased and in this case the absolute signs must be removed and Vs8 becomes negative (for n-channel transistor).

90

CMOS DEVICE MODELING

TABLE 3.3-1 Dependence of the Small-Signal Model Parameters on the de Values of Voltage and Current in the Saturation RegionSmall-Signal Model ParametersB..

de Current.. (2K' (D Wfl-) 112

de Current and Voltage

de Voltage""-(Vos- Vr)K'W L ')'[fj(VGJ- V7)] 112

g..,lr.t.

"'t(2Jo(J)lfl

2.lo

2(2\4> ;\

+

IVsail ill

I

Bm~n ~ 12.8 11-A/V, and 8.ts = 2.0 ILA/V for then-channel device and Bm = 12.0 ~/V, and B.ts = 2.5 JJ.A/V for the p-channel device.

Using the values of Table 3.1-2 and Eqs. (3.3-6), (3.3-8), and (3.3-9) gives g,., = 105 fJ.A/V, 70.7 fJ.AIV, 8m~n

=

Although MOS devices are not often used in the nonsaturation region in analog circuit design, the relationships of the small-signal model parameters in the nonsaruration region are given as (3.3-10)

(3.3-11) and8rb e fJ(Vas- Vr- V~)

(3.3-12)

Table 3.3-2 summarizes the dependence of the small-signal model parameters on the largesignal model parameters and de voltages and currents for the non saturated region. The typical values of the small-signal model parameters for the nonsaturated region are illustrated in tbe following example.

TYPICAL VALUES OF THE SMALL-SIGNAL MODEL PARAMETERS IN THE NONSATURATED REGIONFind the values of the small-signal model parameters in the nonsaturation region for an n-channel and a p-channel transistor if Vas = 5 V, Vos =' l V, and IV851 ""' 2 V. Assume that the WIL ratio for both transistors is 1 p.m/1 p.m. Also assume that the value forK' in the nonsaturation region is the same as that for the saturation (generally a poor assumption}.

3.3

Small-Signal Model for the MOS Transistor

91

TABLE 3.3-2 Dependence of the Small-Signal Model Parameters on the de Values of Voltage and Current in the Nonsaturation RegionSmall-Signal Model Parameter:s de Voltage and/or current Dependence

2(21~,1

+ 1Vsall112

I!(Vn.,- Vr- Vlls)

Solution First, it is necessary to calculate the threshold voltage of each transistor using Eq. (3.1-2). The results are a Vr of 1.02 V for the n-channel and -1.14 V for the p-channel. This gives a de current of 383 j.LA and 168 j.LA, respectively. Using Eqs. (3.3-10), (3.3-11). and (3.3-12), we get Km = 110 ~J.A/V, Cmru = 13.4 ~J.A/V, and r.u = 3.05 kil for then-channel transistor and 8m = 50 IJ..A/V, 8mru = 8.52 j.LA/V, and rtb = 6.99 kO for the p-channel transistor. The values of rd and r:. are assumed to be the same as r0 and rs of Fig. 3.2-1. Likewise, for small-signal conditions C8., Csd C~~ Cbd, and C"" are evaluated for Cv, CBd and C8 , by knowing the region of operation (cutoff, saturation or nonsaturation) and for Cbd and Cbs by knowing the value of V11o and Vns With this infonnation, C8,, C11d C8b Cbd, and Cb, can be found from Cus. Cuo Ca 8 Cso and Css. respectively. If the noise of the MOS transistor is to be modeled, then three additional current sources are added to Fig. 3.3-1 as indicated by the dashed lines. The values of the mean-square noisecurrent sources are given as

i~rD = ( 4 ::)Afi~rS = (~;)A/and

(A2)

(3.3-13)

(Al)

(3.3-14)

(3.3-15) The various parameters for these equations have previously been defined. With the noise modeling capability, the small-signal model of Fig. 3.3-1 is a very general model. It will be important to be familiar with the small-signal model for the saturation region developed in this section. This model. along with the circuit simplification techniques given in Appendix A, will be the key element in analyzing the circuits in the following chapters.

92

CMOS DEVICE MODELING

3.4

COMPUTER SIMULATION MODELSThe large-signal model of the MOS device previously discussed is simple to use for band cal culations but neglect~ many important second-order effect~. Wbile a simple model for hand calculation and design intuition is critical, a more accurate model is required for computer simulation. There are many model choices available for the designer when choosing a device model to use for computer simulation. At one time, HSPICE"' supported 43 different MOSFET models [2] (many of which were company proprietary) while SmartSpice publishes support for 14 [9). Whlcb mndel is the right one to use? In the fabless semiconductor environment, the user must use the model provided by the wafer foundry. Jn companies where the foundry is captive (i.e., the company owns its own wafer fabrication facility) a modeling group provides the model to circuit designers. It is seldom that a designer cbOO$ell a model and performs parameter extraction to gel the terms for the model chosen. The SPICE LEVEL 3 de model will be covered in some detail because it is a relatively straightforward extension of the LEVEL 2 model. The BSJM3v3 model will be introduced but the detailed equations will not be presented because of the volume of equations required to describe it-there are other good texts that deal with the subject of modeling exclusively {10,11], and there is little additional design intuition derived from covering the details. Models developed for computer simulation have improved over the years but no model has yet been developed that, with a single set of parameters, coveis device operation for all possible geometries. Therefore, many SPICE simulators offer a feature called model binning: Parameters are derived for transistors of different geometry (W's and l.'s) and the simulator detennines which set of parameters to use based on the particular Wand L called out in the device instantiation line in the circuit description. The circuit designer need only be aware of this since the binning is done by the model provider.

SPICE LEVEL 3 ModelThe large-signal model of the MOS device previously discussed is simple to use for hand calculations but neglects many important second-order effects. Most of these second-order effects are due 10 narrow or short channel dimensions (le.-;s than about 3 p.m). ln this section, we will consider a more complex model that is suitable for computer-based analysis (circuit simulation, i.e., SPICE simulation). In particular, the SPICE LEVEL 3 model will be covered (see Table 3.4-1}. This model is typically good for MOS technologies down to about 0.8 ~~om. We will also consider the effects of temperature on the parameters of the MOS large-signal model We first consider second-order effects due to small geometries (Fig. 3.4-1 ). When Vas is greater than V11 the drain current for a small device can be given a.~ {2] follows:

Drain Current'os =BETA Vas-

.

[

Vr- - 2

(l+ft,)]w.rr

VoE llo

(3.4-1)

BETA= KP- = ..."cox4Ir .. .L..rrHSP(CE is now owned by Avant! Inc:. and has been n:named Star-H.spice.

w.lf

(3.4-2)

3.4

Computer Simulation Models

93

TABLE 3.4-1 Typical Model Parameters Suitable for SPICE Simulations Using LEVEL-3 Model (Extended Model)*Typical Parameter Value Parameter

Sym6ot

Parameter OescripCI'on Threshold Mobility Narrow-width threshold adjustment factor Static-feedback threshold adju.tment factor Saturation field factor In channel length m~Jdulalion Mobility degradation factor Subs!rate doping Oxide lhickne~;s Melllllurgicaljunction deplh Delta width Lareral diffusion Psrameter for weak inversion modeling

rr-Chtmnel0.7:!: 0.15

p-Chmree-0.7:!: 0.15

l.hriU

vrouoDELTAEl'A

vt:m 1N-s

660 2.40.1

2101.250.1

KAPPA THETA

0.15 0.1 3 X 1016140

2.50.1 6 x 10161400.2 0.015 6 X IOH :220 X 10- 12 220 x

IN INem-' AJ.Ull

NSUB TOXXJWD

0.20.016 7 X 1011 :220 X 10-la :220 X 10-11

J.Ull)1.111

LD NFS

cm- 2F/m

cosoCGDO

CGBOCJ CJSW MJ MJSW

100 110

x w- 2 x w- Jso x w- 120.5 0.38

w-

700 X 10-IZ

Flm FlmP/m2 F/m

560 X 10"6350 X 10-lt 0.5

0.35

"The-o;e values ate based on a 0.8 J.Ull silicon-gate bulk CMOS n-well process and include capacitance parame1en1from Table 3.2-1.

I..., = L - 2{LD)

(3.4-3)

w.lf = w lfoe

2(WD)

(3.4-4)

=

min(vru.., vos(sat))

(3.4-5)(3.4-6}

1" =

GAMMA f. fn + 4(PHI + vss) 112

Gate

Figure 3.4-1 Illustration of tbe shortchannel effects in rbe MOS transistor.

Bulk

94

CMOS DEVICE MODELING

Note that PHI is the SPICE model term for the quantity 2(/)p. Also be aware that PHI is always positive in SPICE regardless of the transistor type (p- or n-cbannel). In this tellt, the term PHI will always be positive while the term 2(/)p will have a polarity determined by the tr.msistor type as shown in Table 2.3-1.fn =DELTATBs;

w.aJ;

2C.,.2 112

(3.4-7)wp ) ]_

=

l- 4rr XJ l - ( XJ+wp XJ{LD +we[+ "ss) 1122. e. )112 51 ( q NSUB

LD} XJ

(3.4-8)(3.4-9)

wp = xd(Plflxd=

(3.4-10)

(3.4-11)

kt = 0.0631353,

kl = 0.08013292,

k3 = 0.011 10777

Threshold VoltageVr

= V~n -

ETA- 8.14 X 10-22 ) (

c....

3 ~

. Vns

+ GAMMA /.(PHI + Vss) 112+ /n{PHI +llss)

(3.4-12)

(3.4-13)

orvbl

= vro -

GAMMA

VPHl

(3.4-14)

Saturation VoltageVw

v,s- Vr = 1 + fb=

(3.4-15)

VDs(sat)

v.., +

Vc-

(v;.. + ~~~)'

12

-

(3.4-16)(3.4-17)

vc =

VMAX l.,ff p;.~

lfVMAX is not given, then v00 (sat)

v001

3.4

Computer Simulation Models

95

Effective Mobility

I I

I

~

,.., - 1 +THETA (vGI- V7)'P..ff =

" -

UO

when VMAX = 0

{3.4-18)

p,

1+~Vc

v when VMAX > 0; otherwise l'ctt = p..

(3.4-19)

Channel Length Modulation

ti.L = xd [KAPPA (vDs- vDS(sat))]'12,tiL=ep

when VMAX

=0

{3.4-20)

~xJl + [

ep ~Jy +

KAPPA xtf (vDS- VDs(sat))

J

12 ,

(3,4-21)

whenVMAX>O whereep =.Vc (vc

+ Vos (sat))

L.tt VDS (sat}1 _ tJ.iDs

(3.4-22}

los=

(3.4-23)

The temperature-dependent variables in the models developed so far include the Fermi potential, PHI, EO, bulk junction potential of the sourc~ulk and drain-bulk junctions, PB, tbe reverse currents of the pn j'unctions, / 8 , and the dependence of mobility on remperacure. The temperature dependence of most cf these variables is found in the equations given previously or from well-known expressions. The dependence of mobility on temperature is given asUO(T} = UO(T0)

T)BBX ( To

(3.4-24)

. where BEX is the temperature exponent for mobility and is typically -1.5.llthorm

(T) " " -

kT q

(3.4-25)

EG(T)

= 1.16- 1.02 10-To

PHI(T) = . 'T} _

[r + ~:os.o] T) [3 In (To + T) PHI(To) . (- vlhernlo ( T}

(3.4-26)

EG(T0 ) EG( T) ] vobonD (To) - vtherm ( T)

(3.4-27)

vbl\

- VIR\o}

. ,.,.

+

PHJ(T)- PIU(T0)

2

+

EG(T0 ) - EG(T) 2

(3.4-28)

96

CMOS DEVICE MODfLING

VTO(T) =

vbl {T)

+ GAMMA[ VPHJ(

T)]

(3.4-29)

PHI(7) = 2v~~>orm In ni.,T)

(NSUB)312

(3.4-30)exp[EG

n/..T)

= 1.45 1016 (!:._) T0

(.!.- 1) ( 2 vlheml (To) ) I ToEG(T0 ) EG(T) ]

(3.4-31)

For drain and source junction diodes, dle following relationships apply: PB(T) = PB To

(T) -

v~~~mn (T) 3 In To + vlllonn (To) - v......., (T)

( (T)_Vthonn

(3.4-32)

and ls (T)]2(PHT

+ vs8 )

(

3'5 2)

_

NFS is a parameter used in the evaluation of VoN and can be extracted from measurements. The drain current in the weak inversion region, Vas< VoN is given as

IDS

.

= IDS (VoN \IDE Vse) exp

.

(Vos- VaN) fast

(3.5-3)

where ios is given as [from Eq. (3.4.1), with Vm replaced with V01,]ros

.

=BETA. VoN- Vr- - 2

[

(1 +'b) ]VIJE

Voe

(3.5-4)

llltMJ

Weak

..p;

1000.0HIO.O

inVel'i\iOfl

"'glon

inversia11

Siron&"'&ion

10.01.0

0

V7

VIIH

vG.J

U

\11

VON

Vas

Figure 3.5-l Weak inversion characteristics of the MOS transistor as modeled by Eq. (3.5-4).

3.6Moclcrau! inversion region

SPICE Simulation of MOS Circuits

99

Figure 3.5-l The three regions of operation of an MOS transistor.

+1000.0 100.0Weak lnven;iooSln!llg

lnvenlionregion

111.0

r.o .___ ___.;.....__..___,._____0

For hand calculations, a simple model de.'>Cribing weak inversion operation is given aslo a; L loo exp

W

(Vo.r) n(kT/q)

(3.5-5)

"'

where the term n is the subthreshold slope factor, and 1 is a process-dependent par-.nneter 00 that is dependent also on vs11 and V7 These two terms are best extracted from experimental data. '!Ypically n is greater tbaa 1 8lld less than 3 (1 < n < 3). The point at whicb a transistor enters the weak inver$ion region can be approximated as

"< V7 + nq -

kT

(3.5-6)

Unfortunately, the model equations given here do not properly model the transistor as it makes the transition from strong to weak inversion. In reality, there is a transition region of operation between strong and weak inversion called the "moderate inversion" region (15]. This is illustrated in Fig. 3.5-2. A complete treatment of the operation of the ttansistorthrough this region is given in the literature fl5,16]. It is important to consider the temperature behavior of the MOS device operating in the subthreshold region. As is the case for strong inversion, the temperature coefficient of the threshold voltage is negative in the subthreshold region. The variation of current due to temperature of a device operating in weak inversion is dominated by the negative temperature coefficient of the threshold voltage. Therefore, for a given gate-source voltage, subthreshold current increases as the temperature increases. This is illustrated in Fig. 3.5-3 [17). Operation of the MOS device in the subthreshold region is very important when low power circuits are desired. A whole class of CMOS circuits have been developed based on the weak inversion operation characterized by the above model [ 18-21]. We will consider some of these circuits in later chapters.

3.G SPICE SIMULRTIOI OF MOS CIRCUITSThe objective of this section is to show how to use SPICE to verify the perfonnance of an MOS circuit. It is assumed that the reader already has experience using SPICE to simulate circuits containing resisto!'ll, capacitors, source.~, and so on. This section will elltend the reader's

100

CMOS DEVICE MODEUNG

lo-4

Figure 3.53 Transfer characteristics of a loog-cbannet device as a function of temperature. (Cupyrigbl /977}.

to""i0cAJ

IIY

1

L=9jlm W/l.;9.7

V0 =0.1

to-oto2-0.20

YBS=O

0.2vGS

0.4

0.6(volts)

0.8

knowledge to include the application of MOS b'ansiBtors into SPICE simulations. The models used in this seclion are the LEVEL I and LEVEL 3 models. In order to simulate MOS circuits in SPICE, two components of the SPICE simulation file are needed. They are instance declarations and model descriptions. Instance declarations are simply descriptions of MOS devices appearing in the circuit along with cbaracteristics unique to each instance. A simple example tbat shows the minimum required terms for a transistor instance follows:

M1 ! 6 ? 0 NCH W=100U L:1UHere, the first letter in the instance declaration, M, tells SPICE that the instance is an MOS transistor (ju.~t like R tells SPICE that an instance is a resistor}. The 1 makes this instance unique (different from M2, M9 9, etc.) The four numbers following Ml specify the nets (or nodes) to which the drain, gate, source, and substrate (bulk) are connected. These nets have a specific order as indicated below:

M . .Following the net numbers, is the model name governing the character of the particular instance. In the example given above, the model name is NCR. There must be a model description somewhere in the simulation file that describes the model NCH. The transistor width and length are specified for the instance by the w "' 1 0 o u and L = 1 u expressions. The default units for width and length are meters so the U following the number 100 is a multiplier of 10-. (Recall that the following multipliers can be used in SPICE: M, u, N. P. F, for 10"3, 10"6 , 10"9 , 10" 12 10" 1 ~. respectively.) Additional information can be specified for each instance. Some of these are:

Drain area and periphery (AD .and PD)Source area and periphery (AS and P s) Drain and source resistance in squares (NRD and NRS)

3.6

SPICE Simulation of MOS Circuits

101

Multiplier designating how many devices are in parallel (M)

Initial conditions (for initial transient analysis)Drain and source area and periphery terms are used in calculating depletion capacitance and diode currents (remember, the drain and source are pn diodes to the bulk or well). The numbers of squares of resistance in the drdin and source (NRD and NR s) are used to calculate the drclin and source resistances for the tram;istor. The multiplier designator is very important and thus deserves extended discussion here. In Section 2.6 layout matching techniques were developed. One of the fundamental principles described was the ''unit-matching" principle. This principle prescribes that when one device needs to be M times larger than another device, then the larger device should be made from M units of the smaller device. In the layout, !he larger device would be drawn using M copies of the smaller device-all of them in parallel (i.e., all of the gates tied together, all of the drains tied together, and all of the sources tied together). In SPICE, one must account for the multiple component~ tied in parallel. One way to do this would be to instantiate the larger device by instantiating M of the smaller devices. A more convenient way to handle this is to use the multiplier parameter when the larger device is instantiated. Figure 3.6-l illustrates two methods for implementing a 2X device (unit device implied). In Fig. 3.6-l(a) the correct way to instantiate the device in SPICE is

Ml 3 2 1 0 NCH W=20U L=lUwhereas in Fig. 3.6-1 (b) the correct SPICE instantiation is

Ml 3 2 l

0 NCH W=lOU

~=lU

M=2

Figun:3.6-1 (a)Ml 3 2 1 0 NCH W 20U L = lU.~)Ml 3 2 1 0 NCH W = lOU L = lU M = 2.

=

r-

~.___....,

...(b)

~

J

~

I ~~n__(a)

102

CMOS DEVICE MODEUNG

Clearly, from the point of view of matching (again, it is implied that an attempt is made to achieve a 2:1 ratio), case (b) is the better choice and thus the instantiation with the multiplier is required. For the salce of completeness. it should be noted that the following pair of instan , tiatioos are equivalent to the use of the multiplier:M1A 3 2 1 0 NCH W=lOU L=lU MlB 3 2 1 0 NCH W=lOU L=lU

Some SPICE simulators offer additional terms further describing an instance of a MOS transistor. A SPICE simulation file for an MOS circuit is incomplete without a description of the model to be used to characterize lhe MOS transistors used in the circuit. A model is described by placing a line in the simulation file using the following format:.MODEL

The model line must always begin with . MODEL and be followed by a model name such as N c H in our example. Following the model name is the model type. The appropriate choices for model type in MOS circuits is either PMOS or NMOS. The final group of entries is model parameters. If no entries are provided, SPICE uses a default set of model parameters. Except for the crudest of simulation.~. you will always want to avoid the default parameters. Most of the time you should expect to get a model from the foundry where the wafers will be fabricated, or from the modeling group within your company. For times where it is desired to check hand calculations that were performed using the simple model (LEVEL 1 model) it is useful to know the details of entering model information. An example model description line follows . MODBL NCH NMOS LEVEL=l VTD=l KP=50U GAMMA=0.5 +LAMBDA=O.Ol

In this example, the model name isNCH and the model type is NMOS. The model parameters dictate that the LEVEL\ model is used with V'J' o, KP, GAMMA, and LAMBDA specified. Note that the + is SPICE syntax for a continuation line. The information on the model line is much more extensive and will be covered in this and the following paragraphs. The model line is preceded by a period to flag the program that this line is not a component. The model line identifies the model LEVEL (e.g., LEVEL=l) and provides the electrical and process parameters. If the user does not input the various parameters, default values are used. These default values are indicated in the user's guide for the version of SPICE being used (e.g .. SmartSpice). The LEVEL 1 model parameters were covered in Section 3.1 and are the zero-bi.a.~ threshold voltage, VTO (Vrol. in volt~ extrapolated to io = 0 for large devices; the intrinsic transconductance parameter, KP (K'), in amperes/volt2; the bulk threshold parameter, GAMMA (-y) in volt 112 : the surface potential at strong inver.;ion. PHI (2r/JF), in volts; and the channel length modulation parameter, LAMBDA()\), in volt- 1 Values for these parameters can be found in Table 3.1-2.

3.6

Spice Simulation of MOS Circuits

103

Sometimes, one would rather Jet SPICE calculate the above parameters from the appropriate process parameters. This can be done by entering the surface state density in em - 2 (NSS}, the oxide thickness in meters (TOX), th.e surface mobility, UO {#o), in cm21Vs, and the substrate doping in em- 3 (NSUB ). The equations used to calcuJate the electrical parameters are

VTO = .PMS - (e.,JTOX) +

q(NSS)

(2q ss; NSUB PHI) 112

(e.,.ITOX)

+ PHI

(3.6-1)

e.,,KP =UOTOX(2q s 51 NSUB) 112 GAMMA = (e.,.,/TOX) and

(3.6-2)

(3.6-3)

PHI= 12-PFI

2kT = - l n (NSUB) -q

n,

(3.6-4)

LAMBDA is not calculated from the process parameters for the LEVEL 1 model. The constants for silicon, given in Table 3.1-1, are contained within the SPICE program and do not have to be entered. The next model parameters considered are those that were considered in Section 3.2. The first parameters considered were associated with the bulk-drain and bulk-source pnjunctions. These parameters include the reverse current of the drain-bulk or source-bulk junctions in A (lS) or the reverse-current density of the drain-bulk or source-bulk junctions in A/m2 (JS). JS requires the specification of AS and AD on the model line. lf IS is specified, it overrides JS. The default value of IS is usually 1o- 14 A. The next parameters considered in Section 3.2 were the drain ohmic resistance in ohms (RD), the source ohmic resistance in ohms (RSJ. and the sheet resistance of the source and drain in ohms/square (RSH). RSH is overridden if RD or RS is entered. To use RSH, the values of NRD and NRS must be entered on the model line. The drain-bulk and source-bulk depletion capacitors can be specified by the zero-bias bulk junction bottom capacitance in farads per m 2 of junction area (CJ). CJ requires NSUB and assumes a step junction using a formula similar to Eq. (2.2-12).Altemately, the drain-bulk and source-bulk depletion capacitances can 'be specified using Eqs. (3.2-5) and (3.2-6). The necessary parameters include the zero-bias bulk-drain junction capacitance (CBD) in farads, the zero-bias bulk-source junction capacitance (CBS) in farads, the bulk junction potential (PB) in volts, the coefficient for forward-bias depletion capacitance (FC), the zero-bias bulk junction sidewall capacitance (CJSW) in farads per meter of junction perimeter, and the bulk junction sidewall capacitance grading coefficient (MJSW). IfCBD or CBS is specified, then CJ is overridden. The values of AS, AD, PS, and PD must be given on the device line to use the above parameters. "JYpical values of these parameters are given in Thble 3.2-1. The next parameters discussed in Section 3.2 were the gate overlap capacitances. These capacitors are specified by the gate-source overlap capacitance (CGSO) in farads/meter, the gate-drain overlap capacitance (CGDO) in farads/meter, and the gate-bulk overlap capacitance (CGBO) in farads/meter. Typical values of these overlap capacitances can be found in

104

CMOS DEVICE MODELING

Table 3.2 I. Finally, the noise parameters inc1ude the flicker noise coefficient (KF') and the flicker noi~ exponent (AF}. Typical values of these parameters are 10- 28 and l, respectively. Additional parameters not discussed in Section 3.4 include the type of gate material (TPG) . the thin oxide capacitance model flag, and the coefficient of channel charge allocaled to the drain (XQC). The choices for TPG are + 1 if the gate material is opposite to the substrate, -1 if the gate material is the same as the substrate, and 0 ir the gate material is aJu. minum. A charge-controlled model is used in the SPICE simulator if the value of the parameter XQC has a value smaUer than or equal to 0.5. This model attempts to keep the sum of charge associated with each node equal to zero. If XQC is larger than 0.5, charge conservation is not guaranteed. In order to illustrate its use and to provide examples for the novice user to follow, several examples will be given showing how to use SPICE to perfonn various simulations.

USE OF SPICE TO SIMULATE MOSOUTPUT CHARACTERISTICS

Use SPICE to obtain the output characteristics of then-channel transistor shown in Fig. 3.6-2 using the LEVEL 1 model and the parameter values of Table 3.1-2. The output curves are to be plotted for drain-source voltages from 0 to 5 V and for gate-source voltage.-; of 1, 2, 3, 4, ' and 5 V. Assume that the bulk voltage is zero.Figure 3.6-2 Circuit for Example 3.6-1.

1

+VDS

vas

lfiMU.J 1MTable 3.6-1 shows the input file for SPICE to solve this problem. The first line is a title for the simulation file and must be present. The lines not preceded by ": define the interconnection of the circuit. The second line describes bow the transistor is connected, defines the model to beTABLE 3.6-1 SPICE Input File for Example 3.6-1EX. 3.6-l Use of SPICE to Simulate MOS Output Ml 2 1 0 0 MOSl WSU L~l.OU VDS 2 0 S VGS 1 0 1 .MOD~L MOSl NMOS VT0=0.7 KPl10U GAMMA=0.4 LAM8DA=0.04 PHI=0.7 ,DC VDS 0 S 0.2 VGS 1 S l .PRINT DC V(2} I(VDS) .END

3.6

Spice Simulation of MOS Circuits

105

used, and gives thew and L values. Note that because the units are meters, the suffix u is used to convert to j.Lm. The third and forth lines describe the independent voltages. vns and VG s are used to bias the MOSFET. The fifth line is the model description for MI. The remaining lines instruct SPICE to perform a de sweep and print desired results.. DC asks for a de sweep. In this particular case, a nested de sweep is specified in order to avoid seven consecutive analyses. The . cc . . . line will set VGS to a value of 1 V and then sweep VDS from 0 to 5 V in increments of0.2 V. Next, it will increment VGS to 2 V and repeat the vns sweep. This is continued until five VDS sweeps have been made with the desired values of VGS. The PRINT line directs the program to print the values of the de sweeps. The last line of every SPICE input file must be END 11. Figure 3.6-3 shows the output plot of this analysis.Figure 3.6-3 Output from Example3.6-1.

0

0.5

1.0

1.5

2.0

2.S

3.0

3.5

~.0

._, ,.0

vos

< l .....

DC ANALYSIS OF FIG. 3.6-4Use the SPICE simulator to obtain a plot of the value of VoUT as a function of VJN of Fig. 3.6-4. Identify the de value of vm that gives VoUT = 0 V.Figun: 3.6-4 A simple MOS amplifier for Example3.6-2.

106

CMOS DEVICE MODEUNG

The input file for SPICE is shown in Table 3.6-2. It follows the same fonnat as the previ0111 example except that two typeS of transistors are used. These models are designated by MO SN and MO s P. A de sweep is requested starting from VJN = 0 V and going to +5 V. Figure 3.6-S shows the resulting output of the de sweep.TABLE 3.6-2 SPICE Input File for Example 3.6-2Bx. 3.6-2 OC Analysis of Fig. 3.6-4 Ml 2 1 0 0 MOSN w~su L=lO M2 2 3 4 4 MOSP w~so L~lU M3 3 3 4 4 MOSP w~su L~lU Rl 3 0 lOOKVD1> 4 0 DC 5,0

VIN 1 0 DC 5.0 .MODEL MOSN NMOS VT0~0.7 KP=llOU GAMMA=0.4 LAMBOA=0.04 PBI=0.7 .MODEL MOSP PMOS VT0=-0.7 KP=SOU GAMMA=0.57 LAMBDA=0.05 PHI=0.8 .DC VIN 0 S Q.l .PRINT DC V(21 .END5.0 ....---~,-----------.

Flgun:3.6-5 Output of Example 3.6-2.

.~.o.

-

2.0

.1.0 -

.0.0

'-...,Q

0-'

'

1.0

'

1

1-'

2.0

'

4.$

'

3.0 3-' ....- J

'

'

-4.0

'.,

.

5.1)

AC ANALYSIS Of FIG. 3.6-4Use SPICE to obtain a small-signal frequency response of Vou1(w)/V;n(w) when the amplifier is biased in the transition region. Assume that aS pF capacitQris attached to the output of Fig. 3.6-4 and find the magnitude and phase response over the frequency range of J00 Hz to 100 MHz.

lfiMit.J,;The SPICE input file for this example is shown in Table 3.6-3.1tis important to note thatV'IN has been defined as both an ac and a de vQltage source with a de value of 1.07 V, If the de

3.6 TABLE 3.6-3 SPICE Input File for Example 3.6-3Ex. 3.6-3 AC Analysis of Fig. 3.6-4M1 2 1 0 0 MO~ W=SU L:lU M2 2 3 4 4 MOSP W"SU L=lU M3 3 3 4 4 MOSP W=SU L=lU

Spice Simulation of MOS Circuits

107

CL 2 0 5P Rl 3 0 lOOKVDD 4 0 DC S.CI

VIN 1 0 DC 1.07 AC 1.0 .MODEL MOSN NMOS VTO 2 0.7 KP 1100 GAMMA~ 0.4 LAMBDA~ 0.04 PHI : 0.7 .MODEL MOSP PMOS VTO" -0.7 KP z SOU GAMMA" 0.$7 LAMBDA= 0.05 PHI~ 0.8.AC DEC 20 100 lOOMEG

.OP.PRINT AC VM(2) V0Bf2) VP{2l J;:Nl)

voltage were not included, SPICE would find the de solution for VIN = 0 V, which is not in die transition region. Therefore, the small-signal solution would not be evaluated in the transition region. Once the de solution has been evaluated, the wnplitude of the signal applied as the ac input has no influence on the simulation. Thus, it is convenient to U.'le ac inputs of unity in order to treat the output as a gain quantity. Here, we have assumed an ac input of 1.0 V peak. Tbesimulationdesiredisdefinedbythe .AC DEC 20 100 lOOMEG line. This line directs SPICE to make an ac analysis over a log frequency with 20 points per decade from 100Hz to 100 MHz. The o P option has been added to print out the de voltages of all circuit nodes in order to verify that the ac solution is in the desired region. The program will calculate the linear magnitude, dB magnitude, and phase of the output voltage. Figures 3.6-6{a) and 3.6-6(b} show the magnitude (dB} and the phase of this simulation.

2Q

0

-10.2()

30

+ ........,..,......,....,.,_.............,_......"'T"",........""''"..........,..,.I kHz 10 -It< IIIII klfz I MilIQ Mill IIIII Mlft

IW II

10011- Vn

(5.5-13)

222

CMOS AMPUFIERSFigure 5.5-3 (a) Source foUower with a MOS diode load.

louT-OUT

ioUT-OUT

(b) Source follower with a current-sink load.

(a)

(b)

assuming that 1ltN can be taken to V00 and no output current is flowing. However, V71 is a function of Vour so that we must substitute Eq. (3.1-2} into Eq. (5.5-13) and solve for vOUT. To simplify the mathematics, we approximate Eq. (3.1-2) as

(5.5-14)Substituting Eq. (5.5-14) into Eq. (5.5-13) and solving for v0 ur gives2

Vour(max) a Voo

'YI +2

-

Vr01-

'Y1 2 y 'r12 + 4(VJ>o- Vss- Vnn)

(5.5-15)

Using the nominal values of Table 3.1-2 and assuming that VoD -Wssl 2.5 V, we lind that vmrr0.22C~

3. Detcnnine the minimum wluc for tbc ''tail curmtt" (li) l'rom the largest of the two wlucs.t,=SRC.

J, 10 (4. Design for S3 from the maximum inpot voltage specificalioo.

Voo

2 r,

+ \Vssl)

S. Verify !bat lhe pole and zero due to c,., and c... ( 0.67W,4C.,,J will not be domimllltby asaumlngp3 to be grea~lhao lOGB.11 ""

2C..,;~

>

lOGB

6.

Design for S1 (Sl,) to achieve the desiMd GB.

6.3 Design of the Two-Stage Op AmpTABLE 6.3-2 (continued)

275

I .7. PesiJD 1\Jr ~ from tbe minimum input voltage. Fmt calculm Vll.iS(sat) tben findS~.

I. l'hld S. and 1 by letting the secood pole (h) be equal to 2.2 limes GB. 6

Ld V~ ~ VS!k which gives

.9. Allcrnately,l,can be calculated by solving for 56 using

........

8>06 K6V,....(sat)

md d!en using the pR"vious R"lationshlp to find 1.. Of course. the proper mirror between M3 and M4 is no longer guaranteed. 10. llesiga S, to achieve tbc desired cum:nt ratina between lj and 1,..

t IJ.

CJeck gain and power dissipation specificatiOM,

A

=

1,(~,

+ ~.)(~ + ~,)

2/l.aKmt.

l

, 12. If the gain specification i~ not met. lhelllhe curren~ /~ 8lld t. c1111 be decrea~~ed or the WIL ratios or M2 and/or M6 increa.'ied. The pre. viou5 calculations must be rechecked to ensure lhat IIIey have been !lllti~lied. If the power dissipation is too high. then one can only rrducc the currcniS 1, and t. Rcducllon of currents will probably necessitate an increase of some of the WIL ratio. to satisfy input and output swings. _; 13. Simulate tbe circuit to check to see lbat all specifications BR' mer.

________________________________________________________________________________

276-'

CMOS OPERATIONAL AMPUFIERS

that these adjustments to improve noise perfonnance do not adversely affect some Olber important perfonnance parameter of the op amp. The power-supply rejection ratio is to a large degree determined by lhe configuration used. Some improvement in negative PSRR can be achieved by increasing the output resistance of MS. This is usually accomplished by increasing both Ws and 4 proportionately wilhout seriously affecting any other perfonnance. Transistor M7 should be adjusted accordingly for proper matching. A more detailed analysis of the PSRR of the two-stage op amp will be considered in the next section. The following example illustrates the steps in designing the op amp described.

DESIGN OF A TWO-STAG OP AMPUsing the material and device parameters given in Tables 3.1-1 and 3.1-2, design an amplifier similar to that shown in Fig. 6.3-1 that meets the following specifications with a phase IIlW'gin of 60. Assume the channel length is to be 1 IJ.m.

A,> SOOOVIVGB=5MHz V.,.t range= 2 V

V00 = 2.5VCL = IOpF

ICMR = -1 to2V

Vss = -2.5V SR > 10 V/IJ.S Pdi,. :S 2 mW

ljtiMu.J,IThe first step is to calculate the minimum value of the compensation capacitor Cc, which isCc > (2.2/10)(10 pP) = 2.2 pFChoose Cc as 3 pF. Using the slew-rate specification and C,. calculate 1 , 5

Next calculate (WILh using ICMR requirements. Using Eq. (6.3-12) we have (w.ZL) 3 -

(50

X

30 X 10-6 10- )[2.5 - 2 - 0.856

+ 0.55] 2 -

- 15

Therefore,(W/Lh = (W/L)4 = 15

Now we can check the value of the mirror pole, p 3, to make sure that it is in fact greater than 10GB. Assume the Coa = 2.47 fF/IJ.m2 The mirror pole can be found as- g., 3 - Y2K;Si3 9 P3 .., 2C,.3 = 2(0.667) W~Co, = 2.81 X 10 radls

or 448 MHz. Thus, p 3 and z3 are not of concern in this design because p 3 >> I0 GB.

6.3 Design of the Two-Stage Op Amp The next step in the design is to calculate Kml using Eq. (6.3-13).

277

Therefore, (W/L) 1 is (W/L) 1 = (WILn

= 2KNJ

g!l

=1

2

(94.25)2 . IIO. = 2.79"" 3.015

Next, calculate VI>SS using Eq. (6.3-15).

t

VDss = (-1)- (-2.5)- ~ 30XJ0 6110

6

x to-

3

. -0.85

= 0.35 V

Using VDSS calculate (W/L)s from Eq. (6.3-16).2(30 x w- 6> (W/L)s = (110 X 10-6)(0.35l

= 4.49 .,. 4.5

From Eq. (6.2-20), we know that8m6 2: I Ogml o;: 942.5

JLS

Assuming that g..,= 942.5 ....Sand calculating g""' as 150 .,..s, we use Eq. (6.3-18) to get

s6 = s4 ~ =8m4

8m6

t5 - - = 94.25 = 94

942.5 150

Calculate / 6 using Eq. (6.3-19).l6

=

(942 5

(2)(50 X lO 6 )(94}

.

X

10- 6 ) 2

= 94.5 .,.A ... 95 AIL

Designing S6 by using Eq. (6.3-20) gives S6 "" 15. Since the WIL ratio of 94 from above is greater, the maximum output voltage specification will be met. Finally, calculate (W/L}, using Eq. (6.3-21 ).(W/L},

= 4.5 G~ !~=:) = 14.25 =

:

14

Let us check the Vou1(min} specification although the W/L ofM7 is large enough that this is probably not necessary. The value of Vnu1(min} isVm;n(out)

= V057 (sat) = \1'~ = 0.351 V

{"'2-95

which is less than required. At this point. the first-cut design is complete.

278

CMOS OPERATIONAL AMPLIFIERS

The power dissipation can be calculated as

Pm .. = 5 V (30 }LA+ 95fLA) = 0.625 mWNow check to see that the gain specification has been met.

A = " 30

(2)(92.45X

X

101 )(942.5 X 10- 6)X

10 (0.04

6

+ 0.05}95

10- 6(0.04

+ 0.05)

= 7696V/V

which meets specifications. If more gain were desired, an easy way to achieve it would be to increase the Wand L values by a faclOr of 2, which because of the decreased value of>.. would increase the gain by a factor of 20. Figure 6.3-3 shows the results of the first-cut design. The next phase requires simulation.

Vss=-2.5 V Figure 63-3 Result of Example 6.3-l.

Nulling Resistor, Miller CompensationIt may likely occur that the undesired RHP zero may not be negligible in the above design JlfO" cedure. This would occur if the GB specification was large or if the output stage transconductance (gm6) was not large. In this case, it becomes necessary to employ the nulling resistor compensation method. We shall use the results of Section 6.2 to illustrate how to apply this solution. Section 6.2 described a technique whereby the RHP zero can be moved to the left halfplane and placed on the highest nondominant pole. To accomplish this. a resistor is placed in series with the compensation capacitor. Figure 6.3-4 shows a compensation scheme using transistor MS as a resistor. This transistor is controlled by a control voltage Vr that adjusts the resistor so that it maintains the proper value over process variatioliS [6]. With the addition of the resistor in the compensation scheme, the resulting poles and zeros are [see Eqs. (6.2~37) to (6.2-40)]PI~---=---

Cm2

g..,[

A.Cc

A.C.

(6.3-23)

6.3 Design of the Two-Stage Op Amp

279

I

VssFigure 6.3-4 CMOS two-stage op amp using nulling resistor compensation.

(6.3-24)

(6.3-25)

(6.3-26) where A.= 8mt8mtJR,R11 In order to place the zero on top of the second pole (Pi), the following relationship musl hold: (6.3-27) The resistor R, is realized by the transistor MS. which is operating in the active region because the de current through it is zero. Therefore, R, can be written as

R - _av_rus_l - ----~-.,....-- - iiiDB v.,...-o - KJ.Ss(Vsos - fVrpi)The bias circuit is designed so that voltage VA is equal to V8 As a result.

(6.3-28)

(6.3-29)In the saturation region

(6.3-30)

280

CMOS OPERATIONAL AMPLIFIERS

Substituting into Eq. (6.3-28) yields

R10 (VI,.s)

323

'

'

Simulation (Elcample 6.6-1)10,000 SMHz +2.4V,-l.2V +10.-7(V/1J.S) 0.625mW +2.3 V, -2.2 V

Opeo-loop gainGB(MHz)

.'"

ICMR (volts)

Slew filii: (V/!J.S) P lmW)

.I' = 0.01 V -. Also, assume that the minimum device dimension is 2 f)om and choose the smallest devices possible. Design C, and R, to give GB = 1 MHz and to eliminate the influence of the RHP zero. How much load capacitance should this op amp be capable of driving without suffering a degradation in the phase margin? What is the slew rate of this op amp? Assume Voo=-V~"'2.SVandR8 = IOOkil. 6.3-9. Use the electrical model parameters of the previous problem to design W3 , L3, W4 Z... W5 , ~- C.., and R, of Pig. P6.3-8 if the de currents are in creased by a factor of 2 and if W1 = ~ = W = 2 Lz = 2 ~to obtain a low-frequency. differential

wbereS1 "' W/L,.

'iJ.t Draw a schematic of the op amp similar to Fig. 6.3-1 but using p-channel input devices. Assuming that same bias currents flow in each circuit. list all characteristics of these two circuits !bat might be different and teD which is better or worse !han the oth