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CMOS Analog Design LECTURE NOTES Prof. Dr. Bernhard Hoppe

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Page 1: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

CMOS Analog DesignLECTURE NOTES

Prof. Dr. Bernhard Hoppe

Page 2: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 2

Introduction

Page 3: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 3

Analog Integrated

Circuits

Design Steps:

1.

Definition2.

Implementation

3.

Simulation4.

Geometrical

description

5.

Simulation including

the

geometrical

parasitics6.

Fabrication

7.

Testing

and verification

Page 4: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 4

Analog Integrated

Circuits

Design:Tools & Methods:

Simulation•

Design Capture

Hand Calculations

Bottom

Up Flow

Page 5: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 5

Discrete

Analog Circuit

Design-

Using

breadboards

Integrated

Analog Circuit

Design -

Using

computer

simulation

techniques

Page 6: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 6

Pros

and Cons

of Computer simulationsAdvantages:

1.

No breadboards

required2.

Every

node

in the

circuit

is

accessible

3.

Feedback loops

may

be

opened4.

Modification

of the

circuit

is

easy

5.

Modification

of processes

and ambient conditions

is possible

Page 7: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 7

Pros

and Cons

of Computer simulationsDrawbacks:

1.

Accuracy

of models2.

Convergence

problems

of the

simulator: circuit

may

not

converge

to a stable

operating

point 3.

Time required

to perform

simulations

of large circuits

4.

Use

of the

computer

as a substitute

for

thinking

Page 8: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 8

The

PN junction

Page 9: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 9

PN junctionUsed

for:

1.

Insulation

purposes2.

Diodes

and zeners

3.

Basic structure

of MOS and Bipolar transistor

Page 10: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 10

Important

features

for

device

propertiesAnd modelling

aspects

Depletion

region

width•

Depletion

region

capacitance

Reverse bias

breakdown

voltage•

Diode equation

iD

Vs VD

Page 11: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 11

Diode Model:

Step

functionchange

of impurity

concentration

=> Idealization

Page 12: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 12

Diode Model:

Space

chargewidthXd

= Xn

- Xp

Equilibriumcondition:Field

forces

=

Diffusion forces

Page 13: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 13

Xd

= ?, E0

= ?, Φ0

= ?

Due

to electrical

neutrality, the

charge

on either

side

of the

junction

must

be

equal

Thus,qND

Xn

= qNA

Xp

where

q = 1.6 x 10-19

C

To calculate

the

fieldstrength

from

the

charge,Gauss

equation:

dE(x)

= qNdx

εSi

where

εSi = 11.7x8.85x10-14

F/cm –

Si dielectric

constant

Page 14: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 14

On integration

we

get

the

max

electric

field

at thejunction, E0

E0

= 0

∫E0dE = Xp

∫0

–qNA

/ εSi dx

Therefore, E0 = -qN

DX

n

=

qNAX

pεSi εSi

Page 15: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 15

Voltage

is

found

by

integrating

the

electric

field, resultingin

Φ0 - VD

= -E

0(X

n – X

p)

2

where

VD = applied

external

voltageΦ0 = barrier

potential

Page 16: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 16

Barrier

potential Φ0 is

given

as

Φ0 = (kT / q) ln

(NA

ND / ni2) = (Vt

) ln

(NA

ND / ni2)

where

k

= Boltzmann‘s

constant

1.38 x 10-23

J/K

ni

= intrinsic

concentration

of silicon1.45 x 1010

/cm3

at 300K

Vt

= 25.9 mV at 300K

Page 17: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 17

Using

equations

for

E0 and Φ0 – VD

, and solving

for

Xnor

Xp

we

get

Xn

= ( 2εSi(Φ0

– VD)NA )1/2

qND(N

A

+ ND)

and Xp

= -

( 2εSi(Φ0

– VD)ND )1/2

qNA(N

A

+ ND)

Page 18: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 18

Width

of the

depletion

region

Xd

is

given

as

Xd

= Xn

– Xp

= ( 2εSi(NA

+ ND) )1/2

(Φ0 - VD

)1/2

qNAN

D

Page 19: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 19

Conclusions:

1.

Xd

is

proportional to (Φ0 - VD

)1/2 or

(-

VD

)1/2

2.

If

NA >> ND then

Xd

~ Xn

3.

If

ND >> NA then

Xd

~ Xp

4.

Lower

doped

side

determines

Xd

Page 20: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 20

Depletion

charge

and depletion

layercapacitance:Depletion

charge

Qj

is

given

as

Qj

= |AqNA

Xp

| = AqND

Xn

Qj

= A

( 2εSiqNAND

)1/2

(Φ0 - VD

)1/2

(NA+N

D)

where

A is

the

cross sectional

area

of the

pn

junction

Page 21: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 21

Depletion

charge

and depletion

layer

capacitance:Magnitude

of the

electric

field

at the

junction

E0

= ( 2qNAND

)1/2

(Φ0

-

VD

)1/2

εSi(N

A+N

D)

Page 22: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 22

Depletion

charge

and depletion

layer

capacitance:Depletion

layer

capacitance

Cj

is

given

as

Cj

= dQj

= A

( εSiqNAND

)1/2 (Φ0 - VD

)-1/2

dVD

2(NA+ND)

=

Cj0 [1-(VD /Φ0)]m

Page 23: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 23

Depletion

charge

and depletion

layer

capacitance:where

Cj0 is

capacitance

when

VD

= 0m is

a grading

coefficient

m = 1/2 => step

junctionm = 1/3 => linearly

graded

junction

1/3 <= m <= 1/2 => real junctions(experimental fit)

Page 24: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 24

Plot of the

space

charge

capacitance:

Ideal

Actual

Page 25: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 25

Example:

Calculate

Xd

, Xn

,Xp

, E0

, Cj0

, and Cj

for

VD

= -4 V,NA = 5 x 1015

/cm3,

ND = 1020

/cm3,

A = 10 μm x 10 μmTemperature

= 300 K

Page 26: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 26

Breakdown

voltage

of a reverse

biased

diode:

BV

= ( εSi(NA

+ ND) )(Emax

)2

2qNAN

D

assuming

|VD > Φ0

|Emax

is

the

maximum

electric

field

that

can

existacross

the

depletion

region

For silicon, Emax

~ 3

x 105

V/cm

Page 27: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 27

Breakdown

mechanisms:

1.

Avalanche

breakdown: Multiplication

of carrier concentrations

due

to collisions

of minority

carriers

with

the

lattice

electrons. It

has a negative temperature

coefficient.

2.

Zener

breakdown: Valence

band breakdown. It occurs

at comparatively

lower

voltages. It

does

not

depend

upon

temperature

(tunneling

effect).

Page 28: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 28

Breakdown

mechanisms: Reverse biased

current

(due

to avalanche

effect)

iRA

= MiR

=

( 1 ) x iR[1-

(VR /BV)n]

where

M = avalanche

multiplication

factorn = empirical

parameter

3 <= n <= 6

iR

= ‘normal‘

reverse

current

Page 29: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 29

Typical

pn

junction

characteristics:

Page 30: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 30

Voltage-Current

relationship

of diode:Impurity

concentration

profile

for

diffused

pn

junction

under

forward

bias: Minorities

pile

up at the

boundaries

of the

depletion

region!

Page 31: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 31

Voltage-Current

relationship

of diode:Minority

carrier

concentration

for

diffused

pn

junction:no applied

voltage: no excess

minority

carrier

concentration: np

(0) = np0

and pn

(0) =pn0Reverse biased

(vD

negative): minority

carrier concentration

is

depleted

below

the

equilibrium

value!Current

in reverse

biased

pn-junction

is

a diffusion

current, depending

on the

slope

of the

minority carrier

concentration

at the

boundaries

of the

depletion

region.

Page 32: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 32

Voltage-Current

relationship

of diode:Terminologies: pn0

and np0 = equilibrium

concentrations

of the

minoritycarriers

in n-type

and p-type

regions

pn

(0) = pn0 exp(VD

/Vt

) is

value

of the

excessconcentration

at x = 0

np

(0) = np0 exp(VD

/Vt

) is

value

of the

excessconcentration

at x‘

= 0

Page 33: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 33

Voltage-Current

relationship

of diode:The

total current

in an pn

junction

diode

is

given

as

iD

= qA

( Dppn0 +

Dnnp0

)(exp(VD

/Vt

) –

1)Lp

Ln

Or

iD

= Is

(exp(VD

/Vt

) –

1)

Page 34: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 34

Voltage-Current

relationship

of diode:where

Is

= qA

( Dppn0 +

Dnnp0

)Lp

Ln

is

a constant

called

the

saturation

currentA = area

of the

pn

junction

Dp

= diffusion

constant

of holes

in n-type

semiconductorDn

= diffusion

constant

of electrons

in p-typesemiconductor

Lp

= diffusion

length

for

holes

in n-type

semiconductorLn

= diffusion

length

for

el. in p-type

semiconductor

Page 35: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 35

Example:

Calculate

the

saturation

current

of a pn

junction

diodewithNA = 5 x 1015

/cm3, ND = 1020

/cm3,

A = 1000 μm2 , Dn

= 20 cm2 / s,Dp

= 10 cm2 / s, Ln

= 10 μm,Lp

= 5 μm.

Page 36: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 36

The

MOS transistor

Page 37: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 37

N-well

technology:Physical

structure

of an n-MOS

and p-MOS

device:

Page 38: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 38

N-well

technology:

pMOS

formed

within

a lightly

doped

n-

material

called

the

N-well•

nMOS

formed

within

a lightly

doped

p-

substrate

Both

types

of transistors

are

four

terminal

devices•

The

p-bulk

connection

is

common

throughout

the

integrated

circuit

and is

connected

to Vss

(the

most negative supply)

Multiple n-wells

can

be

connected

to different potentials

(but

+ve

w.r.t. Vss

)•

nMOS

and pMOS

devices

are

complementary:

nMOS

equations

can

be

mapped

to pMOS equations

Page 39: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 39

nMOS

threshold

voltage

equation:Cross section

of an n-channel

transistor

with

all

terminals

grounded:

Page 40: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 40

nMOS

threshold

voltage

equation:Terminologies:Cox

= Area

specific

oxide

capacitance

in F/m2

ΦF

= Equilibrium

electrostatic

potential (Fermi

potential) in the

semiconductor

ΦS

= Surface

potential of the

semiconductorΦMS

= Difference

in the

work

functions

between

the

gate material and bulk

silicon

in the

channel

region

QSS

= Undesired

+ve

charge

present

in the

interfacebetween

the

oxide

and the

bulk

silicon

Qb0

= Fixed

charge

in the

depletion

regionVSB

= Substrate bias

(VSource

- VSubstrate

)

Page 41: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 41

nMOS

threshold

voltage

equation:Threshold

voltage

VT consists

of following

contributions:

1.

ΦMS

= ΦF (substrate) -

ΦF (gate)where

ΦF (metal) = 0.6 V

2.

[-2ΦF – (Qb

/Cox

)]: voltage

required

to change

the surface

potential and offset the

depletion

layer

charge

3.

Undesired

+ve

charge

QSS due

to impurities

and imperfections

at the

interface

must

be

compensated

by

a gate voltage

of –

QSS /Cox

Page 42: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 42

nMOS

threshold

voltage

equation:Summation of the

contributions:

VT = ΦMS

+ [-2ΦF – (Qb

/Cox )] + (–

QSS /Cox )= ΦMS

- 2ΦF – (Qb0 /Cox ) –

(QSS /Cox ) -

(Qb

- Qb0 ) / Cox

The

threshold

voltage

can

be

rewritten

as

where

VT0

= ΦMS

- 2ΦF – (Qb0 /Cox ) –

(QSS /Cox )

( )0 2 2T T F SB FV V Vγ φ φ= + − + − −

Page 43: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 43

Body effect

coefficient:The

body

factor, body

effect

coefficient, or

bulk-threshold

parameter

γ

is

defined

as

γ

= √2qεSiNA

(unit: V1/2)Cox

Page 44: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 44

Sign

conventions

in threshold

voltage

equation:

n-channel

device p type

substrate

p-channel

device n type

substrate

Parameter

ΦMS

_ _ metal

_ _ n+ Si

+ + p+ Si

_ + ΦF

_ + Qb0

, Qb

+ + QSS

+ _ VSB

+ _ γ

Page 45: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 45

Example:

Calculate

the

threshold

voltage

and body

factor

γ

for

an n-channel

transistor

with

an n+-silicon

gate for

no

substrate

bias

and a Vsb

od

2V if

tox

= 200 Angström

, NA = 3 x 1016

/cm3,

gate doping

ND = 4 x 1019

/cm3,

surface

charge

density

NSS = 1010

/cm2,

temperature

= 300 K.

Page 46: CMOS Analog Design Lecture Notes - hoppe.eit.h-da.dehoppe.eit.h-da.de/CMOS-Analog/CMOS Analog Design... · Prof. Dr. Hoppe CMOS Analog Design 5 Discrete Analog Circuit Design-Using

Prof. Dr. Hoppe CMOS Analog Design 46

Solution (1):

tox

= 200 Angström, NA = 3 x 1016

/cm3,

ND = 4 x 1019

/cm3,

NSS = 1010

/cm2,

Temperature

of 300 K means•

kB

T/q = 0.026V (Temperature

Voltage)•

ni

= 1.45 x 1010

/cm3 (Intrinsic

Carrier

Concentration)

011,7Siε ε=

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Prof. Dr. Hoppe CMOS Analog Design 47

Solution (2):

Formula

for

the

threshold-voltage:

with

the

Fermi-potential:

The

zero

substrate

bias

thershold

voltage

is:

The space charge in the channel

The

work-function

difference

( )0 2 2T T F SB FV V Vγ φ φ= + − + − −

lnsub iBF

A

nk Tq N

φ =

0 2 2b A Si FQ q N ε φ= − ⋅ ⋅

00 2 b SS

T MS Fox ox

Q QVC C

φ φ= − − −

lngate B DF

i

k T Nq n

φ =

P- doped

N- doped

sub gateMS F Fφ φ φ= −

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Prof. Dr. Hoppe CMOS Analog Design 48

Solution (3):The

work-function

difference

and

the

space

charge

induced

potential in the

channel0

2

2

2

2

2 2

2 (1.6 19) (3.0 16) 11.7 (8.854 14) 0.76 /3.9 (8.854 14) /(200.0 10) /

(8.7 8) / 0.51(170.0 9) /

A Si Fb

oxox

ox

q NQC

t

e e e As cme e As Vcm

e As cm Ve As Vcm

ε φε

− ⋅ ⋅=

− ⋅ − ⋅ + ⋅ ⋅ − ⋅=

⋅ − −

− −= = −

1.45 10 4.0 190.026 ln 0.026 ln3 16 1.45 10

0.38 0.57 0.95

sub gateMS F F

e eV Ve e

V V V

φ φ φ + += − = − =

+ +− − = −

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Prof. Dr. Hoppe CMOS Analog Design 49

Solution (4):The

body-factor

reads

So the

threshold

voltage

without

substrate

bias

is

and for

Vsb

= 2V we

get:

0 0.95 0.76 0.51 0.01 0.33TV V V V V V= − + + + =

02 2 0.51 0.58

0.872A Si F b

ox F ox

q N Q V VC C

ε φγ

φ

⋅ ⋅ −= = = =

0.33 0.58( 0.76 2.0 0.76) 0.78TV V V V= + + − =

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Prof. Dr. Hoppe CMOS Analog Design 50

Current

voltage

relation

of the

MOS transistor:1. Linear mode: -

Sah equation

iD

= (W/L)μn

Cox

[(VGS – VT

) –

(VDS

/2)] VDS

holds

good for

(VGS – VT

) >= VDS and VGS >= VT

2. Saturation

mode:

iD

= (W/2L)μn

Cox

[(VGS – VT

)2]

holds

good for

(VGS – VT

) <= VDS

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Prof. Dr. Hoppe CMOS Analog Design 51

Device

transconductance

parameter:

The

factor

μn

Cox

is

defined

as the

devicetransconductance

parameter, given

as

K‘

= μn

Cox

= μn

εox

/ tox

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Prof. Dr. Hoppe CMOS Analog Design 52

CMOS device

modeling

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Prof. Dr. Hoppe CMOS Analog Design 53

Pinch-off

Saturation:

Voltage

drop in the

channel

is

constant•

The

Field

pulling

the

electrons

from

the

source

remains

constant•

iD

remains

constant•

Electrons

are

injected

from

the

channel

into

the

space

charge

region

=> ballistic

transport

to drain node

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Prof. Dr. Hoppe CMOS Analog Design 54

How

large is

the

saturation

current

?:

Saturation

condition:VDS = (VGS – VT

)

Saturation

current

equation:

iD

= (W/2L)μn

Cox

[(VGS – VT

)2]

holds

good for

0 <= (VGS – VT

) <= VDS

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Prof. Dr. Hoppe CMOS Analog Design 55

Output characteristics

of the

MOSFET for VT

= 1V:

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Prof. Dr. Hoppe CMOS Analog Design 56

Channel

length

modulation

effect:

Constant

saturation

current

only

for

long

channel devices

i.e. Pinch-off

point „close“

to the

drain

Long channel

devices

have

length

L >= 10 μm•

For lengths

shorter

than

1 μm, short

channel

effects

are

observed•

Most important

effect: Channel

length

modulation

effect

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Prof. Dr. Hoppe CMOS Analog Design 57

Channel

length

modulation

effect:

In reality, the

saturation

current

depends

linearly

on VDS

Modified

current

equation:

iD

= (W/2L) μn

Cox

[(VGS – VT

)2 (1 + λVDS

)]

where

λ

= channel

length

modulation

factor

(unit: 1/V)

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Prof. Dr. Hoppe CMOS Analog Design 58

Kleinsignalparameter beschreiben das Verhalten eines Systems in der Nähe eines Arbeitspunktes

In Sättigung

gilt für die Abhängigkeit des Drainstroms von der Gate Source Spannung (Vds

und Vsb

fest)

Eingangsleitwert

Kleinsignalparameter

( )GS THm n oxWg C V VL

μ= −

Dm

gsds

I festgV

V∂=∂

Doxn ILWC2μ= VV

I2THGS

D

−=

( )VVfg THGSm −=∴Aν

spannungsabhängig

Nichtlinearität!

DmRg−=

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Prof. Dr. Hoppe CMOS Analog Design 59

In Sättigung gilt für die Abhängigkeit des Drainstroms von der der Drain-Source-Spannung bei fester Gate

Source Spannung

Ausgangsleitwert

Kleinsignalparameter

( )1 ²2 GS THds n ox D

Wg C IV VLμ λ λ= ⋅ ≈ ⋅−

Dds

dsgs

I festgV

V∂=∂

1/gds

= ro der Ausgangswiderstand des Transistors

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Prof. Dr. Hoppe CMOS Analog Design 60

In Sättigung gilt für die Abhängigkeit des Drainstroms von der

der Source-Bulk-Spannung

bei fester Drain-Source-

und Gate Source SpannungSubstratabhängigkeit

Kleinsignalparameter

2 2D D D T

mbs m mBS SB T SB F SB

I I I Vg g gVV V V V

γ ηφ

⎛ ⎞⎛ ⎞∂ −∂ ∂ ∂= = = − = ≡ ⋅⎜ ⎟⎜ ⎟∂ ∂ ∂ ∂ +⎝ ⎠⎝ ⎠

&gs

Ddsmbs

SB

I V VgV

fest∂=∂

Ändert sich VSB

, dann ändert sich die Einsatzspan- nung

und damit der Strom im Transistor!

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Prof. Dr. Hoppe CMOS Analog Design 61

In Sättigung gilt für die Abhängigkeit des Drainstroms von der der Drain-Source-Spannung bei fester Gate

Source Spannung

Kleinsignalparameter Leitwerte gm

und gds

( )1 ²2 GS THds n ox D

Wg C IV VLμ λ λ= ⋅ ≈ ⋅−

Dds

ds

I festg gsVV∂

=∂

1/gds

= ro der Ausgangswiderstand des Transistors

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Prof. Dr. Hoppe CMOS Analog Design 62

Transfer characteristics

of the

MOSFET: iD

plotted

against

VGS for

fixed

VDS

, VT = 2V

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Prof. Dr. Hoppe CMOS Analog Design 63

Short channel

effects:

As technology scaling

reaches

channel

lengths shorter

than

1 μm, second order effects

become

significant•

MOSFETs

with

L < 1 μm

are

called

short

channel

devices•

Main effects:

1. velocity

saturation2. threshold

voltage

variation

3. hot carrier

effect

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Prof. Dr. Hoppe CMOS Analog Design 64

Review

of classical

derivation

of iD

: Gradual Channel

Approximation:

x-direction

perpendicular

to the

surface,y-direction

from

0 to L: the

channel

VT

is

assumed

to be

constant

along

the

channelElectrical

field

in y-direction

much

larger than

the

field

in x-direction

Current flow in the channel in y-direction onlyThe

whole

channel

is

assumed

to be

inverted: VGS > VT

VGD = VGS

-

VDS

> VT

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Prof. Dr. Hoppe CMOS Analog Design 65

Review

of classical

derivation

of iD

:

The

mobile charge

in the

channel

flows

along

the

y-direction

driven

by

EyThe

mobile charge

at position

y depends

on VGS

and the

channel

voltage

Vc

(y) is

Q(y) = -Cox

[VGS - Vc

(y) -

VT

] ...(1)

Note:The

channel

is

tapered

as we

move

from

source to drain as the

gate to channel

voltagecausing

surface

inversion

is

smaller

at the

drain end!

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Prof. Dr. Hoppe CMOS Analog Design 66

Review

of classical

derivation

of iD

:

The

incremental

resistance

of the

segment

dy

reads:

……2

Current

iD

is

flowing

from

source and drain in y-direction

(1-dimensional model)Voltage

drop along

dy: …….3

( )n

dydRW Q yμ

= −⋅ ⋅

( )D

Dn

i dydV i dRW Q yμ

⋅= ⋅ = −

⋅ ⋅

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Prof. Dr. Hoppe CMOS Analog Design 67

Review

of classical

derivation

of iD

:

Integration along

y from

0 to L yields

:

We

insert

equ.1 for

Qc

(y) and obtain

Assuming

that

the

Channel

Voltage

is

the

only

voltage

depending

on y we

obtain

for

the

current

iD

0 0

( )DSVL

D n Ci dy W Q y dVμ= − ⋅∫ ∫

( )0

( )DSV

D ox n GS c T ci L W C V V y V dVμ= ⋅ − −∫

( ) 222D n ox GS T DS DSWi C V V V VL

μ= ⋅ − −

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Prof. Dr. Hoppe CMOS Analog Design 68

Review

of classical

derivation

of iD

:

iD

depends

on µn

and Cox

= εox

/tox

: technology dependentand on geometry

W and L, channel

width

(W) and length

(L)

W/L is

the

most

important

design

parameter

Example: µn

= 600cm2/Vs Cox

= 7,0*10-8F/cm2 W=20µm L = 2µm VT

=1.0V

iD

curves

are

inverted

parabolas

with

maximum

at VDS

=VGS

-VT

Beyond

this

voltage: negative differential transconductanceNot observed

in real MOSFETs

( ) 2 20,21 / 2 1,0D GS DS DSi mA V V V V= − −

( ) 222D n ox GS T DS DSWi C V V V VL

μ= ⋅ − −

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Prof. Dr. Hoppe CMOS Analog Design 69

Review

of classical

derivation

of iD

:

( ) 222D n ox GS T DS DSWi C V V V VL

μ= ⋅ − −

Dashed

curves

represent

unphysical

behaviour!

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Prof. Dr. Hoppe CMOS Analog Design 70

Review

of classical

derivation

of iD

:iD

-formula

derived

for

complete

channel

is

inverted

This

is

the

linear operating

regionnot

valid

beyond

the

linear/saturation

boundary:

Above

VDSAT current

increases

no more

GS T

GD GS DS T

V VV V V V

≥= − ≥

DS GS T DSATV V V V≥ − =

( )

( )

2

2

22

,2

D n ox GS T DSAT DSAT

n ox GS T

Wi C V V V VL

W C V V saturation currentL

μ

μ

= ⋅ − − =

= ⋅ −

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Prof. Dr. Hoppe CMOS Analog Design 71

Channel

length

modulationIf

VDS

> VDSAT

the

channel

is

no longer

inverter

at the

drain end. Surface

potential is

too

low: Pinch

off effect!

Above

VDSAT the

channel

charge

at the

drain end becomes

zero

(very

small)

Q(y=L) ≈

0

DS GS T DSATV V V V≥ − =

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Prof. Dr. Hoppe CMOS Analog Design 72

Channel

length

modulationSaturation

effect

= onset

of pinch-off

of channel

at the

drain end y = L

If

VDS

> VDSAT the

pinch

off at L‘

= L -

ΔL

Pinched

off part

of channel

is

depleted:

Gradual channel

approximation

valid

from

y = 0 to y = L‘:

As L‘

reduces

with

increasing

VDS

further

beyond

VDSAT

iD

is

growing

in saturation

with

drain-source-voltage

( ) 0 '( ')c DSAT

Q y für L y LV y L V

= < ≤= =

( ) 2

2 'D n ox GS TWi C V VL

μ= ⋅ −

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Prof. Dr. Hoppe CMOS Analog Design 73

Channel

length

modulationWe

may

rewrite

the

saturation

current

ΔL may

be

shown

to be

proportional to

There

is

the

following

empirical

relationship

DS DSATL V VΔ −∼

( ) 2121

D n ox GS TWi C V VL L

L

μ

⎛ ⎞⎜ ⎟

= ⋅ −⎜ ⎟Δ⎜ ⎟−⎝ ⎠

( ) ( ) ( ) 2 2

1 1 1

1 12 21

DS DS

D n ox GS T n ox GS T DS

L V with VL

W Wi C V V C V V VL L LL

λ λ

μ μ λ

Δ− ≈ − ⋅ ⋅

⎛ ⎞⎜ ⎟

= ⋅ − ≈ ⋅ − + ⋅⎜ ⎟Δ⎜ ⎟−⎝ ⎠

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Prof. Dr. Hoppe CMOS Analog Design 74

Channel

length

modulation

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Prof. Dr. Hoppe CMOS Analog Design 75

Equivalent

derivation

of iD

using

gradual channels:

iD

= -

vn

(y)Q(y)W

...(2‘)

Current

is

charge

at surface

times

width

of the

channelmoving

with

the

electron

velocity

vn

~ E, therefore

vn

= -

μn

E(y) = -

μn

dV/dy

...(3‘)

Substituting

eq.(1) and (3) in (2) we

get

iD

dy

= μn CoxW [VGS -

V(y) -

VT

]

dV ...(4‘)

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Prof. Dr. Hoppe CMOS Analog Design 76

Review

of classical

derivation

of iD

:

Integrating

eq.(4) along

the

channel

for

0 to L gives

iD

= (W/L)μn

Cox

[(VGS – VT

) –

(VDS

/2)] VDS

This

derivation

shows, that

drain current

is

depending

on the

carrier

velocity, which

was assumed

to be

the

drift velocity

as in conductors

like

copper.However

the

velocity

saturates

at strong

fields

giving

rise

to the

velocity

saturation

effect

in short

channel transistors!

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Prof. Dr. Hoppe CMOS Analog Design 77

Velocity saturation

effect: Measurements

of vn

as a function

of E

The most important short-channel effect in MOSFETs is the velocity saturation of carriers in the channel.

A plot of electron drift velocity versus electric field is shown above.

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Prof. Dr. Hoppe CMOS Analog Design 78

Impact of velocity

saturation:Velocity of electrons as a function of E:

vn

= μnE

for E < Ec 1 + E/Ec

vn

= vsat

for E >= Ec

where Ec

is the critical electric field at which velocity saturation occurs Inserting a factor in the equation of iD

, we get:

iD

= K(VDS

)(W/L)μn

Cox

[(VGS – VT

) –

(VDS

/2)] VDS

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Prof. Dr. Hoppe CMOS Analog Design 79

Impact of velocity

saturation:where

K(VDS

)

= 1

1 + VDS/EcL

is a SPICE parameter for modeling.

For L >> 1 μm, K(VDS

) ~ 1For short channel devices, K(VDS

) < 1 resulting

intosmaller

iD

than expected

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Prof. Dr. Hoppe CMOS Analog Design 80

Impact of velocity

saturation:How large is the current?Assume that carrier velocity has reached limit value vn

= 107

cm/s The

effective

channel

length

Leff

will be

shorter

than

L:

Since

the

voltage

at Leff

is

VDSAT

we

have:

Drain current

is

independent of channel

lengthDrain current

is

linear with

drain-source-voltage

0

( ) ( ) ( ) ( )effL

D n ni sat W v sat q n x dx W v sat Q= ⋅ ⋅ ⋅ = ⋅ ⋅∫

0

( ) ( ) ( ) ( )effL

D n n ox DSATi sat W v sat q n x dx W v sat C V= ⋅ ⋅ ⋅ = ⋅ ⋅ ⋅∫

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Prof. Dr. Hoppe CMOS Analog Design 81

Impact of velocity

saturation:

Short channel transistors enter the saturation region before VDS

= VGS – VT

[ ]

[ ]

2

( ) ( )

( )2

23

D n ox DSAT n DSAT ox DSAT

DSATD ox n GS T DSAT

DSAT

DSAT GS T

i sat W v sat C V W µ V C V

VWi sat K C µ V V VL

gleichsetzen und nach V auflösen

V K V V

= ⋅ ⋅ ⋅ = ⋅ ⋅ ⋅

⎡ ⎤= ⋅ ⋅ − −⎢ ⎥

⎣ ⎦

= ⋅ −

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Prof. Dr. Hoppe CMOS Analog Design 82

Impact of velocity

saturation

(second impact):

For short

channel

devices, K(VGS – VT

) < 1Two

transistors

with

same

W/L and VGS = VDD will have

the following characteristics:

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Prof. Dr. Hoppe CMOS Analog Design 83

Velocity saturation

(0,25µm CMOS)

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Vdrain (V)

0.0

0.5

1.0

1.5

2.0

Cur

rent

(mA)

iD(MMN1)x1= x2= dx=-3.83m 3.29 3.30

NMOS_Drainstrom

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Vdrain (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Cur

rent

(mA)

iD(MMN1)x1= x2= dx=-3.83m 3.29 3.30

NMOS_Drainstrom

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Vdrain (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Cur

rent

(mA)

iD(MMN1)x1= x2= dx=-3.83m 3.29 3.30

NMOS_Drainstrom

W/L=2.5µm/0,25µm, Imax

= 2,2mAW/L=25µm/2,5µm,

Imax

= 5,4mA

W/L=10µm/1,0µm, Imax

= 4,3mA

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Prof. Dr. Hoppe CMOS Analog Design 84

A simple model

for

hand calculations:(1) Velocity saturation occurs abruptly at E = Ec

vn

= μn

E for E < Ec

vn

= vsat

= μn

Ec

for E >= Ec

(2) VDSsat

at which Ec

is reached is given asVDSsat

= LEc = Lvsat

/μn

(3) Approximate saturation current for a short channel device is given as

iDsat

= vsat

CoxW [VGS – VT

– VDSsat

]

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Prof. Dr. Hoppe CMOS Analog Design 85

iD

Vs VGS

characteristics

for

long

and short

channel devices:

Two

transistors, both

with

W/L = 1.5 will have the following characteristics:

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Prof. Dr. Hoppe CMOS Analog Design 86

Threshold

voltage

variations

in long

and short channel

devices:

Long channel nMOS: VT

= f (technology, source –

bulk

voltage)Short channel nMOS:

VT

= f (technology, source –

bulk

voltage, L, W, VDS

)

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Prof. Dr. Hoppe CMOS Analog Design 87

Disadvantages

of short

channel

devices:

Reduction

in gain•

Cannot

switch

off properly

due

to reduction

in VT

More

leakage

current

in the

„off“

condition•

More

dependence

on transistor

variables

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Prof. Dr. Hoppe CMOS Analog Design 88

Hot carrier

effect:•

During

the

last decade, transistor

dimensions

were

scaled

down but

not

the

power

supply•

Increase

in the

field

strength

causes

increase

in the

kinetic

energy

of electrons

(hot electrons)•

Some

of the

electrons

become

so ‘hot‘

that

they

can

jump

over

the

barriers

and tunnel

into

the

oxide•

Electrons

are

trapped

in the

oxide

and these

additional charges

increase

VT

of the

transistors•

This

leads

to a long

term

reliability

problem

For an electron

to become

hot, a field

strength greater

than

104

V/cm is

needed, which

is

easily

possible

for

technologies

with

L < 1 µm

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Prof. Dr. Hoppe CMOS Analog Design 89

iD

Vs VDS

characteristics

degradation:Hot carrier

effect

degrades

the

V-I characteristics

of

short

channel

transistors

due

to extensive usage

oraging

problem

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Prof. Dr. Hoppe CMOS Analog Design 90

Process

variations:Device

parameters

vary

between

different wafer runs

and even

on the

same

die!....why?Answers

:

(1) Variations

of process

parameters:–

impurity

concentrations

oxide

thickness–

diffusion

depths

(2) Temperature

effects

due

to non uniform conditions:–

variations

in sheet

resistances

variations

in threshold

voltages–

variations

in parasitic

capacitances

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Prof. Dr. Hoppe CMOS Analog Design 91

Process

variations:

(3) Variations

in geometry

of the

devices:–

limited

resolution

of the

lithographic

processes

results

into

variations

in W/L ratios

for

the neighbouring

transistors

device

mismatch

in circuits

built

on the

basis

of transistor

pairs, for

ex: differential stages

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Prof. Dr. Hoppe CMOS Analog Design 92

Transistor typical

parameter

values:0.25 µm technology, VDD = 2.5V, Minimum channel

length

device

n-channel

device p-channel

device Parameter

0.43 -0.40 VT0 (V)0.4 -0.4 γ

(V1/2)

0.65 -1.0 VDSsat

(V)115 -30 K‘

(μA/V2)

0.06 -0.1 λ

(V-1)

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Prof. Dr. Hoppe CMOS Analog Design 93

Passive components

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Prof. Dr. Hoppe CMOS Analog Design 94

Passive components

for

building

analog circuitsin CMOS technology:

MOS technology –

planar

technology •

Capacitors

and resistors

are

compatible

with

MOS

technology fabrication

steps•

Inductors

are

not

compatible

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Prof. Dr. Hoppe CMOS Analog Design 95

Capacitors:

Used

more

frequently

in analog integrated

circuits than

in discrete

designs

Applications: –

compensation

capacitors

in amplifiers

used

in gain

determining

components

in charge amplifiers

charge

storage

devices

in switched

capacitor filters

and digital to analog converters

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Prof. Dr. Hoppe CMOS Analog Design 96

Desired

characteristics

for

capacitors:

Good matching accuracy•

Low

voltage

coefficient

High ratio

of desired

capacitance

to parasitic capacitance

High capacitance

per unit

area•

Low

temperature

dependence

Note:

Analog CMOS processes

meet

these

criteria, pure digital processes

do not!

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Prof. Dr. Hoppe CMOS Analog Design 97

Types

of capacitances

in analog CMOS processes:

(1)

Poly Si / oxide

/ channel

capacitor

(MOS cap)-

like

a gate capacitance

of MOS transistor, but

n+

implant

introduced

to form a well between

„electrodes“ for

this

plate

capacitor

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Prof. Dr. Hoppe CMOS Analog Design 98

Types

of capacitances

in analog CMOS processes:

(2) Poly / oxide

/ poly capacitor-

top

and bottom

plates

are

made

up of poly silicon

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Prof. Dr. Hoppe CMOS Analog Design 99

Types

of capacitances

in analog CMOS processes:

(3) Metal 3 / oxide

/ metal 2 capacitor-

structure

similar

to the

poly 2 / poly 1 capacitor

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Prof. Dr. Hoppe CMOS Analog Design 100

Types

of resistors:

(1)

Diffused

resistor:

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Prof. Dr. Hoppe CMOS Analog Design 101

Types

of resistors:

(1)

Diffused

resistor:-

Standard process: sheet

resistance

is

in the

range

50 Ω/sq

to 150 Ω/sq

-

Salicided

process: surface

layer

on silicon

containing TaSi

or

TiSi

compounds. Sheet

resistance

is

in the

range

5 Ω/sq

to 15 Ω/sq

-

Problems:(a) capacitance

to n-well

(b) voltage

coefficient

100....250 ppm/V

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Prof. Dr. Hoppe CMOS Analog Design 102

Types

of resistors:

(2) Polysilicon resistor:

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Prof. Dr. Hoppe CMOS Analog Design 103

Types

of resistors:

(2) Polysilicon resistor:-

surrounded

by

a thick

oxide

layer

-

sheet

resistance

is

in the

range

30 Ω/sq

to 200 Ω/sq, depending

on doping

levels

-

Polysilicide

process: sheet

resistance

is

around 10 Ω/sq

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Prof. Dr. Hoppe CMOS Analog Design 104

Types

of resistors:

(3) N-well

resistor:

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Prof. Dr. Hoppe CMOS Analog Design 105

Types

of resistors:

(3) N-well

resistor:-

n-well

is

not

heavily

doped, hence

the

sheet

resistance

is

high in the

range

1 kΩ/sq

to 10 kΩ/sq

-

Voltage

coefficient

is

very

high, so it

acts

as a good pull up resistor...but

not

suitable

for

generating

a

precise

voltage

drop

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Prof. Dr. Hoppe CMOS Analog Design 106

Performance summary

of passive components

in a 0.8 µm CMOS technology:

Component

type Range of process

values

Matching accuracy

Temperature coefficient

Voltage coefficient

MOS cap 2.2 to 2.7 fF/µm2

0.05 % 50 ppm/K 50 ppm/V

Poly-poly

cap 0.8 to 1.0 fF/µm2

0.05 % 50 ppm/K 50 ppm/V

M1-M2 cap 0.021 to 0.025 fF/µm2

1.5 % - -

P+ diffusion resistor80 to 150 Ω/sq

0.4 % 1500 ppm/K 200 ppm/V

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Prof. Dr. Hoppe CMOS Analog Design 107

Performance summary

of passive components

in a 0.8 µm CMOS technology:

Component

type Range of process

values

Matching accuracy

Temperature coefficient

Voltage coefficient

n+ diffusion resistor

50 to 80 Ω/sq 0.4 % 1500 ppm/K 200 ppm/V

Polysilicon resistor

20 to 40 Ω/sq 0.4 % 1500 ppm/K 200 ppm/V

N-well

resistor 1 to 2 kΩ/sq ? 8000 ppm/K 10,000 ppm/V

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Prof. Dr. Hoppe CMOS Analog Design 108

Temperature

dependence

of MOS devices

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Prof. Dr. Hoppe CMOS Analog Design 109

Temperature

dependence

of MOS components:

Temperature

dependence

of MOS components

– important

performance

characteristic

in analog circuit

design•

The

temperature

behavior

of passive components

is

usually

expressed

in terms

of a fractional

temperature coefficient

TCF

defined

as:

TCF

= 1.dXX dT

X can

be

resistance

or

capacitance

of the

passive component. Usually

TCF is

multiplied

by

106

and

expressed

in units

of part

per million

per oC

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Prof. Dr. Hoppe CMOS Analog Design 110

Temperature

dependence

of drain current

iD

of a MOS transistor:

Most sensitive parameters

in the

drain current equation

are

µ

(mobility) and VT (threshold

voltage)

Due

to scattering

at thermally

induced

lattice vibrations, temperature

dependence

of µ

is

given

as

µ = Kµ

T -1.5

Temperature

dependence

of VT

is

approximated

asVT

(T) = VT

(T0

) –

α

(T -

T0

) α

= 2.3 mV/oC

and the

expression

is

valid

over

the

range

200 -

400 K•

In total iD

decreases

with

increasing

temperatureiD

| 125 oC

= 0.7 iD

| 25 oC

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Prof. Dr. Hoppe CMOS Analog Design 111

Temperature

dependence

of reverse

biased

diode current:

When

VD

< 0, the

diode

current

is

given

as

-iD

= Is

= qA

( Dppn0

+

Dnnp0

)=

qAD

.(ni)2

Lp

Ln

L N

= KT3exp(-

VG0 / Vt

)where

D, L, N are

diffusion

constant, diffusion

length

and

impurity

concentration

of the

dominant term

(either

n or

p)

VG0

= band gap

voltage

of Si at 300 K (1.205V)Vt

= thermal voltage

kT/q

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Prof. Dr. Hoppe CMOS Analog Design 112

Temperature

dependence

of reverse

biased

diode current:

Differentiating

with

respect

to T results

indIs

/dT

= (3KT3/T)exp(-VG0 / Vt

) + (qKT3VG0

/KT2)exp(-VG0 / Vt

)

= 3IS

+

ISVG0

T TVt

The

TCF

for

the

reverse

diode

current

is

1

dIS

=

3 +

VG0

IS

dT

T

TVt

Reverse diode

current

doubles

for

every

5 oC increase

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Prof. Dr. Hoppe CMOS Analog Design 113

Example:

Calculate

the

TCF

for

the

reverse

diode

current

for

300 Kand Vt

= 0.025 V

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Prof. Dr. Hoppe CMOS Analog Design 114

Analog CMOS subcircuits

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Prof. Dr. Hoppe CMOS Analog Design 115

MOS switch:•

MOS switch

a very

useful

device

Analog circuits: the

MOS switch

is

used

in multiplexers, modulation

and switched

capacitor

filters•

Digital circuits: used

in transmission

gate logic,

dynamic

latches, etc.•

MOS transistor

as a switch:

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Prof. Dr. Hoppe CMOS Analog Design 116

Model for

a switch:•

An ideal switch

is

a short

circuit

when

ON and an

open

circuit

when

OFF •

Equivalent

circuit

for

a voltage

controlled

non ideal

switch:

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Prof. Dr. Hoppe CMOS Analog Design 117

Model for

a switch:VC = control

voltage

A, B, C

= terminals; C being

the

control

terminalrON

= ON resistancerOFF

= OFF resistance

(very

high)VOS = offset voltage

between

A and B when

the

switch

is

ONIA

, IB = leakage

currentsIOFF = offset current

when

the

switch

is

OFF

CA

, CB = parasitic

capacitances

at the

terminals

to GNDCAC

, CBC = capacitive

coupling

between

A and B, contribute

to the

effect

called

charge

feedthrough

big

problem

in MOS switches!

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Prof. Dr. Hoppe CMOS Analog Design 118

ON resistance

of a MOS switch:

rON

consists

of the

series

combination

of rD

, rS

and the

channel

resistance

rD

, rS

parasitic

drain and source resistances

(~ 1Ω)•

rchannel

channel

resistance

(~ 50Ω)....dominant!•

Expression for

small-signal

channel

resistance:

rON

= 1

= L

diD/dVDS

Q

K‘W(VGS

- VT

- VDS)

where

Q designates

the

quiesent

point of the transistor

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Prof. Dr. Hoppe CMOS Analog Design 119

Range of voltages

at the

terminals

of a MOS switch

compared

to the

gate (control) voltage:

nMOS: VG larger than

the

source to drain voltage

to switch

the

transistor

ON (atleast

higher

by

VT

)•

pMOS: VG has to be

less

than

the

source to drain

voltage

to switch

the

transistor

ON •

nMOS: Bulk

has to be

connected

to the

most

negative voltage•

pMOS: Bulk

has to be

connected

to the

most

positive voltage•

Consider

nMOS

switch:

VG = VDD , VBulk

= VSS , then

the

transistor

is

ON untilVDD – VT >= VBA = VSD

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Prof. Dr. Hoppe CMOS Analog Design 120

Single stage

amplifiers

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Prof. Dr. Hoppe CMOS Analog Design 121

Applications

of CMOS amplifiers:

Analog applications:-

to overcome

noise

-

to drive

a next

stage-

used

in feedback

systems

-

to provide

logic

levels

for

interfacing

to digital circuits

Digital applications:-

to drive

a load

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Prof. Dr. Hoppe CMOS Analog Design 122

Basic notions:

Generalised

systemtransfer

curve:

x may

be

current

orvoltage

y(t) = α0 + α1

x(t) + α2

x2(t) + ...... + αn

xn(t) for

x1 <= x <= x2

In a narrow

range

of x, y can

be

approximated

witha linear relationship:y(t) ~ α0 + α1

x(t)where

α0 = operating

point

α1 = linear (small

signal) gain

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Prof. Dr. Hoppe CMOS Analog Design 123

Basic notions:

If

α1

x(t) << α0

, then

the

operating

point OP is

very slightly

disturbed

and linearization

around

OP is

possible

small

signal

analysis•

Δy = α1

Δx : linear relationship

between

increments of input

and output

If

x(t) varies

over

a large range, then

the

higher order terms

become

important

large signal

analysis•

If

the

slope

of the

characteristics

varies

with

the

signal

-

Nonlinearity

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Prof. Dr. Hoppe CMOS Analog Design 124

Competing

design

targets

for

amplifiers:

1.

Gain2.

Speed

3.

Power consumption4.

Supply

voltage

5.

Linearity6.

Noise

7.

Maximum voltage

swing at the

output8.

Input and output

impedance

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Prof. Dr. Hoppe CMOS Analog Design 125

Amplifier

design

octagon:-

Several

targets...and

complex

dependencies

!

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Prof. Dr. Hoppe CMOS Analog Design 126

Digital circuit

design

targets:

Three

targets:-

die size

-

speed-

power

consumption

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Prof. Dr. Hoppe CMOS Analog Design 127

CMOS amplifiers

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Prof. Dr. Hoppe CMOS Analog Design 128

Basic principles:

MOSFET translates

variations

in its

gate-source voltage

to a small

signal

drain current

If

a resistive

load

is

used, these

current

variations

in turn produce

variations

in the

output

voltage

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Prof. Dr. Hoppe CMOS Analog Design 129

Amplifier

configurations:

1.

Common source stage

(CS)2.

Source follower

or

common

drain stage

(SF)

3.

Common gate stage

(CG)4.

Cascode

stage: cascade

of CS and CG stage

5.

Differential amplifiers

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Prof. Dr. Hoppe CMOS Analog Design 130

Common source amplifier

configuration

(CS):

Small signal

model

for

thesaturation

region:

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Prof. Dr. Hoppe CMOS Analog Design 131

Input –

output

characteristics:1.

Vin

< VTH

:Vout

= VDD

2.

Vin

>= VTH

:M1 is

ON

saturation

region

3.

Vin

>= Vout

+ VTH

:M1 in linear region

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Prof. Dr. Hoppe CMOS Analog Design 132

Input –

output

characteristics:

1. Vin

< VTH

:

2.

Vin

>= VTH

:

3.

Vin

>= Vout

+ VTH

:

( )2THinoxnDDDout VVLW

C21

RVV −μ−=

( )[ ]VVVV2LWC

21

RVV 2outoutTHinoxnDDDout −−μ−=

VV DDout =

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Prof. Dr. Hoppe CMOS Analog Design 133

Supressing

short

channel

effects:

Analog circuits: Lmin

of technology is

not

utilized. Instead

analog circuits

use

4...5 times

Lmin

For C35 process

analog Lmin

~ 1.5 µm•

Longer

transistor

length

results

in

(1) negligible

subthreshold

current(2) small

channel

length

modulation

effect

(3) small

velocity

saturation

effect

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Prof. Dr. Hoppe CMOS Analog Design 134

Deep

triode

region:

If

Vin

is

high enough

to drive

M1 into

deeptriode

region, Vout

<< 2(Vin

- VTH

) and fromthe

equivalent

circuit

VRR

RVDon

onDDout+

=

( )VVRLWC1

V

THinDoxn

DD

−μ+=

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Prof. Dr. Hoppe CMOS Analog Design 135

Small signal

gain:

( )2THinoxnDDDout VVLW

C21

RVV −μ−=

In deep

triode

region, we

have

a voltage

divider

while

in the

saturation

region

we

have

the

proper amplifier

operation:

The

small

signal

gain

is

given

as:

VVA

in

out

∂∂

( )VVLWCR THinoxnD −μ−=

DmRg−=

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Prof. Dr. Hoppe CMOS Analog Design 136

Small signal

parameter•

In saturation,

Transconductance

gm

:

( )VVLWC THGSoxn −μ=

fixedVVIg DS

in

Dm ∂

∂=

Doxn ILWC2μ=

VVI2

THGS

D

−=

( )VVfg THGSm −=∴

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Prof. Dr. Hoppe CMOS Analog Design 137

Transconductance

gm

:

Thus

transconductance

gm

is

dependent

on input voltage!

Gain

varies

with

Vin...Nonlinearity

problem

for large signals!

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Prof. Dr. Hoppe CMOS Analog Design 138

How

to maximize

the

voltage

gain?

Where

VRD

is

voltage

drop across

load

resistance

To increase

the

gain:-

make

W/L larger

- make VRD large.... make

RD

large - make ID

smaller

(make

transistor

weaker)

IVIL

WC2AD

RDDoxn ∗μ−=ν

IV

LWC2A

D

RDoxn ∗μ−=ν

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Prof. Dr. Hoppe CMOS Analog Design 139

Trade-offs

in maximizing

the

voltage

gain:

Larger W/L larger input

capacitance•

Larger VRD

smaller

output

swing•

If

VRD is

kept

constant

ID

has to be

made

smallerRD

must

be

increasedhigher

time constants

at the

output

!

Trade-off: gain, BW, voltage

swing !

⇒⇒

⇒⇒

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Prof. Dr. Hoppe CMOS Analog Design 140

Trade-offs

in maximizing

the

voltage

gain:

For large values

of RD

, the

effect

of channel

length modulation

in M1 becomes

significant

Using

the

approximation

( ) ( )V1VVLWC

21

RVV out2

THinoxnDDDout λ+−μ−=

( ) ( )V1VVLWCR

VV

outTHinoxnDin

out λ+−μ−=∂∂

( )in

out2THinoxnD V

VVV

LWC

21R

∂∂

λ−μ−

( ) ( ) ( )2THinoxnD VVLWC21I −μ≈

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Prof. Dr. Hoppe CMOS Analog Design 141

Trade-offs

in maximizing

the

voltage

gain:

We

obtain:

Hence

Thus

decreases

the

amplification

factor

!

DD

Dm

IR1RgAλ+

−=ν

νν λ−−= AIRgRA DDmD

λ

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Prof. Dr. Hoppe CMOS Analog Design 142

Small signal

model

for

channel

length

modulation:

Since

,

DD

Dm

IR1RgAλ+

−=ν

OD r1I =λ

DO

DOm Rr

RrgA+

−=ν

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Prof. Dr. Hoppe CMOS Analog Design 143

Intrinsic

gain:

Intrinsic

gain

= upperbound

of the

overall

gain•

Ideal current

source infinite impedance

Todays

technology:gm

rO

is

between

10 to 30

Om

D

O

OmD

rgA

inresults1

Rr

rgA,Rlim

−=

+−=∞→

ν

ν

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Prof. Dr. Hoppe CMOS Analog Design 144

CS stage

with

diode

connected

load:

In MOS technology, resistors

are

complicated

to implement

Hence

„active

loads“

or

so called

„diode

connected transistors“

are

used

MOSFET acts

as small

signal

resistor

when

gate and drain is

shorted

Diode connected

transistors

are

always

in saturation because

VDS

= VGS

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Prof. Dr. Hoppe CMOS Analog Design 145

Small signal

equivalent

circuit:

As VDS

= VGS V1

= VX ⇒

XmO

XX Vg

rVI +=

g1r

g1

mO

m

≈∴ Impedence

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Prof. Dr. Hoppe CMOS Analog Design 146

Active

load

with

body

effect:

( )O

XXmbmX r

VVggI ++=

Vx

is

the

source potential of the

transistor

in the

operating

point: hence

Vbs

equals

Vx

= V1

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Prof. Dr. Hoppe CMOS Analog Design 147

Active

load

with

body

effect:

Thus

the

body

effect

reduces

the

impedance

!

Ombm r

1gg

1

++==

X

X

IV Impedance

mbmO

mbm gg1r

gg1

+≈

+=

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Prof. Dr. Hoppe CMOS Analog Design 148

Voltage

gain

of CS stage

with

diode

connectedload:

For negligible

λ,

Considering

device

dimensions,

2mb2m1m gg

1gA+

−=ν

2m

2mb

2m

1m

gg

11

gg

=ηη+

−= where

( )( ) η+μ

μ−=ν 1

1ILWC2ILWC2

A2D2oxn

1D1oxn

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Prof. Dr. Hoppe CMOS Analog Design 149

Voltage

gain

of CS stage

with

diode

connectedload:

Since

,

( )( ) η+

−=ν 11

LWLW

A2

1

2D1D II =

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Prof. Dr. Hoppe CMOS Analog Design 150

CS stage

with

diode

connected

load

Large signal

analysis:

Note:

If

VTH2

depends

only

slightly

on Vout

(weak

bodyeffect), then

we

have

a linear behavior

and Vout

is

proportional to Vin

2D1D II =

( ) ( )22THoutDD2

oxn2

1THin1

oxn VVVLWC

21VV

LWC

21

−−⎟⎠⎞

⎜⎝⎛μ=−⎟

⎠⎞

⎜⎝⎛μ∴

( ) ( )2THoutDD2

1THin1

VVVLWVV

LW

−−⎟⎠⎞

⎜⎝⎛=−⎟

⎠⎞

⎜⎝⎛∴

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Prof. Dr. Hoppe CMOS Analog Design 151

CS stage

with

diode

connected

load

Large signal

analysis:

Differentiating

both

sides

w.r.t

Vin

With

application

of the

chain

rule

we

getThe

result

matches

with

the

smallsignal

analysis

!

⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂

−∂∂

−⎟⎠⎞

⎜⎝⎛=⎟

⎠⎞

⎜⎝⎛

in

2TH

in

out

21 VV

VV

LW

LW

⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂

η=⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂

⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂

=∂∂

in

out

in

out

out

2TH

in

2TH

VV

VV

VV

VV

( )( ) η+

−=∂∂

=ν 11

LWLW

VVA

2

1

in

out

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Prof. Dr. Hoppe CMOS Analog Design 152

Input / output

characteristics

of active

load

CS stage:

At point A, M1 enters

the

triode

region

(strong nonlinearity

!)

Above

VTH1

and below

VA

,(linear behavior) inout VV ∝

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Prof. Dr. Hoppe CMOS Analog Design 153

CS stage

with

pMOS

active

load:

To improve

amplification

we

use

CS stage

with

pMOS

active

load

pMOS

output

node

can

charge

uptofull

VDD .....more

voltage

swing !

No body

effect•

Gain

depends

very

weakly

on device

dimensions

0=η⇒

( )( )2p

1n

LWLW

μ−=ν

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Prof. Dr. Hoppe CMOS Analog Design 154

Ausgangsspannungsbereich

Vout

(max) = VDD

– Vtp

Vout

(min): komplizierter:

M1 ungesättigter Bereich:1 1ds gs tn out in tnv v V v v V≥ − ⇒ ≥ −

CS-Stufe mit pMOS-Last

Vout

(min)

VDD

11 1 1

² ²(( ) ) (( ) )2 2ds out

d n ox gs tn ds n ox DD tn outv vW Wi µ C v V v µ C v V v

L L= − − = − −

2 2( )² ( )²2 2

p ox p oxd sg tp DD out tp

µ C µ CW Wi v V v v VL L

= − = − −

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Prof. Dr. Hoppe CMOS Analog Design 155

Ausgangsspannungsbereich:

Gleichsetzen

id1

= id2

und auflösen nach Vout

ergibt

Annahme: Einsatzspannung von pMOS

(Betrag) und nMOS

gleich VT

CS-Stufe mit pMOS-Last

(min)1

DD Tout DD T

p p

n n

V Vv V Vµ Wµ W

−= − −

+

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Prof. Dr. Hoppe CMOS Analog Design 156

Verstärkung Aν

= Vout

/Vin

und Ausgangswiderstand Rout

:Aufsummieren aller Ströme, die in den

Ausgangsknoten fließen:

CS-Stufe mit pMOS-Last

1 1 2 20 m in ds out m out ds outg v g v g v g v= + + +

1 2 2 2

1 1

ds m ds m

Routg g g g

= ≅+ +

1 1 2

1 2 2 2 1

out m in n OX

in ds m ds p OX

V g v µ C W LV g g g µ C W L

−= =

+ +

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Prof. Dr. Hoppe CMOS Analog Design 157

3dB Frequenz: Verstärkung sinkt hier auf 50%:

ω-3dB = 1/[Rout

(Cout

)]

Cout

ist die gesamte kapazitive Last am Ausgang:–

Externe Eingangskapazität

Leitungskapazität–

Parasitäre Transistorkapazitäten

Beispiel: Rout

= ro

für einen pMOS-Transistor

W/L = 3/1, in dem der Drainstrom 60µA fließt ist bei Cout

= 5 pF:

CS-Stufe mit pMOS-Last

6

3 3

1/ 2 ( / ) 2 60 3 50 / 134 /

5 /134 / 0,037 1027 / 4,3

o m p ox D

o

dB dB

r g µ C W L I µA V µA V

r C pF µA V sMrad s f MHzω

− −

= = = ⋅ ⋅ ⋅ =

= = ⋅= ⇒ =

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Prof. Dr. Hoppe CMOS Analog Design 158

Designrezeptur: W zu L bei geg. VerstärkungHängt von den Vorgaben ab. In der Regel wird eine

Verstärkung vorgegeben, aus der sich alles weitere ableitet.

Im Labor werden wir einen Verstärker entwerfen, der eine Verstärkung von Aν

= -

4 haben soll. Daraus folgt:Aus Gleichung auf S. 92 folgt dann ein Weitenverhältnis

für pMOS-

und nMOS-Transistor.Nächster Schritt ist dann zu verifizieren, dass die

Verstärkung auch tatsächlich erreicht wird. Dazu ist die Kennlinie also Vout

= f(Vin

)

aufzunehmen.Die Verstärkung folgt dann als Ableitung von Vout

nach Vin

CS-Stufe mit pMOS-Last

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Prof. Dr. Hoppe CMOS Analog Design 159

Designrezeptur: ArbeitspunktAus der simulierten Verstärkung folgt dann der

Arbeitspunkt, der implizit für die Kleinsignalanalyse verwendet wurde, aus der die Formel für Aν

stammt.

Aus der Verstärkungskenn-Linie kann nun der Arbeits-punkt abgelesen werden:

Vin

= 0,67V / Vout

= 1,91V

CS-Stufe mit pMOS-Last

Kennlinie

Verstärkung

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Prof. Dr. Hoppe CMOS Analog Design 160

Designrezeptur:

Output SwingAus der Verstärkungskennlinie kann die minimale und

maximale Ausgangsspannung abgelesen werden:

Simulation:Vout

(max) = 2,98VVout

(min) = 0,06V

Theorie:Vout

(max) = 2,8VVout

(min) = 0,08V

CS-Stufe mit pMOS-Last

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Prof. Dr. Hoppe CMOS Analog Design 161

Designrezeptur: Frequenzverhalten

Am Arbeitspunkt können wir den Strom in M1 und damit in M2 ausrechnen damit folgt gm2

(Eingangsleitwert pMOS)

CS-Stufe mit pMOS-Last

( )2

1 2

2

2

2 33 3

1 ( )2

2 ( / )

/

2

pD D p ox gsPMOS Tp

p

m p ox p D

o m

m dBdB dB

Wi i µ C V Arbeitspunkt V

L

g µ C W L I

r C C gg rad f HzC s

ωωπ−

− −

= = −

=

=

= ⇒ =

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Prof. Dr. Hoppe CMOS Analog Design 162

Designrezeptur: Frequenzverhalten

Simulation:f-3dB

= 4,1 MHzVerst. = 12,1 dB

Theorie:f-3dB

= 6,2 MHzVerst. = 12 dB

CS-Stufe mit pMOS-Last

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Prof. Dr. Hoppe CMOS Analog Design 163

Source follower:

CS stage

has a good voltage

gain, but

load

impedance has to be

high

If

the

load

impedance

is

low, a „buffer“

is

needed

for impedance

matching

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Prof. Dr. Hoppe CMOS Analog Design 164

Source follower:

Source follower

(or

„common

drain stage“) may operate

as a voltage

buffer

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Prof. Dr. Hoppe CMOS Analog Design 165

Source follower

input/output

characteristics:

Vout

follows

Vin

with

a voltage

difference

(level

shift) equal

to VGS

( ) S2

outTHinoxnout RVVVLWC

21V −−μ=

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Prof. Dr. Hoppe CMOS Analog Design 166

Small signal

gain

(large signal

analysis):

Differentiating

both

sides

w.r.t. Vin

since

( ) S2

outTHinoxnout RVVVLWC

21V −−μ=

( ) Sin

out

in

THoutTHinoxn

in

out RVV

VV1VVV2

LWC

21

VV

⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂

−∂∂

−−−μ=∂∂

⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂

η=∂∂

in

out

in

TH

VV

VV

( )

( ) ( )η+−−μ+

−−μ=

∂∂

1RVVVLWC1

RVVVLWC

VV

SoutTHinoxn

SoutTHinoxn

in

out

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Prof. Dr. Hoppe CMOS Analog Design 167

Small signal

gain

(large signal

analysis):

With

we

get:( )outTHinoxnm VVVLWCg −−μ=

( ) Smbm

Sm

Rgg1RgA++

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Prof. Dr. Hoppe CMOS Analog Design 168

Small signal

gain

(small

signal

analysis):

•outbs

out1

VVVV−=

=−in Vsince

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Prof. Dr. Hoppe CMOS Analog Design 169

Small signal

gain

(small

signal

analysis):

will result

in

Maximum possible

gain

= 1

S

outout1mb11m R

VVgVg =−

in

out

VVA =ν

( ) Smbm

Sm

Rgg1RgA++

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Prof. Dr. Hoppe CMOS Analog Design 170

Drawback of RS

implemented

as ohmic

resistor:

ID1

depends

strongly

on input

DC level•

If

Vin

changes

from

1.5 to 2.0 V (10 % increase)then

ID1

increases

by

a factor

of „2“•

Hence

VGS

– VTH

increases

by

√2 highly

non linear I/O characteristics

!

Improvement: instead

of RS

we

takea constant

current

source M2 to get

a linear behavior

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Prof. Dr. Hoppe CMOS Analog Design 171

Output impedance

of SF with

constant

currentsource as load:

X1 VV −=

0VgVgI XmbXmX =−−∴

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Prof. Dr. Hoppe CMOS Analog Design 172

Output impedance

of SF with

constant

currentsource as load:

Note:

Body effect

decreases

the

output

resistance

of the source follower

!

mbmout

X

X

gg1R

IV

+== Hence

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Prof. Dr. Hoppe CMOS Analog Design 173

Example: Source follower:W/L = 20µm/0.5µmVTH0

= 0.6 V|2ΦF

| = 0.7 Vµn

Cox

= 50 µA/V2

γ

= 0.4 V2

I1 = 200 µA

Q1: What

is

Vout

for

Vin

= 1.2 V?Q2: If

I1

is

produced

by

an nMOS

device, what

is

theminimum

W/L ratio

for

which

M2 remains

saturated?

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Prof. Dr. Hoppe CMOS Analog Design 174

Solution A1:

VTH depends

on VoutIterative solution: (1) we

calculate

Vout

for

VTH0(2) we

calculate

VTH for

Vout

obtained

in (1)

( )2outTHinoxnD VVVLWC

21I −−⎟

⎠⎞

⎜⎝⎛μ=

( )

LWC

I2VVVoxn

D2outTHin

μ=−−∴

( )40*A50A200*2V6.02.1 2

out μμ

=−−∴

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Prof. Dr. Hoppe CMOS Analog Design 175

Solution A1:

Now,

Using

the

new

VTH

the

improved

value

of Vout

is

0.119 V, which

is

approximately

35 mV less

than

the

calculated

value.

V153.0Vout =∴

( )FSBF0THTH 2V2VV φ−+φγ+=

( )7.0153.07.04.06.0VTH −++=∴

V635.0=

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Prof. Dr. Hoppe CMOS Analog Design 176

Solution A2:

Consider

transistor

in place

of current

source:•

Drain-source

voltage

of M2 is

0.119 V

Device

is

saturated

only

if

VGS

– VTH

< 0.119 V•

In the

saturation

region

we

have,

( )22

oxnD 119.0LWC

21A200I ⎟

⎠⎞

⎜⎝⎛μ=μ=

m5.0m283

LW

min2 μμ

=⎟⎠⎞

⎜⎝⎛∴

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Prof. Dr. Hoppe CMOS Analog Design 177

Drawbacks

of the

SF configuration:

Source followers

exhibit

a high input

impedance

and a moderate output

impedance, but

at the

cost

of two

drawbacks:

(1) nonlinearity(2) voltage

headroom

limitation

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Prof. Dr. Hoppe CMOS Analog Design 178

Nonlinearity

of the

SF configuration:

Even with

an ideal current

source I1

the

I/O characteristics

display

a nonlinearity

due

to the

dependence

of VTH

on Vsource•

Submicron

technology: rO

of the

transistor

also changes with

VDS

additional nonlinear

effects

!•

Nonlinearity

due

to body

effect

can

be

eliminated

if

the

bulk

is

tied

to the

source•

Because

all nMOS

devices

have

a common

bulk

potential, this

is

only

possible

for

pMOS

devices

in a n-well

technology

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Prof. Dr. Hoppe CMOS Analog Design 179

Nonlinearity

of the

SF configuration: •

pMOS

source follower

with

no body

effect:

Price paid:

PFET have

a lower

carrier

mobility

leading

to higher

output

impedance

than

for

a nMOS

source

follower

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Prof. Dr. Hoppe CMOS Analog Design 180

Voltage

headroom

limitation

of SF:

Source followers

shift

the

level

of the

signal

by

VGSconsuming

voltage

headroom

and hence

limiting

the

voltage

swing

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Prof. Dr. Hoppe CMOS Analog Design 181

Voltage

headroom

limitation

of SF:

Without

source follower: Vmin

at node

X is

VGS1

– VTH1

for having

M1 in saturation

With

the

source follower: Vmin

at node

X should

be greater

than

VGS2

+ (VGS3

– VTH3

) so that

M3 is

in saturation

For same

overdrive

voltages

in M1 and M3, voltage swing allowable

at X is

reduced

by

VGS2

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Prof. Dr. Hoppe CMOS Analog Design 182

Common gate stage

(CG):

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Prof. Dr. Hoppe CMOS Analog Design 183

Common gate stage

(CG):

Input is

applied

to the

source terminal

and output

is

taken at the

drain terminal

Gate is

connected

to a dc

voltage

to establish

proper operating

conditions

Bias current

may

flow

directly

through

the

input

signal source –

direct

coupling

M1 can

be

biased

by

a constant

current

source, with

the signal

capacitively

coupled

to the

circuit

capacitive

coupling

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Prof. Dr. Hoppe CMOS Analog Design 184

Direct

coupling

Large signal

analysis:

Assume

that

Vin

decreases

from

a large positive value•

Vin

>= Vb

– VTH

: M1 is

off and Vout

= VDD•

For lower

values

of Vin

: M1 goes

into

saturation

As Vin

decreases, so does

Vout

, eventually

driving

M1 into the

triode

region

if

( )2THinboxnD VVVLWC

21I −−μ=

( ) THbD2

THinboxnDD VVRVVVLWC

21V −=−−μ−

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Prof. Dr. Hoppe CMOS Analog Design 185

CG input

output

characteristics:

If

M1 is

saturated, output

voltage

can

be

expressed

as:

( ) D2

THinboxnDDout RVVVLWC

21VV −−μ−=

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Prof. Dr. Hoppe CMOS Analog Design 186

CG stage

small

signal

gain:

Small signal

gain

can

be

obtained

by

differentiating

w.r.t. Vin

Since

, we

have

Gain

is

positive !

( ) Din

THTHinboxn

in

out RVV1VVV

LWC

VV

⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂

−−−−μ−=∂∂

η=∂∂=∂∂ SBTHinTH VVVV

( )( )η+−−μ=∂∂ 1VVVR

LWC

VV

THinbDoxnin

out

( ) Dm R1gA η+=∴ ν

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Prof. Dr. Hoppe CMOS Analog Design 187

CG stage

input

impedance:

For λ

= 0, the

impedance

seen

at the

source of M1 is

like in the

case

of source follower

Thus, the

body

effect

decreases

the

input

impedance

!

( )η+=+ 1g

1gg

1

mmbm

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Prof. Dr. Hoppe CMOS Analog Design 188

Cascode

stage:

Cascade

of a common source and a common gate stage is called a

„cascode

stage“•

M1 generates

small

signal

drain current

proportional to Vin

M2 routes

this

current

to RD

M1 is

the

input

device•

M2 is

the

cascode

device

M1 and M2 carry the

same current

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Prof. Dr. Hoppe CMOS Analog Design 189

Cascode

stage

bias

conditions:

M1 is

saturated

if

VX

>= Vin

– VTH1•

To keep

M1 and M2 both

in saturation,

VX

= Vb

– VGS2•

Hence, Vb

– VGS2

>= Vin

– VTH1

Or

Vb

= Vin

+ VGS2

– VTH1

M2 in saturation

Vout

>= Vb

– VTH2•

Hence

Vout

>= Vin

– VTH1

+ VGS2

– VTH2

If

Vb

is

chosen

to keep

M1 at the

edge

of saturation, minimum

output

voltage

for

which

both

transistors

operate

in saturation

is

equal

to the

overdrive

voltage

of M1 plus that

of M2

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Prof. Dr. Hoppe CMOS Analog Design 190

Voltages

in cascode

stage:

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Prof. Dr. Hoppe CMOS Analog Design 191

Cascode

stage

large signal

analysis:

Vin

= 0 V Vout

= VDD•

Vin

< VTH1

M1 and M2 are

„off“Vout

= VDDVX

= Vb

– VTH2•

Vin

>= VTH1

M1 is

„on“Vout

drops

as M1 draws

currentVGS2

increases

as ID2

increaseshence

VX

drops•

Vin

sufficientlylarge VX

drops

below

Vin

by

VTH1-

M1 enters

triode

region

Vout

drops

below

Vb

by

VTH2-

M1 and M2 are

in triode

region

⇒⇒

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Prof. Dr. Hoppe CMOS Analog Design 192

Cascode

stage

large signal

analysis:

Main advantages

of cascode

structure: -

high output

impedance

-

high voltage

gain

proportional to 2mg

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Prof. Dr. Hoppe CMOS Analog Design 193

Cascode

stage

small

signal

equivalent

circuit:

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Prof. Dr. Hoppe CMOS Analog Design 194

Cascode

stage

output

impedance:

The

circuit

can

be

viewed

as a common-source

stage with

a resistor 1Or

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Prof. Dr. Hoppe CMOS Analog Design 195

Cascode

stage

output

impedance:

Using

the

equation

of output

resistance

for

common source stage,

Assuming

, we

have

M2 boosts

the

output

impedance

of M1 by

a factor

of !!

( )( ) 2O1O2O2mb2mout rrrgg1R +++=

1rg Om >>( ) 1O2O2mb2mout rrggR +≈

( ) 2O2mb2m rgg +

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Prof. Dr. Hoppe CMOS Analog Design 196

Cascode

stage

voltage

gain:

Voltage

gain

of a cascode

stage

is

given

as:

The

maximum

voltage

gain

is

roughly

equal

to the square

of the

intrinsic

gain

of the

transistors

High output

impedance

of the

cascode

stage

results

in a high voltage

gain

!

( ) 1O2O2mb2m1m rrgggA +=ν

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Prof. Dr. Hoppe CMOS Analog Design 197

Current

sources

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Prof. Dr. Hoppe CMOS Analog Design 198

Practical

current

source:

For an ideal current

source and Iout

is

constant

for all output

voltages

Normally

is

finite and Iout

= f(Vout

)

∞=Or

Or

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Prof. Dr. Hoppe CMOS Analog Design 199

Requirements

of a good performance

current

mirror:

The current-ratio is precisely set by the aspect-ratio (W/L) and is independent of temperature

Output impedance is very high, i.e., very high Rout

and very low Cout

. As a result, the output current is independent of output voltage (DC and AC)

Input resistance Rin

is very low•

The

voltage

compliance

is

low, i.e., the

minimum

output

voltage

Vout

, for

which

the

output

acts

as a current source, is

low

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Prof. Dr. Hoppe CMOS Analog Design 200

Basic current

mirror:

M1 is

diode

connected

transistor

which

is

always

in saturation

ID1 is

mirrored

into

transistor

M2

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Prof. Dr. Hoppe CMOS Analog Design 201

Basic current

mirror:

Since

VGS1 = VGS2

and if

provided

the

channel

length

modulation

effects

are

very small

Since

VGS1 = VGS2 , W/L ratios

determineID2 !

2D1D2

2

1

1 IILW

LW

=⇒=

( )2TH1GS1

1oxn1D VV

LWC

21I −μ=

( )2TH2GS2

2oxn2D VV

LWC

21I −μ=

21

12

1D

2D

LWLW

II

=

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Prof. Dr. Hoppe CMOS Analog Design 202

Basic current

mirror:

OR

where

What

is

the

minimum

voltage

across

M2 such that

M2 remains

in saturation?

-

What

is

the

output

resistance?where

λ

is

channel

-

length

modulation

factor

( )( ) REF

1

2out I

LWLW

I =

D

SSGSDD1DREF R

VVVII −−==

2DSTH2GSminout VVVVV =−==

2Dout2m2O I

1I1

g1r

λ=

λ==

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Prof. Dr. Hoppe CMOS Analog Design 203

Basic current

mirror

design

example:

5 design

variables: L1

, W1

, L2

, W2

, and R = f(VGS

)

If

we

test 10 values

per design

parameter

per simuation, then

we

need

105

simulations

!

Strategy:step

(1):

Select

a common

channel

length

such that

λ

is

very

small

L1 = L2

= L

λ

= f(L) should

be

as small

as possibletherefore

L >> Lmin

Note:

For AMS CSD Lanalog

= 1 µm

2

1

2D

1D

WW

II

=⇒

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Prof. Dr. Hoppe CMOS Analog Design 204

Basic current

mirror

design

example:

step

(2):

Select

VGSVGS is

chosen

close

to VTH in order to have

reasonable

currents

in large devices

VGS – VTH = ΔV is

„overdrive“

or

excess

voltage

n-channel

device p-channel

device Parameter

0.5 -0.65 VTH (V)0.58 0.42

175 60

0.06 0.06 λ

(1/V) for

L = 1µm

( )2ox VAC21 μμ

( )Vγ

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Prof. Dr. Hoppe CMOS Analog Design 205

Basic current

mirror

design

example:

For a reasonable

overdrive

voltage

say, ΔV = 0.2V, we get

VGS = VTH + ΔV = 0.7 V

step

(3):

Calculate

R

For example: to design

a current

mirror

ID1 = ID2 = 10 µA the

required

R can

be

calculated

as

1D

SSGSDD

IVVVR −−

=

Ω=μ

−−= k260

A106.2

A1007.03.3R

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Prof. Dr. Hoppe CMOS Analog Design 206

Basic current

mirror

design

example:

How

to implement

R = 260 kΩ

?sheet

resistance: N-well: 1 kΩ

per square

NDIFF: 180 Ω

per squarePDIFF: 160 Ω

per square

Note:

On-chip

resistance

of such a high value

is

not possible

to implement. To overcome

this

we

usually

use

externally

connected

resistances

to the

IC pins

step

(4):

Calculate

W1 and W2

( ) A10m1

W*V04.0*VA

2175 12

2 μ=μ

⎟⎠⎞

⎜⎝⎛ μ∴

( ) A105.07.0*VAC

LW

21I 2

2oxn1

11D μ=−⎟

⎠⎞

⎜⎝⎛ μμ=

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Prof. Dr. Hoppe CMOS Analog Design 207

Basic current

mirror

design

example:

step

(5):

Calculate

Vmin

Note:

Thus, the

minimum

output

voltage

= overdrive voltage

selected

by

the

designer

step

(6):

Calculate

rout

m3m85.2WW 21 μ≈μ==∴

THGS2DS VVV −≥∵V2.0VVV outmin =Δ==

Ω=μ

= M67.1A10*)V1(06.0

1I1r

2Dout

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Prof. Dr. Hoppe CMOS Analog Design 208

Basic current

mirror

design

example:

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Prof. Dr. Hoppe CMOS Analog Design 209

Cascode

curent

mirrors:

In practice, channel

length

modulation

effect

results

in significant

error

in copying

currents

While

VDS1

= VGS1 = VGS2

, VDS2 may

not

equal

VGS2 because

of the

circuitry

fed

by

M2

In order to suppress

the

effect

of channel

length modulation, a cascode

current

source can

be

used

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Prof. Dr. Hoppe CMOS Analog Design 210

Cascode

curent

mirrors:•

If

Vb

is

chosen

such thatVY

= VX

, then

Iout

closelytracks

IREF

This

is

because

the cascode

device

„shields“

the

bottom

transistor

from variations

in Vp

Thus, we

say

that

VY remains

close

to VX

and hence

ID2

= ID1

with

high accuracy

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Prof. Dr. Hoppe CMOS Analog Design 211

Cascode

curent

mirrors:•

How

do we

generate

Vb

?•

Since

the

objective

is

to ensure

VY

= VX

, we

mustguarantee

Vb

– VGS3 = VX or

Vb

= VGS3 + VX

This

result

suggests

that

if a gate source voltage

is

added

to VX

, the

required value

of Vb

can

be obtained

The

idea

is

to place another

diode

connected

device

M0 in series

with M1, thereby

generating

a

voltage

VN

= VGS0 + VX

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Prof. Dr. Hoppe CMOS Analog Design 212

Cascode

curent

mirrors:•

Proper choice

of the

dimensions

of M0 w.r.t. M3 yields

VGS0 = VGS3

Connecting

node

N to the gate of M3 we

have

VGS0 + VX = VGS3 + VY

If

the

transistor

dimensions are

properly

matched, then

we

get

VX = VY

This

result

holds

even

if M0 and M3 suffer

from

body

effect

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Prof. Dr. Hoppe CMOS Analog Design 213

Differential Amplifiers

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Prof. Dr. Hoppe CMOS Analog Design 214

Why

Differential Amplifiers?

Differential amplifiers

are

versatile

building blocks

in analog circuits:

Input stages

of Operational amplifiers–

Read

amplifier

in SRAMs

Noise

and crosstalk

immune signal processing

Low

voltage

data

transfer

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Prof. Dr. Hoppe CMOS Analog Design 215

Why

Differential Signals?

Differential signals are

immune with

respect

to crosstalk effects

as „+“

and „-“

signals

are

affected in an identical

fashion!

Clock

Coupling Signal

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Prof. Dr. Hoppe CMOS Analog Design 216

Principles

of Differential Amplifiers

Differential amplifier

may

be formed

by

two

CS-stages.

Problem im input

voltage

is too

low

on one

side, then

the

corresponding

CS-stage is

switched

off!

output voltage is clippednonlinear behaviour

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Prof. Dr. Hoppe CMOS Analog Design 217

Principles

of Differential Amplifiers

Solution the two CS- stages are source-

coupled by a current source

No clipping of output voltage but slight nonlinearities for low input common mode voltages!

Obviously the gain vanishes for lager input voltage differences!

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Prof. Dr. Hoppe CMOS Analog Design 218

Key parameters

of Differential Amplifiers

Gain (of course)

Input Common Mode Range:

linear operation until one of the transistors leaves saturation!ICMR: Input Common Mode Range (ca. 50% VDD-VSS)

Offset:Transistors M1 and M2 are not completely identical due to process variations Vin1

= Vin2

not necessarily Vout1

= Vout2

but Vout1

= Vout2

if and only if Vin1

= Vin2

+ VosVos

= Input-Offset-Voltage (typ. 5 -

20 mV)

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Prof. Dr. Hoppe CMOS Analog Design 219

Common Mode AmplificationCommon Mode Voltages should not be

amplified!

Only Differential Voltages are of interest!Common mode gain AvC

= 0!

1 21 2 1 2( )

2in in

out out D in in CV VV V A V V Aν ν

+− = − ±

Differential Gain

Common Mode Gain

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Prof. Dr. Hoppe CMOS Analog Design 220

Common Mode AmplifificationCommon Mode Voltage VinCMapplied to the amplifier inputs reduces the diff-amp to an effective CS-stage with half the load resistance and twice the W/L-ratio of the pull-down transistor. The common mode gain results in

/ 21

2 2

Dcm

SS

n ox d

RAR

WC IL

μ

=+

For a zero common mode gain Rss

has to be infinity

ideal current source at the bottom!

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Prof. Dr. Hoppe CMOS Analog Design 221

Real Differential Amplifier

Quite often we have a symmetrical voltage range around 0V

e.g. VDD=2.5V, VSS=-2.V

Then all voltages are referenced to analog ground: 0V

Real Differential Amplifier

amplifies

a differential signal

and outputs a single

ended

voltage

Vout

VSS

VoutVin1 Vin2

+-

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Prof. Dr. Hoppe CMOS Analog Design 222

Differential to Single Ended

If we do so, only ΔI/2 = (I2

–I1

)/2 is

utilised

to produce

the output

voltage

using

the

voltage

drop over

RD

Gain is reduced by 50%, as current of M1 is not considered!

Just drop one

output

voltage

say

Vout1

?

Vout

1 2 2SSI II Δ

= − 2 2 2SSI II Δ

= +

ISS

M1 M2

M3

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Prof. Dr. Hoppe CMOS Analog Design 223

Differential to Single Ended

If ΔVin

grows

then

I1

+ ΔI and I2

-

ΔI

but

I3

and I4

grow

due

to mirror-effect

by

ΔI

!

I2

gets

smaller

and I4

grows Vout ∼ ΔI !

Better

solution

is

to mirror

current

in M1 into

the

output

path

Vout

ISS

M5

M3 M4

M2M1

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Prof. Dr. Hoppe CMOS Analog Design 224

Gain

Calculation

Note that M1 and M2 are effected by the substrate bias effect!Hence bulk-terminals of these transistors may be connecte

either

to VSS or to a floating well!

Source-coupled

pair M1 and M2 with

a current

mirror

current

source (M3 and M4)

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Prof. Dr. Hoppe CMOS Analog Design 225

Gain

Calculation

The current Iss

in M4 is the sum of the currents of M1 and M2

The

input

differential voltage

vID

maybe

expressed

by

the

differences in the

Gate-Source-Voltages

of M1 and M2

1 21 2

2 2

' 'D D

ID GS GS

N N

i iv v v W WK KL L

= − = −

1 2SS D DI i i= +

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Prof. Dr. Hoppe CMOS Analog Design 226

Gain

Calculation

The normalized currents look like

The

drain currents

of M1 and M2 are

readily

obtained

by

using

both equations

for

vID

and ISS

and by

some

algebraic

transformations:

22 4

1 2

22 4

2 2

' '2 2 4

' '2 2 4

SS SS ID IDD N N

SS SS

SS SS ID IDD N N

SS SS

I I W v W vi K KL I L I

I I W v W vi K KL I L I

⎧ ⎫⎪ ⎪⎛ ⎞= + −⎨ ⎬⎜ ⎟⎝ ⎠⎪ ⎪⎩ ⎭

⎧ ⎫⎪ ⎪⎛ ⎞= − −⎨ ⎬⎜ ⎟⎝ ⎠⎪ ⎪⎩ ⎭

ID

/ISS 2 -2

iD2 iD1

vID

⋅ISS

/KN

’(W/L)-1/2

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Prof. Dr. Hoppe CMOS Analog Design 227

Gain

Calculation

The current equations apply as long as the arguments of the square roots remain real, imposing the condition:

2 'SS

IDN

Iv K WL

<

From

the

currents

one

may

obtain

the

transconductances

of the differetial

inputs, which

have

the

same

magnitude

but

different signs:

The

maximum

gain

is

achieved

at vID

= 0

1 ( 0) '4

D SSm ID N

ID

I W Ig V Kv L∂

= = =∂

Compared

with

the

transconductance

of an NMOS-Transistor

ID

=ISS

/2 one

sees that

the

transconductance

is

reduced

to 50%, because

only

half of the

differential

input

voltage

is

acting

at each

input

node.

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Prof. Dr. Hoppe CMOS Analog Design 228

Gain

with

current

mirror

loads

If a current mirror and no load resistances are utilized, the current mirror mirrors the current in transistor M1 into the path with transistor M2 with the correct sign and transform the output

differential voltage into a single ended signal.

NMOS-inputsPMOS Current

Mirror load

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Prof. Dr. Hoppe CMOS Analog Design 229

Gain

with

current

mirror

loads

iout

is the differential current i1

-i2

(perfect matching of devices). The transconductance

of this current is denoted gmd

1

1

( 0) ' 2outmd ID N SS m

ID

i Wg V K I gv L∂

= = = =∂

Compared

with

the

transconductance

of an NMOS-Transistor

ID=ISS/2 one

sees

that

the

transconductance

is

now

100%.

Large signal

voltage

transfer

curve:

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Prof. Dr. Hoppe CMOS Analog Design 230

Gain

with

current

mirror

loads

The (small signal) gain maybe obtained from

The

output

resistance

is

determined

by

the

devices

M2 and M4 in the output

sidebranch

out md ID

ID out out

i g vv r i

==

2 42 4

1 1

( )2

outSSds ds

r Ig g λ λ= =

+ +

Hence

we

obtain1

2 4 1

2 1'outN

ID SS

v WA Kv L Iν λ λ

= =+

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Prof. Dr. Hoppe CMOS Analog Design 231

Input Voltage

Range

The differential amplifier operates properly until the input voltages are such that one transistor leaved saturation.

This voltage range is investigated by setting the differential voltage to zero and sweeping the common mode voltage VIC

To keep M1 (or M2) in saturation we have to find the highest (lowest) input volatge

keeping M1 (and M2) in saturation:

VDS1

VGS1

VT1

Voltage

drop in M3

13113(max) TNSGDDGSDSSGDDIC VVVVVVVV +−=+−−=

The

minimum

voltage

is

determined

by

the

voltage

drop in the source transistor

M5

5 1(min) ( )IC SS DS GSV V V sat V= − +

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Prof. Dr. Hoppe CMOS Analog Design 232

Slew

Rate

The

Slew

Rate

(SR) specifies

the

speed

for

charging

or discharging

a capacitive

load

at the

output

CL

to a voltage

which

is the

gain

multiplied

with

VID

. Note that

all internal

parasitics contribute

to the

total output

load. The

charging/discharging

current

is

sourced

from

the

current

sink (transistor

M5).

Current

in M5

5 / LSR I C=

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Prof. Dr. Hoppe CMOS Analog Design 233

3dB-frequency and power

dissipation

The

3dB-frequency is

determined

by

the

RC-time-constant

of the output

branch

Power dissipation

Pdiss

is

obtained

from

the

current

supplied

or sourced

from

the

bottom-transistor

M5 multiplied

with

th

evoltage

drop from

VDD to VSS

3 312dB dB

out L

fR C

ω π− −= =

( )diss DD SS SSP V V I= − ⋅

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Prof. Dr. Hoppe CMOS Analog Design 234

Summary

of the

relevant formula

For a design

we

use

the

following

fomulas:

5

11 1

1

5 3 4

3

5 2

3 1 1 3 1

2( )

2

( ) ( ) ( )1

(min) ( )(max)

outN P

diff m out n ox d out

diss DD SS DD SS

dBout L

IC SS DS GS

IC DD SG DS GS DD SG TN

RI

WA g R C I RL

P V V I V V I I

R CV V V sat VV V V V V V V V

λ λ

μ

ω−

=+

= = ⋅

= + = + ⋅ +

=

= − += − − + = − +

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Prof. Dr. Hoppe CMOS Analog Design 235

How

to meet

the

design

targets?

Assume

we

have

the

following

specification

and we

use

the

0.8µm sample

technology

3

2,510 /

100 ( 5 )1,5 2

100

1

DD SS

dB L

diff

diss

V V VSR V µsf kHz C pF

V ICMR VA

P mW

= − =≥≥ =

− ≤ ≤=

In which

order we

have

to determine

the

transistor

dimensions

for a differential amplifier

with

NMOS-inputs

and a PMOS current

mirror

load?

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Prof. Dr. Hoppe CMOS Analog Design 236

Design procedure: M5 The

first

transistor

to be

dimensioned

is

M5 the

source coupling

current

sink.

This

transistor

has to provide

the

current

for

charging

and dischargig

the

load capacitance. Hence

the

Slew

Rate the

specification

has to be

considered:

We have to consider the upper bound for the power dissipation, which limits I5

to 200µA and we have to be aware that the this current is relevant for the output

resistance Rout

, which itself enters together with CL

into the 3dB-frequency, which was specified to exceed 100kHz Rout has to be less than 318 kΩ

5 5

5

/ / 5 10 /50

LSR I C I pF V µsI µA

= = ≥≥

( )

3 3

5

12

16,28 100 3185

2 318

dB dBout L

outout

outN P

fR C

kHz R kR pF

R kI

ω π

λ λ

− −= =

⋅ ≤ ⇒ ≤ Ω

= ≤ Ω+

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Prof. Dr. Hoppe CMOS Analog Design 237

Design procedure: M5 then

M3(=M4)Using

the

channel

length

modulation

factors

we

obtain

I5

= 70µA.To achieve some design margin we set I5

= 100µA

M3 (and M4) have to dimensioned according to the Input Common Range ICMR

13113(max) TNSGDDGSDSSGDDIC VVVVVVVV +−=+−−=

Solving

for

VGS3

we

obtain

2,5V –

2V + 0,7V = 1,2V = VGS3

This

voltage detremines

the

saturation

current

of M3, which

has to be

in the

operating

point (vID

= 0) equal

to Iss

/ 2 = 50 µA. If

use

the

equation

for

the

saturation current

of M3 and solve

for

VGS3

we

get

VWL

VµAµAVVSG 7,0

²/505022,1

3

33 +

⋅==

3

3

3 4

3 4

0,5 2

2 80.5²

LVW

W WL L

=

= = =

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Prof. Dr. Hoppe CMOS Analog Design 238

Design procedure: M1 (=M2)Using

the

gain

specification

and using

and inserting id1

for ISS

/2

3

3

1 2

1 2

100 23.31

18,4

WL

W WL L

=

==> = =

1

2 4 1

2 1'outN

ID SS

v WA Kv L Iν λ λ

= =+

1 1 11

1 1 1 1

11 1

2 2 2 110 ²23,31 100 /

( ) ( ) (0,04 0,05) 50Ox Oxn d n

N P d N P d

W W W µAµ C i µ CL L L V W V VLi i µAλ λ λ λ

⋅= = = =

+ ⋅ + ⋅ + ⋅

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Prof. Dr. Hoppe CMOS Analog Design 239

Design procedure: M5Using

the

lower

ICMR specification

we

may

calculate

VDS5

At first we need VGS2 which can be calculated from the current in M2 which is in the operating point ISS

/2=50µA

5 2(min) ( )IC SS DS GSV V V sat V= − +

( )222 2

22n ox

GS TNµ C WI V V

L= −

W2

/L2

= 18,4 and hence

(using

VT and the

other

technology dependent parameters): VGS2

= 0.222V + 0,7V.

The

resulting

voltage

VDS5

(sat) = 0,3V –

0,222V = 0.0777V.

M5 has to provide

for

this

small

overdrive

voltage

of 0.0777V 100µA

( )5 5

25 5

2 200 300( )² 110 0,0777n ox ds

W I µAL µ C V sat µA

= = =⋅

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Prof. Dr. Hoppe CMOS Analog Design 240

Design procedure: Fine tuningM5 is

very

large. To get

a smaller

M5 we

need

to increase

M1 (and M2). Then

the

voltage

drop across

the

input

transistors

is

less

and hence

VDS5

is increased

and then

a smaller

M5 is

sufficient

to provide

the

required

100µA

Using

W1

/L1

= W2

/L2

= 25 we

get

W5

/L5

= 150, which

is

sufficient

for

the

resulting overdrive

voltage

VDS5

(sat) = 0,11V.Note that

the

gain

is

increased

by

larger input

transistors, but

this

is

no

drawback! In order to reduce

the

small

channel

effects

we

select

as a common

channel

length

1µm, which

is

slightly

more

than

the

minimum

dimension

of 0.8µm

W1 = W2

= 25 µm W3

= W4

= 8 µmW5

= 150 µm

Cross check: Is

the

gain

large enough?

' '1 1 1 1

1 2 1 1 2 1

2 2 2 110 25 1170,09 100SS SS

K W K WAL I L Iυ λ λ λ λ

⋅ ⋅ ⋅= = = =

+ ⋅ + ⋅

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Prof. Dr. Hoppe CMOS Analog Design 241

Operational Amplifiers

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Prof. Dr. Hoppe CMOS Analog Design 242

Overview

Operational Transconductance

Amplifier

OTA = Unbuffered

Operational Amplifier

1. Design Methodology2. Two-Stage

Opamps

3. Frequency

Compensation

of Opamps4. Cascode

Opamps

5. Characterization

of Opamps

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Prof. Dr. Hoppe CMOS Analog Design 243

Opamp Design Methodology

Differential-transconductance

OTA-stage

provides

the differential-to-single-ended

conversion

as well as good

part

of overall

gain

⇒ improves

noise

+ offset performance

Second gain-stage

is

usually

an inverter•

If

opamp is

to drive

low-resistive

loads, a buffer

(output)

stage

must

be

included

⇒ to lower

the

output resistance

and maintain

a large signal

swing

Bias circuit

provides

the

proper operating

point to each stage

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Prof. Dr. Hoppe CMOS Analog Design 244

Opamp Design Methodology

Compensation

is

necessary

to ensure close-loop

stability!

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Prof. Dr. Hoppe CMOS Analog Design 245

Opamp Design MethodologyIdeally, an opamp has:•

Infinite differential-voltage

gain

Infinite input-resistance•

Zero output-resistance

Infinite bandwidth•

Perfect

rejection

of common-mode

voltage

(CMRR →∞)

Perfect

rejection

of supply

voltage

variations

(PSRR →∞)

In reality, an opamp only

approaches

these conditions:

For most

applications

involving

unbuffered

opamps, an open-loop

of 5000 or

more

is

usually

sufficient

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Prof. Dr. Hoppe CMOS Analog Design 246

Ideal and non ideal Opamp Symbol for

an opamp realized

by

a VCVS

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Prof. Dr. Hoppe CMOS Analog Design 247

Ideal and non ideal Opamp Model for

a real Opamp

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Prof. Dr. Hoppe CMOS Analog Design 248

Ideal and non ideal Opamp Modelparameters for

Opamp-Model

Rid

, Cid

: differential-input

impedance

Ricm

: common-mode

input

resistance

Rout

: output

resistance

VOS

: input-referred

offset voltage

( necessary

to make

Vo

=0 when

both inputs

are

grounded)

IB1

, IB2

: input-bias

current

(approx. zero

for

a CMOS opamp)

Vi

/CMRR

: represents

the

effect

of a finite common-mode

rejection

ratio

on the

opamp output.

en2

and in2

: model

the

input-referred

noise

generated

by

the

opamp components. These are

voltage-

and current-noise

spectral

densities, with

units

of mean

square

volts

and mean

square

amperes, respectively. They have

no polarity

and are

always

assumed

to add.

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Prof. Dr. Hoppe CMOS Analog Design 249

OpAmp non-idealitiesa) Finite Bandwidth:

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Prof. Dr. Hoppe CMOS Analog Design 250

Finite Bandwidthp1

, p2

, p3

… are

poles

of the

opamp open-loop

transfer function.

In general, pi

= -ωi

, where

ωi

is

the

reciprocal

time- constant

or

break-frequency

of the

pole pi

.

Zeros are

ignored

at the

present

time as they

appear frequencies

well-above

the

unity

gain

frequency

of the

opamps to be

discussed.

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Prof. Dr. Hoppe CMOS Analog Design 251

Finite BandwidthBode-Diagram: Amplification

vs. Frequency

(semilog.)

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Prof. Dr. Hoppe CMOS Analog Design 252

Finite Bandwidth

and PSSR •

Typical

frequency

response: imposed

by

design, ω1

is much

lower

than

other

pole frequencies

⇒ω1

has the

dominant influence

in the

frequency response

(p1

is

the

dominant pole)

b) Finite PSSR (Power Supply

Rejection

Ratio)•

PSRR : represents

the

change

in the

output

voltage

caused

by

a variation

on the

supply

voltage. PSRR+ and PSRR-

are

referred

to VDD and VSS, respectively.

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Prof. Dr. Hoppe CMOS Analog Design 253

Finite PSSR •

Fully-differential

(differential-in, differential-out)

structures

minimize

the

effect

of supply

variations

on the opamp output, as they

are

seen

as common-mode

voltages, at expense

of higher

circuitry

complexity, however.

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Prof. Dr. Hoppe CMOS Analog Design 254

OpAmp non-idealities

c) finite Slew-Rate•

The

opamp output

has a limited

capability

to

drive/source load

currents. There’s

a limited

range

over which

the

output

voltage

can

swing while

still maintaining

high-gain

property.•

The

limiting

voltage-rate

associated

to the

output

swing

when

a large-signal

is

applied

to the

input

is

called

slew- rate, which

is

usually

determined

by

the

maximum

current

available

to charge/discharge

a capacitance.

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Prof. Dr. Hoppe CMOS Analog Design 255

Slew

Rate

Slewing

effect

on a unity-gain

closed-loop

opamp configu- ration. Normally, slew-rate is

determined

by

the

first

stage, rather

than

by

the

output

circuit.

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Prof. Dr. Hoppe CMOS Analog Design 256

OpAmp non-idealities

d) finite Settling

Time•

Important

in sampled-data

applications, it

is

the

time

needed

for

the

opamp output

to reach

a final value, to within

a predetermined

tolerance, following

a small-

signal

applied

to the

input.•

The

settling

time can

be

completely

determined

from

the

location

of poles

(and zeros) in the

opamp small-signal transfer

function

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Prof. Dr. Hoppe CMOS Analog Design 257

Settling

TimeTime-response

to a small-signal

voltage-step

on

closed-loop

configuration

(buffer)

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Prof. Dr. Hoppe CMOS Analog Design 258

OpAmp non-idealities

d) finite Settling

Time•

Important

in sampled-data

applications, it

is

the

time

needed

for

the

opamp output

to reach

a final value, to within

a predetermined

tolerance, following

a small-

signal

applied

to the

input.•

The

settling

time can

be

completely

determined

from

the

location

of poles

(and zeros) in the

opamp small-signal transfer

function

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Prof. Dr. Hoppe CMOS Analog Design 259

Typical

Unbuffered

CMOS Opamp Specifications

Open-loop

Voltage

Gain

70dB•

GBW (unity-gain

frequency) ≥

2MHz

Settling-time

1μs•

Slew-rate ≥

2V/μs

Input CMR ≥

± 3V•

CMRR ≥

60dB

PSRR ≥

60dB•

Output swing ≥

± 4V

Output resistance

50 –

100Ω•

Offset voltage

10mV

Noise

100nV/Hz1/2 @ 1KHz•

Layout area

120k sq

μm

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Prof. Dr. Hoppe CMOS Analog Design 260

Typical

Unbuffered

CMOS Opamp Specifications

Boundary

ConditionsSupply-voltage: ±5V ±10%

Supply-current: 100μA (quiescent)Temperature

range: 0 to 70°C

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Prof. Dr. Hoppe CMOS Analog Design 261

Typical

Unbuffered

CMOS Opamp: 2 Stage

Architecture

M1 to M5 stage

1, M6 and M7 stage

2

Compensation Capacitor

CC

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Prof. Dr. Hoppe CMOS Analog Design 262

Frequency-Compensation

of OpampsOpamps are

primarily

used

in closed-loop

configuration.

The

high and imprecise

gain

can

be

used

with negative feedback

to achieve

a very

accurate

transfer

function, which

approximately

depends

only

on the feedback

elements.

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Prof. Dr. Hoppe CMOS Analog Design 263

Frequency-Compensation

of OpampsIt’s

imperative that

the

signal

fed

back to the

input

be

of

such amplitude

and phase

that

it

does

not

regenerate the

signal

around

the

loop, leading

to either

an

oscillation

or

clamping

the

opamp output

to one

of the supply

potentials.

In order to avoid

positive and regenerative feedback, the

following

conditions

should

be

met:

Loop

Gain

< 1 and Phaseshift

< -180°

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Prof. Dr. Hoppe CMOS Analog Design 264

Negative Feedback SystemIf

F(s)A(s) = -1 at s = jω1 the

gain

reaches

infinity

and the

circuit

amplifies

ist own

noise

until

it begins

to oscillate. In other

words:

if

F(jω1 )A(jω1 ) = -1 the

circuit

begins

to oscillate!

Barkhausen criteria

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Prof. Dr. Hoppe CMOS Analog Design 265

Negative Feedback SystemThis situation happens if ⎪F(s)A(s)⎪

= 1 and argF(s)A(s) = -180°

at s = jω1

Note that total phase shift around the loop at critical frequency ω1 is 360°

but the negative

feedback alone adds 180°

of phase shift.360°

is necessary so that feedback signal adds in

phase to the input to allow oscillation build up!Loop gain of unity or larger is also required to

enhance the oscillation amplitude!

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Prof. Dr. Hoppe CMOS Analog Design 266

Negative Feedback SystemThe frequencies where the magnitude and the

phase of the loop gain are equal to unity or - 180°

are of special importance to stability.

For stability one has to avoid the Barkhausen criteria by adding appropriate passive

components into the loop!How to do so?Look at the Bode-Diagram!

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Prof. Dr. Hoppe CMOS Analog Design 267

Example

for

Bode PlotsLook at a transfer function:

All poles and roots are given in the form: (1+s/ωk

)One root at s = -1 and two poles at s = -10 and s = -100.For a Bode-Plot the complex factors are written as phasors,

i.e. absolute value times the phase factor.

1 1 1/( ) 100 0.1( 10)( 100) (1 /10)(1 /100)

s sH ss s s s

+ += =

+ + + +

1 /1 (1 )1 /1( ) 0.1 0.1 (0.1)(1 /10)(1 /100) (1 /10) (1 /100) (1 /10) (1 /100)

(1 ) exp(arctan( /1))

j jsH ss s j j j j

j j

ω ωω ω ω ω

ω ω

+ ∠ ++= = ∠

+ + + + ∠ + ∠ +

∠ + =

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Prof. Dr. Hoppe CMOS Analog Design 268

What

looks

the

Bode Plot like?MATLAB generates the Bode-Plot using the commands–

>> Mysys=tf(100*[1 1],[1 110 1000])

––

Transfer function:

100 s + 100–

------------------

s^2 + 110 s + 1000––

>> bode(Mysys)

Bode diagram

consists

of 2 plots: magnitude

(or

„gain“) in

dB and phase

(linear) against the

logarithmic

frequency

magnitude

phase

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Prof. Dr. Hoppe CMOS Analog Design 269

Asymptotic

Bode Plots: The

PhaseNote: Phase factor is exponential of the arctangens

of the fraction of

imaginary part divided by the real part of the complex number.Hence the total phase is the sum of the individual phase angles.The real coefficient which is multiplied with the fraction (here

0.1) in

general maybe positive or negative: A positive factor has phase 0°

and a negative factor -180°

Drawing the phase is simple, just draw the phase-angles individually and add them!

[ ][ ]

( ) ( ) exp (arctan(0) exp (arctan( ) exp ( arctan( /10) exp ( arctan( /100)

( ) exp(exp (arctan(0 /10 /100)

H s H s j j j j j

H s j j j

ω ω ω

ω ω ω

= ⋅ ⋅ − ⋅ − =

+ − −

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Prof. Dr. Hoppe CMOS Analog Design 270

Asymptotic

Bode Plots: The Magnitude

Magnitude is a product of different terms. In order to draw them

in a simple fashion, we take a logarithm.

To be specific we write the magnitude in units of decibels.Each quantity Q has a representation X in decibels:

X = 20.0log10

(Q)The magnitude in decibels reads:

Changing to decibels transforms the multiplication into a summation of constant terms and terms of the form 20log10

⎪1+jω/ωk

⎪!

1 /1( ) 0.1

(1 /10) (1 /100)

20 log ( ) 20 log 0.1 20 log 1 /1 20 log 1 /10 20 log 1 /100

jH s

j j

H s j j j

ωω ω

ω ω ω

+=

+ +

⋅ = ⋅ + ⋅ + − ⋅ + − ⋅ +

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Prof. Dr. Hoppe CMOS Analog Design 271

Constructing

a Bode Diagram

A constant term:H(s)=100=40dBThe magnitude is straight line and the phase is 0°

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Prof. Dr. Hoppe CMOS Analog Design 272

Constructing

a Bode Diagram

A real pole:

ω0

is the -3dB or corner frequency.The magnitude

is given by

0 0

1 1( )1 1

H s s j ωω ω

= =+ +

2

10 10 100

0

0

2

0 10 100 0

2

00 10 10

0

120log ( ) 20log 20log 11

: ( ) 0

: ( ) 20log 20log

: ( ) 20log 1 20log

H sj

low frequency H s dB

high frequency H s

break frequency H s

BoundaryCases

ωωω

ω

ω ω

ω ωω ωω ω

ωω ωω

⎛ ⎞= = − + ⎜ ⎟

⎝ ⎠+

<< ≈

⎛ ⎞ ⎛ ⎞>> ≈ − = −⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠

⎛ ⎞= = − + = −⎜ ⎟

⎝ ⎠( )2 3.01dB= −

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Prof. Dr. Hoppe CMOS Analog Design 273

Constructing

a Bode Diagram

A real pole:

ω0

is the -3dB or corner frequency.The phase

is given by

0 0

1 1( )1 1

H s s j ωω ω

= =+ +

( )

( )

( )

0

0

0

0

( ) arctan

: ( ) arctan 0 0

: ( ) arctan 902

: ( ) arctan 1 454

H s

low frequency H s

high frequency H s rad

break frequency H s rad

BoundaryCases

ωω

ω ωπω ω

πω ω

⎛ ⎞∠ = − ⎜ ⎟

⎝ ⎠

<< ∠ ≈ − =

>> ∠ ≈ − ∞ = − = −

= ∠ ≈ − = − = −

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Prof. Dr. Hoppe CMOS Analog Design 274

Constructing

the

Magnitude

Using the high and low frequency approximation we obtain:

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Prof. Dr. Hoppe CMOS Analog Design 275

Constructing

the

Phase

Using the high and low frequency approximation we obtain:

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Prof. Dr. Hoppe CMOS Analog Design 276

Constructing

a Bode Diagram

A real zero:

The magnitude

is given by

0 0

( ) 1 1sH s j ωω ω

= + = +

( )

2

10 10 100 0

0

2

0 10 100 0

2

00 10 10

0

20log ( ) 20log 1 20log 1

: ( ) 0

: ( ) 20log 20log

: ( ) 20log 1 20log 2 3.01

H s j

low frequency H s dB

high frequency H s

break frequency H s

BoundaryCases

ω ωω ω

ω ω

ω ωω ωω ω

ωω ωω

⎛ ⎞= + = + ⎜ ⎟

⎝ ⎠

<< ≈

⎛ ⎞ ⎛ ⎞>> ≈ =⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠

⎛ ⎞= = + = =⎜ ⎟

⎝ ⎠dB

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Prof. Dr. Hoppe CMOS Analog Design 277

Constructing

a Bode Diagram

A real zero:

The phase

is given by

0 0

( ) 1 1sH s j ωω ω

= + = +

( )

( )

( )

0

0

0

0

( ) arctan

: ( ) arctan 0 0

: ( ) arctan 902

: ( ) arctan 1 454

H s

low frequency H s

high frequency H s rad

break frequency H s rad

BoundaryCases

ωω

ω ωπω ω

πω ω

⎛ ⎞∠ = ⎜ ⎟

⎝ ⎠

<< ∠ ≈ =

>> ∠ ≈ ∞ = =

= ∠ ≈ = =

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Prof. Dr. Hoppe CMOS Analog Design 278

Constructing

a Bode Diagram

Example for pos. real zero:

( ) 130sH s = +

10% of ω0

10 times

ω0

Phase rises

by

90°

Magnitude

rises

by 20dB per decade°

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Prof. Dr. Hoppe CMOS Analog Design 279

Constructing

a Bode Diagram

Example for positive real zero

( ) 130sH s = −

Decreases

phase margin! Like

a pole!

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Prof. Dr. Hoppe CMOS Analog Design 280

Rules

for

Ass. Bode PlotsBode Plots

illustrate the asymptotic

behavior of

magnitude and phase of a complex function in terms of it‘s poles and zeros.

Rule 1: The slope of the magnitude plot changes by +20dB/dec at every zero and by -20dB/dec at every pole frequency.

Rule 2:

At every pole(zero) frequency ωm the phase begins to fall(rise) at approximately 0.1ωm, experiences a change

of -45°(+45°) at ωm and -

90°(+90°) at 10 ωmNote that the phase is much more affected by high

frequency poles than the magnitude is!

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Prof. Dr. Hoppe CMOS Analog Design 281

Location

of polesPoles and zeros in the complex plane: sp

= jωp

+ σpPole in the RHP:

σp

> 0. As the impulse response includes a term of the form exp(jωp

+ σp

)t

then the time domain response contains a growing exponential

oscillationPole at the imaginary axis:

σp

= 0. In the time domain response circuit sustains oscillation

Pole in the LHP:

σp

< 0. As the impulse response includes a term of the form exp(jωp

+ σp

)t

then the time domain response contains a falling exponential

oscillation is damped out!If

one

plots

the

location

of poles

as the

loop

gain

varies

one

gets

a root

locus

diagram

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Prof. Dr. Hoppe CMOS Analog Design 282

Frequency-Compensation

of OpampsStability

is

achieved

if

following

condition hold

Stability

condition is

better

illustrated

with

the

use

of Bode diagrams. The

⎪A(jω)F(jω) ⎪

curve

must

cross the

0dB-

point before

Arg[-

A(jω)F(jω)] reaches

0°–

A measure

of stability

is

given

by

the

phase

value

when

⎪A(jω)F(jω) ⎪

=1 and it

is

called

phase-margin

ΦM

.

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Prof. Dr. Hoppe CMOS Analog Design 283

Frequency-Compensation

of OpampsNote:

CMOS OpAmp has a negative

feedback: Inherent

phase

margin

of 180°

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Prof. Dr. Hoppe CMOS Analog Design 284

Frequency-Compensation

of Opamps

The

importance

of good stability

with

adequate phase-margin

(ΦM

) is

better

understood

by considering

the

response

of the

closed-loop

system

in time domain, shown

in the

figure

below, for different phase-margin

values.

Larger phase-margins

result

in less

ringing

of the output

signal.

It’s

desirable

to have

ΦM

of at least 45°,

whereas 60°

is

preferable

in most

cases.

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Prof. Dr. Hoppe CMOS Analog Design 285

Frequency-Compensation

of Opamps

Closed-loop

time-response

for

different ΦM

values

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Prof. Dr. Hoppe CMOS Analog Design 286

Frequency-Compensation

of Opamps

2-stage opamp equivalent

small-signal

circuit

There

are

two

poles

(second order system)

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Prof. Dr. Hoppe CMOS Analog Design 287

Frequency-Compensation

of Opamps

There

are

two

poles

(second order system)

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Prof. Dr. Hoppe CMOS Analog Design 288

Frequency-Compensation

of Opamps

As Ro1

and Ro2

and naturally

high in order to obtain very

high voltage

gain

on every

stage, both

poles

have

relatively

low-frequencies

⇒ very

low

ΦM ⇒ frequency

compensation

is

needed

to move

one

pole to higher

frequencies.

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Prof. Dr. Hoppe CMOS Analog Design 289

The

Miller-Capacitance

(pole-splitting) Compensation

of Opamps

This

technique

comprises

connecting

a capacitor

CC

from the

output

to the

input

of the

second stage, leading

to:

i)

the

effective

capacitance

Co1

is

increased

by

a factor (gm2

Ro2

) CC

, which

moves

down p1

quite

considerably.

ii) owing

to the

negative feedback, the

second-stage

output resistance

is

reduced, moving

p2

to higher

frequencies

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Prof. Dr. Hoppe CMOS Analog Design 290

The

Miller-Capacitance

(pole-splitting) Compensation

of Opamps

This

technique

comprises

connecting

a capacitor

CC

from the

output

to the

input

of the

second stage, leading

to:

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Prof. Dr. Hoppe CMOS Analog Design 291

The

Miller-Capacitance

(pole-splitting) Compensation

of Opamps

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Prof. Dr. Hoppe CMOS Analog Design 292

The

Miller-Capacitance

(pole-splitting) Compensation

of Opamps

⇒ as far as phase-shift

is

concerned, a RHP zero behaves

like

a LHP pole ⇒ΦM

is

degraded

⇒ Compensation

comprises

moving

p2

and z1

(except p1

) to frequencies

sufficiently

high beyond

the

unity- gain

frequency

of the

opamp

a first-order

system

condition is

approached

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Prof. Dr. Hoppe CMOS Analog Design 293

The

Miller-Capacitance

(pole-splitting) Compensation

of Opamps

Root-locus

movement

as CC

increases

and Bode plots

before

and after compensation

for

gain

and Bode plot

after

compensation

for

phase.

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Prof. Dr. Hoppe CMOS Analog Design 294

Eliminate

or

Relocate

the

RHP zeroThe

RHP zero

can

be

displaced

by

inserting

a nulling

resistor

RZ

in series

with

CC

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Prof. Dr. Hoppe CMOS Analog Design 295

Eliminate or Relocate the RHP zero

Again, assuming

that

p1

and p2

are

widely

spaced and Rz

<< Ro1

or

Ro2

, it

turns

out

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Prof. Dr. Hoppe CMOS Analog Design 296

Eliminate or Relocate the RHP zero

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Prof. Dr. Hoppe CMOS Analog Design 297

Eliminate or Relocate the RHP zero

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Prof. Dr. Hoppe CMOS Analog Design 298

Eliminate or Relocate the RHP zero

Implementation

of Resistor

by

linear MOSFET

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Prof. Dr. Hoppe CMOS Analog Design 299

Design procedure

> 5000 V/V VDD

= 2,5 VSS

= -2,5V

Verst.*Bandbr. (GB): 5 MHz

CL

= 10 pF Slew

Rate > 10V/µs

Vout-Bereich: ±

2V ICMR = -1 bis 2V Pdiss

2mW

Specification

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Prof. Dr. Hoppe CMOS Analog Design 300

Design procedureCircuit

diagram

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Prof. Dr. Hoppe CMOS Analog Design 301

1.

Choice

of technology and channel

length

We

use

the

AMS C35 technology

⇒ Compensation

comprises

moving

p2

and z1

(except p1

) to frequencies

sufficiently

high beyond

the

unity- gain

frequency

(the

Gain-Bandwidth

GBW) of the

opamp

a first-order

system

condition is

approached

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Prof. Dr. Hoppe CMOS Analog Design 302

1.

Choice

of technology and channel

length

We

use

a 0.8µm CMOS technology

⇒ Compensation

comprises

moving

p2

and z1

(except p1

) to frequencies

sufficiently

high beyond

the

unity- gain

frequency

(the

Gain-Bandwidth

GBW) of the

opamp

a first-order

system

condition is

approached

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Prof. Dr. Hoppe CMOS Analog Design 303

The

Miller Capacitance

Compensation

comprises

moving

p2

and z1

(except

p1

) to frequencies

sufficiently

high beyond

the

unity-gain

frequency

(the

Gain-Bandwidth

GBW) of the

opamp

a first-order

system

condition is

approached

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Prof. Dr. Hoppe CMOS Analog Design 304

2. Choose

the

Miller-CapacitanceAs outlined

in the

previous

slides

Position of non dominant pole and the

root

in RHP are

given

by the

transcondactecnce

of second stage

(i.e. that

of transistor

M6

in the

schematic) and the

output

capacitance

(i.e. in principle

the

load

cap)

GB is

amplification

at 0Hzmultiplied

with

p1

:

6 62 1

m m

L C

g gp zC C−

≈ ≈

1(2. ) 1 2

1

stage o o C

pg R R C

= −

(1 . ) (2 . ) 1 02 (0)st sat nd stage sat og g R R Aν=1m

c

gGBC

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Prof. Dr. Hoppe CMOS Analog Design 305

Choosing

the

Miller-CapacitanceThe

2 stage

OpAmp has two

poles

and one

RHP-zero. If

the

zero

is

assumed

to be

placed

10 times

higher

then

the

Gain-Bandwidth

(GB), then

the

second pole has to be

placed

at a frequency

2.2times higher

than

GB to obtain

a

phase

margin

of 60°

= ΦM

[ ]1 1 1

1 2 1

1 1 1

1 2 1

180 ( ) ( )

180 tan tan tan 60

120 tan tan tan

M Arg A j F j

p p zGB GB GBp p z

ω ωω ω ω− − −

− − −

Φ = ± °− =

± °− − − = °

° = + +

The

phase

margin

has to be

60°

below

and above

GB. Hence

all frequencies

are

replaced

in the

formula

by

GB.

GB

is

given

by

the

DC-amplification

multiplied

by

the

absolute value

of the

dominant pole p1

. As Aν

(0) is

very

large we

obtain

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Prof. Dr. Hoppe CMOS Analog Design 306

Choosing

the

Miller-Capacitance

Therefore

the

pole p2 has to be

located

2.2 times

higher

then

GB:

1 1 1

2

1

2

1 1

1

120 tan (0) tan tan 0,1

24,3 tan

tan (0) tan ( ) 90

tan (0.1) 5,7

GBAp

GBp

A

ν

ν

− − −

− −

° = + +

° =

≈ ∞ =

=

together

with

our

assumption

that

the

zero

is

placed

10 times higher

then

the

Gain-Bandwidth

(GB) in the

third

term

we

obtain

1

2

2

tan 24,3 tan(tan ) 0.45

2.20.45

GBp

GBp GB

−° = =

= =

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Prof. Dr. Hoppe CMOS Analog Design 307

Choosing

the

Miller-Capacitance

6 11

6 1

10 10

10

m m

C C

m m

g gz GBWC C

g g

≈ > =

⇒ >

If

the

RHP-zero

is

placed

at 10xGBW, by

placing

the

non dominant pole p2

at a frequency

2.2times higher

than

GBW gives

60°

= ΦM

0,2210

2.2 3

C L

L

C C

C Chere C pFC pF better C pF

>=

= =

6 6 12

6 66 1

2.2

10 2.2 1010

m m m

L L C

m mm m C L

L C

g g gpC C C

g gwith g g C CC C

−≈ = =

> ⇒ < ⇒ >

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Prof. Dr. Hoppe CMOS Analog Design 308

Choosing

I5

for

the

Slew

RateThe

slew

rate is

determined

by

the

current

of M5 divided

by

the

load

capacitance

of the

differential stage

at the

input. The

load

is

the

Miller capacitor:

( ) ( )5 ( ) 10 / 3 30cI SR C V µs pF µA= > =

5 5/ / 3 10 /LSR I C I pF V µs= = ≥

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Prof. Dr. Hoppe CMOS Analog Design 309

Choosing

W3

and W4

These two

devices

form a current

mirror. The

relevant spec-value

is

the maximum

ICMR-voltage

Vin

(max) = 2.0V:

Therefore

we

have

identical

widths

of 15µm for

M3 and M4

( )

( )

53 2'

3 03 1

26

(max) (max) (min)

30 1550 10 2,5 2,0 0,85 0,55

DD in T T

IWK V V V V

µA µmV V V−

= =− − +

=⋅ − − +

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Prof. Dr. Hoppe CMOS Analog Design 310

Choosing

gm1

i.e. W1

and W2

gm1

is

the

transconductance

of the

input

transistors

forming

a differential pair (M1

and M2

). This

quantity

is

related

to the

GB specified

and Cc

obtained already:

( ) ( ) ( )6 1211 3 10 2 3 10 94,25m

mc

gGB g µSC

π −= ⇒ = ⋅ ⋅ =

2 211 2

1 2 1

94,25 2,79 32 ' 2 110 15

m

N

gW WL L K I

= = = = ≈⋅ ⋅

Since

M1

and M2

provide

50% of the

I5

-current which

was calculated

to be 30µA, we

find

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Prof. Dr. Hoppe CMOS Analog Design 311

Choosing

W5

by

VDS5

The

drain-source

voltage

of M5

is

obtained

from

the

required

minimum

input common

mode voltage

-1.5V.

This

voltage

must

not

drop below

VDS

(sat) in order to keep

M5

(as an effective

current

source) in saturation

55 1

1

6

6

(min) (max)

30 101 ( 2,5 ) 0,85 0,353 110 10

DS in SS TIV V V Vß

V V V V V−

= − − − =

⋅− − − − − =

⋅ ⋅

( )

5 5 55 ' 2

5 5 5 5

6

6 2

2( )( )

2 30 104,49 4,5

110 10 (0,35)

DSDS

I W IV satß L K V

= ⇒ = =

⋅= ≈

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Prof. Dr. Hoppe CMOS Analog Design 312

Choosing

W6

from

gm6 and gm4

Since

the

transconductances

of M1

and M2

are

identical

we

obtain

from

the considarations

for

the

choice

of the

Miller capacitance

gm4

is

determined

by

I5

: ID4

= I5

/2:

From

gm4

, W4

/L4

and

gm6

we

may

calculate

W6

/L6

2 16

102,2 2,2 942,52,2

m L mm

c

g C g pFg µSC pF

= = =

124 4

4

2 ' 2 50 10 15 15 150m P DWg K I µSL

−⎛ ⎞= = ⋅ ⋅ ⋅ ⋅ =⎜ ⎟⎝ ⎠

6

6 4 4

94215 94150

m

m

gW WL L g

⎛ ⎞ ⎛ ⎞= = =⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠

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Prof. Dr. Hoppe CMOS Analog Design 313

Choosing W7The

current

ratios

of M6

and M5

determine

the

width

of this

transistor

If

M7

leaves

saturation

then

we

are

at the

minimum

output-voltage-range (here

-2V):

The

minimum

output

voltage

is

met, hence

first

cut

design

is

complete!

6

7 5 75

14IW W WL L I L

⎛ ⎞⎛ ⎞ ⎛ ⎞ ⎛ ⎞= ⇒ =⎜ ⎟⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠ ⎝ ⎠⎝ ⎠

min 7( ) 2,5 ( )DSV out V V sat= − +

77

' 7

7

2 2 95( ) 0,351110 14DS

N

IV sat VWKL

⋅= = =

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Prof. Dr. Hoppe CMOS Analog Design 314

Recheck Gain and PowerWith

the

dimensions

obtained

so far, we

check whether

Pdiss

and Aν

are

OK

First cut

design

meets

specification!

( )5 30 95 0,625 2dissP V µA µA mW mW= + = <

2 6

5 2 7 6 6 7

12

12

2( ) ( )

2 942,5 92,45 10 7696 / 5000 /30(0,04 0,05)95(0,04 0,05) 10

m mg gAI I

V V V V

ν λ λ λ λ−

⎛ ⎞= =⎜ ⎟+ +⎝ ⎠

⎛ ⎞⋅ ⋅ ⋅= >⎜ ⎟+ + ⋅⎝ ⎠

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Prof. Dr. Hoppe CMOS Analog Design 315

Final Design with dimensions