biasedviews on the industry's broadest fdsoi physical ip...

Kelvin Low et al09 APR 2019

Biased views on the industry's broadest FDSOI physical IP solution

SOI Silicon Valley Symposium 2019

2 © 2019 Arm Limited

Arm Physical Design Group product portfolio & ecosystemMost trusted and widely used provider with more than 10 billion ICs being shipped annually.

Physical Design Group

Products

Standard Cell

Memory complierCustom memories

GPIO

Architect productMRAM Compiler

DFITQV & PQV

POP IP

Foundry partners

CPU TC


Transforming markets with optimized physical IP

AutomotiveMobile and Consumer Networking and Servers IoT

• High performance• Low power• Cost (area)• sensitive• Flexible

performance requirements

• High temperature• Fault tolerance• Long lifetime• Low power• Non-volatile

memory

• High performance• Fault tolerance• Long lifetime• Continuous

operation

• Very low power• Low voltage• Very low cost• Non-volatile

memory

Mainstream• 16/14/12/11nm• 28/22nmPremium• 7/5nm

Networking• 7/5nm• 16/14/11nm• 28/22nmServer• 7/5nm

Engine & Body Control• 55/40nm• >130nmADAS, self driving• 7nm• 16/14/11nm• FDSOI• eMRAM

Ultra Low Power• >40nm• 28/22nm• eMRAM• FDSOIAdvanced Applications• 16/14/12/11nm


Arm Artisan Physical IP and Samsung Foundry partnership Over 3 Billion Chips Shipped with Arm Artisan Physical IP

65nm G/LP

45nm LP

32nm LP

28nm LP/LPP

14nm LPP/LPC

28FDS

11LPP(incl AG1 Auto)

7LPP

In production

In development

+Delivering Successful Production SoC from 65nm to 5nm

5LPE

Download Artisan IP NOW

18FDS

In planning

Next nodes


Benefits and challenges of designing with FDSOI

Benefits

• FDSOI enables better scalability than bulk• Higher performance• Low power• Better reliability• Wider operating range through back bias

Challenges

• All Vts cannot be mixed together• Separate blocks required for flipped well and

conventional well devices• Voltage area required for each bias domain

• Power domains have strict rules regarding finishing cells

• Power grid is more complex• Power supply grid + a power bias grid

• ECO loops can be more difficult• VT swap is not always possible: timing

convergence

Body bias


Unique well structures for 18FDS

• Two well structures offered• Both forward and reverse biasing supported;

range based on Vt1. Traditional well devices

– NMOS in pwell; PMOS in nwell– Goal is to increase Vt for power reduction

2. Flipped well devices – NMOS in nwell; PMOS in pwell– Goal is to decrease Vt for increased

performance

• Combine with multiple channel lengths and a range of bias voltages:→ Increases options for speed/leakage optimization and trade-offs

PW NW

NMOS PMOS

P-SUB

NW

D-NW

PWNW

PMOSNMOS

P-SUB

D-NW

PW NW

NMOS PMOS

P-SUB

NW

D-NW

PWNW

PMOSNMOS

LVT, SLVT or ULVTRVT or HVTTraditional wells

PW NW

NMOS PMOS

P-SUB

NW

D-NW

PWNW

PMOSNMOS

P-SUB

D-NW

PW NW

NMOS PMOS

P-SUB

NW

D-NW

PWNW

PMOSNMOS

LVT, SLVT or ULVTRVT or HVT Flipped wells

Wider reverse bias voltage

range supported

Wider forward bias voltage

range supported


Wide-range of design optimization points• Figure of Merit (FOM) evaluation :

• Modelling of CPU based critical paths• Evaluation of RC models from PDK• Early evaluation of logic cell architecture

performance based on real extracted netlists

• FOM Conclusions:• Bias modulation provides

– More leakage impact for traditional wells– More performance impact for flipped wells

• Wide range of leakage/performances available by biasing modulation

• Multiple Vth allows on the fly design optimization

Traditional Well Devices

Flipped Well Devices

Bias modulation

Normalized Performance

Nor

mal

ized

Leak

age

Leakage vs PerformanceAcross Vt Devices

(single channel length)

Vt 1: Lowest Vt (fastest)

Vt 2

Vt 3

Vt 4

Vt 5: Highest Vt (best leakage)


Extending the PPA range with multiple channel lengths• Additional modulation capability with

Channel Length (CL) options• Increase fine-grain tuning for design-

specific PPA optimization• Free to mix any/all CLs• Apply bias modulation to each Vt and CL

combination

• Fine grain performance/leakage trade-offs enabled by body-biasing• Enhanced by Vt and channel length

options• Continuous range for optimization – no

gaps in performance or leakage

CL3

CL3, Vt1

CL2CL1

CL1, Vt2

Vt1

Vt2

Vt2

Vt4

Vt5

Traditional Well Devices

Flipped Well Devices

Normalized Performance

Nor

mal

ized

Leak

age

Plus bias modulation over each Vt and CL

Leakage vs PerformanceAcross Vt Devices

(different channel length)


Industry’s 1st – broadest FDSOI Foundation IP & solutions

Memory Complier

Standard Cell• Comprehensive cell set for

broad application coverage• HD, UHD & Thick Gate Oxide

Power management & ECO

• 7 Memory Compilers• Multi periphery Vt options• Extensive features set

Complete Physical IP Platform

§ Foundry sponsored (POP IP end-user licensable)§ Support wide range of applications from

mobile, consumer, IoT, auto and ML/AI§ Automotive Grade 1, ASIL-D support§ POP IP for Cortex-A55 ,Cortex-R52 and

Cortex-M33§ Design kits available from 2H19

Architect products

GPIO• GPIO 1.8V• GPIO 3.3V

POP IP• Cortex-A55 with DynamIQ• Cortex-R52• Cortex-M33

• Logic libraries• Memory complier• IO’s

Samsung Foundry18FDS


The goal of POP IP isto enable partners to implement and tapeout Arm coreswith the fastest turn-around time and best-in-class PPA while maximizing the benefits of process technology

Artisan Physical IP

POP Reference

Scripts

POP UserGuide

Artisan® ArchitectProducts

POP LandingTeam Support

CPU optimized Physical IP

RTL-GDS scripts for Major

EDA tool chains

Comprehensive implementation

methodology

Design utilitiesto improve

implementation


Leveraging 18FDS Biasing with POP IP on Cortex A-R-M cores

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0.00001 0.0001 0.001 0.01 0.1 1 10

Nor

mal

ized

Perf

orm

ance

Normalized Power

Cortex-A55

HighestPerformance

Forward BiasVoltage =1V

Cortex-R52Real-Time Processing

Reverse BiasVoltage =1V

Cortex-M33Lowest Power & Cost

Reverse BiasVoltage =1V

Sign-off : TT/Vnom/25c (Power and Performance), SSG/Vnom-10%/m40c (Setup); FFG/Vnom+10% /125c (Hold)


Arm Artisan IP creation products for additional PVT optionsBiasing condition multiplies PVT options – need for flexibility by designers

Extend standard PVTs

• Artisan platform will provide PVTs covering full spectrum• Designers may want additional process, voltage

and temperature combinations

• Arm provides a flexible solution with Artisan Architect products

Artisan Architect products support in-house creation of additional PVT corners• Delivers Arm characterization environment

• Logic Corner Generator (LCG)• I/O Corner Generator (IOCG)• Full char; mix-n-match with Arm-supplied PVTs

• Delivers simple methodology to add PVTs to an entire memory compiler• Memory Compiler Corner Generator (MCCG)• Plug in database – run any instance at new PVT

Process range VDD (V) range Temp range (ºC) Bias type Device well type Nwell body-bias (V) Pwell body-bias (V)

SS, TT, FF VDD-10% to VDD+10% -40 to 150

Forward biasingTraditional well Range 1 Range 2Flipped well Range 3 Range 4

Reverse biasingTraditional well Range 4 Range 3Flipped well Range 2 Range 1


eMRAM value proposition: cost and application-specific PPA

Physics results in Retention vs. Endurance/Speed trade-off

Application-specific tuning

Working memory for SoC providing area, power and BoM savings

eMRAM for storage eMRAM as working memory

Storage memory for MCU as eFlash becomes cost-prohibitive

Source: IMEC, 2018Storage

Working Memory

Novel working-storage memory


Another industry’s 1st - eMRAM compiler IP (deployed on FDSOI)Announced in 2018 and latest news - silicon testchip back and functional!

32Mb testchip

128Mb testchip

Sample#

RD0000 RD1111 RD0000 RD1111 RD0000 RD1111 RD0000 RD1111 RD0000 RD1111 RD0000 RD1111 RD0000 RD1111 RD0000 RD1111macro0 0 0 0 0 1 0 1 0 3 0 3 0 2 0 2 0macro1 0 0 0 0 2 0 2 0 0 0 0 0 2 0 2 0macro2 1 0 1 0 2 0 2 0 3 0 3 0 3 0 3 0macro3 0 0 0 0 1 0 1 0 2 0 2 0 0 0 0 0macro4 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0macro5 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0macro6 2 0 2 0 0 0 0 0 0 0 0 0 1 0 1 0macro7 1 0 1 0 3 0 3 0 1 0 1 0 3 0 3 0macro8 0 0 0 0 0 0 0 0 2 0 2 0 0 0 0 0macro9 0 0 0 0 0 0 10 0 3 0 3 0 5 0 5 0macro10 1 0 1 0 1 0 1 0 0 0 0 0 3 0 3 0macro11 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0macro12 0 0 0 0 0 0 0 0 3 0 3 0 3 0 3 0macro13 0 0 0 0 0 0 0 0 0 0 0 0 2 0 2 0macro14 0 0 0 0 0 0 1 0 2 0 2 0 0 0 0 0macro15 0 1 0 1 2 0 2 0 2 0 2 0 2 0 2 0

1025C 105C

525C 105C

5425C 105C

6025C 105C

Read fail bit count on early 32Mb testchip silicon

• 1-128Mb capacity, SRAM interface w/ X32, X64 and X128 wide IO, ECC, built-in repair analysis and scan


Summary• Extended power-performance dynamic range with FDSOI process technology• Full potential of body biasing together with Vt/CL allows for continuous optimization

points• Announcing industry’s broadest FDSOI foundation IP and solutions portfolio on

Samsung Foundry 18FDS• POP IP on Arm Cortex A, R, M cores incorporates body biasing flexibility• Architect product design utilities to allow users to have additional PVT corners• Additional differentiated solutions with eMRAM compiler starting at 28FDS node• Complete IoT system silicon demonstrator platform in development with FDSOI and

eMRAM


Start Your Designs with Arm Today - Talk to Us! • Find out more at https://developer.arm.com/ip-products/designstart/physical-ip

• Contact us at [email protected] for more information

DesignStartMultiple free library programs available now, and this is just a start…..

https://developer.arm.com/ip-products/designstart/physical-ip

mailto:[email protected]

https://developer.arm.com/ip-products/designstart/physical-ip

mailto:[email protected]

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