fdsoi: a low power, high performance technology scalable...

3rd annual SOI Tokyo Workshop, May. 31st, 2017

FDSOI: A LOW POWER, HIGH PERFORMANCE TECHNOLOGY SCALABLE DOWN TO 10NM

L. Grenouillet, Silicon Component Division, CEA-Let i, FRANCE

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• 3 waves of performance boosters:• Material, including mechanical stressors• High-k / metal gates (gate first or gate last)• Fully Depleted devices

SCALING OF CMOS TECHNOLOGY

M. Bohr et al (Intel) et al, 2011

3rd annual SOI Tokyo Workshop, L. Grenouillet, May. 31st, 2017

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• 3D• Symmetrical double gate

2 MAIN ALTERNATIVES BELOW 28NM

FDSOI MOSFETFinFET

ST/Leti

Intel

14nm:IntelTSMC SamsungGF

28-14nm:STMicroGFSamsung

• Planar• Asymmetrical dual gate


| 43rd annual SOI Tokyo Workshop, L. Grenouillet, May. 31st, 2017

• Introduction/Context

• 28FDSOI, 22FDX/14FDSOI:• Main features and interest

• Performance boosters for 10nm• Electrostatics• Strain boosters• Back Biasing• Benchmarking vs FinFET

• Key messages

OUTLINE





• Key messages

OUTLINE

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N.Planes et al., VLSI’12

28nm design rules

28FDSOI VERSUS BULK

E. Beigne et al., ISSCC’14


• Better electrostatic control on FDSOI than planar b ulk• 32% frequency improvement at VDD=1V • 84% frequency improvement at VDD=0.6V

� FD devices are attractive for low voltage applications


14NM/22NM FDSOI PERFORMANCE BOOSTERS

28FDSOI

22FDX14FD

Performance

In-situ doped epitaxy

StrainedSiGe channelfor PFET

Raccess

Carrier mobility

+50% frequencywith 100mV VDD

reductionElectrostatics

EOT scaling6nm channel20nm BOX

M. Haond et al., S3S’2014 F. Andrieu et al., ESSDERC’14


• -34% delay vs 28nm FDSOI at same static leakage dem onstrated with -100mV V DD operation (0.8V vs 0.9V)

14NM/22NM FDSOI PERFORMANCE

28FD Vdd

14FD Vdd

Delay @ Istat

0.9V 0.8V -34%

Pstat = Vdd×IOFF

O. Weber et al., VLSI’2015

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• Main objectives: • Surface model including inversion at Back Interface• Implemented in ALL the commercial simulators• Used and validated by Industry

LETI UTSOI 1&2 MODEL

GateSource Drain

Back gate

GateSource Drain

Back gate

10-2

0 100

5 10-5

1 10-4

1.5 10-4

2 10-4

2.5 10-4

3 10-4

0 0.2 0.4 0.6 0.8

gm (

A/V

)

VGS

(V)

1 10-3

0 100

2 10-5

4 10-5

6 10-5

8 10-5

1 10-4

1.2 10-4

1.4 10-4

0 0.2 0.4 0.6 0.8

Id (

A)

VGS

(V)

0 100

2 10-4

4 10-4

6 10-4

8 10-4

1 10-3

0 0.2 0.4 0.6 0.8

VGS

(V)

Id (

A)

0 100

2 10-4

4 10-4

6 10-4

8 10-4

1 10-3

1.2 10-3

1.4 10-3

1.6 10-3

0 0.2 0.4 0.6 0.8

gm (

A/V

)

VGS

(V)

10-9

10-8

10-7

10-6

10-5

10-4

10-3

0 0.2 0.4 0.6 0.8

10-8

10-7

10-6

10-5

10-4

10-3

0 0.2 0.4 0.6 0.8

VBS=-5, 0 & 5 V

VDS=50 mV

VDS=0.9 V

VDS=50 mV

VDS=0.9 V

VBS=-5, 0 & 5 V

VBS=-5, 0 & 5 V

VBS=-5, 0 & 5 V

⇒Today, LETI-UTSOI is the unique model used in the industrial environment to sub 28 nm FDSOI tech.

[T. Poiroux et al., IEDM 2013] [O. Rozeau et al., SOI conf. 2011]

Leti-UTSOIFDSOI Model

based on PSP-model

Leti-UTSOI 2FDSOI Model with

back gate coupling


• Key features for FDSOI:• LETI already reported fT/fmax =390/385GHz at 28nm• fT/fmax of 375/290GHz and 260/250GHz for NMOS & PMOS, respectively,

demonstrated in 22FDX• High performance achieved thanks to low parasitics ( Cgd and Rgate)

• Good Cgd thanks to gate first process (no HK along the gate edges)• Good Rgate (polySi vs highly resistive metal in gate last)

RF PERFORMANCE

0

100

200

300

400

500

10 100

Cu

t-o

ff F

req

ue

ncy

(F

T)

GH

z

Gate Length (nm)

FDSOI vs FinFET vs Litterature

Litterature

FDSOI Data

FinFET Data

FDSOI projection

FDSOI Trend

FinFET Trend

R. Carter et al., IEDM’16


• Compared to bulk and FinFETs, FDSOI benefits from its undopedchannel for G m/Gd and V th mismatch, two key characteristics for analog devices

ANALOG CHARACTERISTICS

L. Le Pailleur et al., ESSDERC’16





• Key messages

OUTLINE


BOOSTER ENABLERS FOR 10NM

14nm

10nm

Performance

• BOX thicknessscaling

• Dual-STI

• High-Ge SiGeB / HS SiP source/drain

• High-Ge channel• SAIPS• BOX creep• STRASS *

• sSOI *

• Gate-last *

Back bias

Carrier mobility -40% Power @

same speed

Electrostatics

• EOT scaling• Low-k spacer / epi

facetting• Channel

thickness=Lg/4

* Possible second generation


• Electrostatic control improved by thinning T BOX

• Scalability down to 10nm node• Devices already processed with 3.5nm SOI film

ELECTROSTATIC CONTROL

Node 28nm 14nm 10nm

TSOI (nm) 7 6 5

TBOX (nm) 25 20 15

K. Cheng et al, VLSI 2011

Si data for LG=15nm:TSOI

BOX

TSOI

BOX

TSOI

BOX


BOX scaling bonus: • Back bias efficiency improves (body factor improvement)

BURIED OXIDE SCALING

10 1000

50

100

150

Bod

y F

acto

r (m

V/V

)

BOX thickness (nm)

25nm BOX

20nm BOX

15nm BOX

10nm BOX

28FDSOI

14FDSOI

10FDSOI100mV/V

75mV/V65mV/V

L. Grenouillet et al., S3S’13


NMOS PMOS

• Strain SOI: +100% on narrow NMOS• Strain SiGe: +60% on narrow PMOS• Design/Technology co-optimization mandatory to get full strain effect

• e.g. continuous RX

STRONG EFFICIENCY OF STRAIN ON FDSOI!!

-11

-10

-9

-8

-7

-6

0 250 500 750 1000 1250

ION (µA/µm) (V D=VG=0.9V)

I OF

F (A

/µm

) (V

D=0

.9V

)

+100%

Open : W=80nm sSOI

+35%

Close : W=0.5µm SOI

K. Cheng et al., IEDM’12


• To get higher strain (=higher performance):• Increase the Ge content in the channel and in the source/drain

GE CONTENT IMPACT

0 10 20 30 40 50-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

xGe =40%

xGe =35%

xGe =30%

xGe =25%

Long

itudi

nal s

tres

s σ L [G

Pa]

yGe

concentration in raised source/drain [%]

Simu

B. de Salvo et al., IEDM’14

OF

F c

urr

en

t, I

OF

F(A

/µm

)

ON current, ION (µA/µm)

10-5

10-7

10-9

Ref cSi

25% cSiGe

300 500 700 900 1100 1300

Ion Gain ~ 65%

35% cSiGe on sSOI

35% cSiGe

Lg ~20nm

W=240nm

Vd=0.9V

R. Berthelon, F. Andrieu et al., SSE’16


OTHER MOBILITY BOOSTER OPTIONSPFET:SAIPS = Self Aligned In-Plane Stressors

NFET and/or PFET : BOX CreepThe strained material (eg nitride)

on top of SOI induces inverse

strain into the underlying Si

thanks to the BOX creep occurring

at high temperature ( ~1.2GPa on

mesa)

The SiGe film on the S/D area of

PFET is enriched in Ge in order to

create a lateral compressive stress

into the SiGe channel.

NFET:STRASS = Strained Si by Top Recrystallization of Amorphized SiGe/SOI

The top SiGe seed (relaxed SiGe after

amorphization) imposes during

recrystallization its lattice parameter

to the bottom Si which turns into

tensile Si (1.5Gpa on blanket)


• Very effective transmission of the strain • Uniaxial compressive strain• Self-aligned process• No modification of the channel itself

SAIPS FOR PFET BOOST

SiGe epi + condensation Oxide removal

SAIPS = Self-Aligned In-Plane Stressors

L. Grenouillet et al., S3S’13


• PED measurements demonstrates between -0.5% et -0.8% additional strain (gate first configuration) brough t by SAIPS(~ -1GPa additional compressive stress)

• Consistent with mechanical simulations (A. Idrissi-El Oudrhiri et al. – SISPAD’15)

SAIPS FOR PFET BOOST

L. Grenouillet et al., unpublished


• BOX creep is based on nitride deposition + anneal ( like stress memorization)

• The strained material (eg nitride) on top of SOI ind uces inverse strain into the underlying Si thanks to the BOX cre ep occurring at high temperature

• +1.2 GPa tensile stress already demonstrated to boos t nMOSFETs(morpho)

BOX CREEP FOR NFET/PFET BOOST

A. Bonnevialle et al., VLSI’16


• Localized compressive SGOI for pFETs• Smart and effective integration • + 6 % Ion/Ioff improvement on pFETs• + 5 % in Iodlin due to stress created by BOX creep• Analytical Model of Stress-Enhanced Mobility

• Based on mechanical simulations• Reproduces the Iodlin trends wrt Lact, W• Highlights the best layout configuration

BOX CREEP FOR NFET/PFET BOOST



• The top SiGe seed (relaxed SiGe after amorphization) imposes during recrystallization its lattice parameter to t he bottom Si which turns into tensile Si (1.5Gpa on blanket)

• +1.6 GPa in SOI active regions demonstrated

STRASS FOR NFET BOOST

STRASS = Strained Si by Top Recrystallization of AmorphizedSiGe/SOI



• Back bias is a unique feature of FDSOI (second gate)• Dynamic modulation of VT• Perf/Power trade-off improvement:

• Depending on the static leakage allowed for a given application, the right [Vdd;FBB] combination can be chosen for maximizing the perf./power trade-off.

• Process variability compensation

BACK BIAS INTEREST

O. Weber et al.., VLSI’14

O. Weber et al.., ICICDT’17


• Dual STI demonstrated already• 400mV VT adjustment flexibility demonstrated

FULL BACK BIAS CAPABILITY WITH DUAL STI

L. Grenouillet et al., IEDM 2012


• Versatile dynamic V T tuning• Same device: 10 4 IOFF range, ~x2 I ON

FULL BACK BIAS CAPABILITY WITH DUAL STI

400 600 800 1000 12001E-10

1E-9

1E-8

1E-7

1E-6

1E-5

VDD

=0.9V

I OF

F (

A/µ

m)

ION

(µA/µm)

BB=+2V BB=+1V BB=-0V BB=-1V BB=-2V

+25%

2dec

L. Grenouillet et al., IEDM 2012


• LETI has worked on the DEVICE construction for next generation (w/ 3 VT flavors)• On Dual-STI for bidirectional body bias capability: FBB and RBB possible on the same

devices

• VT flavors are fully swappable and fully mixable. No tap issues, similar DR constraints as 22FD

DUAL STI AND VT CONSTRUCTION

P+ P+N+ N+

nMOS

N+ N+ P+ P+

pMOS

P-well

SLVT RVT SLVT LVT

P+

T3 isolation

P+ P+

RVT

P+N+ N+

LVTVDDsGNDs





• Key messages

OUTLINE


• Preliminary assumptions:• FDSOI: localized sSOI (+1.35GPa) +80% on mobility

• FinFET: -30% on mobility

NMOS MOBILITY BOOSTER

Reference: B. DeSalvo et al. IEDM 2014 (Leti, ST, IMEP, SOITEC, IBM)

FDSOIFDSOI

FFFF

Reference: R. Coquand et al. SSE 2013 (Leti, ST, IMEP, IM2NP)

Symbols: exp. data

10FF

14FDSOI

10FDSOI

+80%

-30%

FinFET achieves a low mobility due to transport direction (or/and modification of conduction masses)

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• Preliminary assumptions:• FDSOI: 25% sSiGe (+1.67GPa)

• FFSOI: +40% on mobility

PMOS MOBILITY BOOSTER

Reference: B. DeSalvo et al. IEDM 2014 (Leti, ST, IMEP, SOITEC, IBM)

FDSOIFDSOI

FFSOIFFSOI

Reference: R. Coquand et al. SSE 2013 (Leti, ST, IMEP, IM2NP)

10FF

14FDSOI

10FDSOI

+90%

The engineering of stressors on FDSOI (SiGe channel, SAIPS, etc) allows to increase significantly the mobility


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• Major difference between FDSOI and FF:• Better electrostatic on FF (symmetric double-gate behavior)

• Better mobility on FDSOI due to the use of sSOI for nfet and cSiGe for pfet

• What is the difference on circuit performances?

PROCESS ASSUMPTIONS: 10FDSOI VERSUS 10FFSOI

10FDSOI 10FF

CPP 64nm 64nm

Nominal supply voltage 0.75V 0.75V

Physical gate length 20nm 20nm

Gate stack Gate Last Gate Last

EOT 0.82nm 0.82nm

nMOSFET µ-boost sSOI-like No

pMOSFET µ-boost 25%-cSiGe40% raised S/D SiGe

Si channel40% raised S/D SiGe


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• Process assumptions

DEVICE DEFINITION

Lg=20nm

CPP=64nm

TSITbox

10FDSOI 10FF *

Si “channel” thickness TSI = 5nm WFin = 8nm

Buried oxide TBOX = 15nm ----

Channel width W = 130nm HFin = 42nm

Fin pitch ---- FP = 40nm

Not at scale

HFin

WFin

CPP=64nm

* Geometry based on IBM publication: Symposium on VLSI Tech. 2014

IBM VLSI’14


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• 10FDSOI versus 14FDSOI: • +25% on speed at constant static power• -43% on dynamic power at constant speed

• FDSOI versus FinFET: • Similar speed at the same static power• 20% dynamic power penalty for FinFET wrt FDSOI at same delay

FINFET VERSUS FDSOI

10FF

10FDSOI

10FDSOI-FBB

14FDSOI

14FDSOIVdd=0.8V

10FFVdd=0.7V

10FDSOIVdd=0.7V

Vdd=0.7V

>25%

-20%

-43%

Pre-layout 21stages FO4 ring oscillatorsPre-layout 21stages FO4 ring oscillators



• Advantage of FDSOI for power efficiency demonstrated

• Scaling path identified down to 10nm node

• Strain management is mandatory for future

• Ultra-Low Power design and related IP are Key for Back Bias adoption

• Competitive Power advantage versus FinFET and Back bias differentiation for Power efficiency

KEY MESSAGES


• Some applications need more digital, more density a nd more performance,

• Others need less power, low-cost, more sensing (ana log), more connectivity (RF), more flexibility, and more energ y efficiency

• FinFET and planar FDSOI fulfill different requiremen ts for different applications

CONCLUSION

eFlash

BEOL eNVM

IoTProducts

FINFET 14/16nm

22FDSOI 28FDSOI 28HKMG

Cost

Perf./Power w/ back bias w/ back bias

Leakage w/ back bias w/ back bias

Analog/RF

O. Weber et al.., ICICDT’17

fdsoi: a low power, high performance technology scalable...

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