FDSOI, RRAM AND 3D ARE KEY TECHNOLOGIES FOR AI CHIPS AND 5G

Jean-René LEQUEPEYS – CTO & LETI Deputy Director

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• To address future computing demands, CEA-Leti isworking on a roadmap that leverage a mix oftechnologies: FDSOI, Embedded NVM, newparadigms for computing and 3D integration.

• At the same time SOI technology keep beingdeveloped for the 5G demands and looking atfurther communications needs, and is also welladapted to Edge AI.

CONTEXT

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1. Short LETI’s overview

2. Main computing challenges

3. FD SOI Technology

4. RRAM Technology

5. 3D Technology

6. 5G and Beyond 5G applications and chips

7. AI applications and chips

AGENDA

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Short LETI’s OVERVIEW

1

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Founded in 1967

France, USA, Japan

2,000 People

> 2,760 Patents in Portfolio

350 Industrial Partners

> 65 Startups Created

10,000 m² Cleanroom 200-300mm

315 M€ Budget 85% from R&D contracts

Grenoble (FR)

LETI’S KEY FIGURES

© J

acques-M

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RA

NC

ILLO

N /

CE

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Géra

rd C

OT

TE

T/

CE

A

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Leti

Academics

Industrial

Proof of Concept

Upstream Research

Pre-IndustrializationConcept Maturation

Production

Demonstrators l Prototyping

Transfer

• Long-term partnerships

• Milestones-oriented projects

• Highly available and flexible teams

LETI’S MISSION : BRIDGING THE GAP BETWEEN ACADEMIA & INDUSTRY

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LETI'S INTERNATIONAL RECOGNITION (EXPERTISE AND SKILLS)

Reuters RTO ranking (2016) : CEA #11. Alternative Energies and Atomic Energy

Commission (France)2. Fraunhofer Society (Allemagne)3. Japan Science & Technology Agency (Japon)4. 4 U.S. Department of Health & Human (USA)5. National Center for Scientific Research (France)

Reuters RTO ranking (2017) : CEA #21. Health & Human Services Services Laboratories

(USA)

2. Alternative Energies and Atomic EnergyCommission (France)

3. Fraunhofer Society (Allemagne)4. Japan Science & Technology Agency (Japon)5. National Institute of Advanced Science & Technology

(Japon)

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96 New Concepts

54

Explorations

44

Incubations

18

Incorporations

12 SERIES A

€ 33.9M

LETI’S START-UP PROGRAM: 2013-2018 KEY FIGURES

2.5 M€

13.7 M€

7.8 M€

2.2 M€

30 M€

23.6 M€

7 M€

Latest rounds

Last 12 months

IPO

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Main computing challenges

2

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Economics of Moore’s law:

� Very few players (2-3) will be able to

play, and we will end up with one or

two fabs in the world going beyond

7nm

� Could be detrimental for innovation Source: L. Su (AMD) – ERI Summit 2019

Source: Qualcomm, ERI Summit 2019

4 MAIN RED WALL FOR COMPUTING CHALLENGES (1/4)

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4 MAIN RED WALL FOR COMPUTING CHALLENGES (2/4)

Memory Red Wall:• The data load is increasing faster than

Moore’s Law, and the data overflow makes current memory technologies a limiting factor

• Most of the data being stored (most estimates suggest at least 80% of it) is still in a completely unstructured formand this presents difficulties when using it for analytical purposes.

• Only 5% of stored data is analyzed

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Data Traffic Red Wall:

• The huge increase in transmitted data

induces drastic issues to bandwidth

availability and slowed down the data traffic

• The number of devices connected to the

Internet is expected to exceed 1 trillion

devices over the next decade or so.

• A data deluge of biblical proportions is

headed our way (EE Times, September 26, 2019)

Source: Ericsson Mobility report June 2018

4 MAIN RED WALL FOR COMPUTING CHALLENGES (3/4)

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Power red wall:• In 2018, Chinese data servers (8% of the WW

data servers) produce 99Mtons of CO2, i.e.

equivalent to 21 Millions of cars

• In 2015, Internet connection has been

estimated to 0.06 kWh/Gbytes

• Data traffic x2 every 4 years

• Energy consumption of network

connections estimated at 1 000TWh in 2030

Network-connected energy consumption by component 2010 -2030

� Upstream energy use of the communications and data networks and the data center which is increasing till 2012 and slowly decreasing� Network standby energy use of the edge equipment, which is rapidly increasing over the period as more devices are connected� Network active energy use of the edge equipment and LAN equipment, which is also increasing over the period

4 MAIN RED WALL FOR COMPUTING CHALLENGES (4/4)

Source: IEA 4E EDNA Report June 2019

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INCREASE PERFORMANCE: A SYSTEM APPROACH FOR CHIPS MAKERS

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NEW PARADIGM: DATA CENTRIC COMPUTING

“Data is to this century what oil

was to the last one:

� a driver of growth and change”

–The Economist

Source: Qualcomm, ERI 2019

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INTRODUCTION OF NEW CONCEPTS ARE NECESSARY

Source: Dickerson (CEO AMAT) – ERI Summit 2018

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FDSOI

3

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28FDSOI IS TODAY A REALITY : PRODUCTS ARE THERE

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FDSOI & RFSOI: A LONG HISTORY OF SUCCESSFULL PARTNERSHIPS

2017

12FD Early development

2019

Sub 10nmEarly development

SOI invented @ LETI and transferred to industry

FDSOI : A high performance, low power and low cost solution well

adapted to 5G, AI and IoT chips

幻灯片 19

DKA11 DE KERLEAU Armelle 112301, 2019/10/29

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FDSOI SCALING PATH DOWN 10NM

FDSOI is scalable down to sub-10nm by :

• Thickness Tsi ↘: for electrostatics

• Width W ↘: for density

• Strain ↗ in high mobility channels :

for performance

FDSOI allows to dynamically change the workingpoint of logic circuits, compared to FinFET wherethe working point – low power or high performance – is done at design time.

It has already been demonstrated that is easier to design analog circuits in planar FDSOI.

R. Carter et al., IEDM’16 (GF-LETI)

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• Extremely scaled FDSOI CMOS have already demonstrated

• With excellent device performance

A. Khakifirooz et al., EDL’12 (IBM)V. Barral et al., IEDM, 2007See also K. Uchida works with poly/SiO2 gate stacks

FDSOI DEVICE SCALABILITY: EXPERIMENTS DONE @ LETI FAB

3.5nm

6nm

6nmRBB

3.5nm

6nm

6nmRBB

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LETI’S FDSOI ROADMAP WITH PERFORMANCE BOOSTERS

Speed

28nm FDSOI

+5

6%

22nm FDSOI

+2

0%

• Tsi, EOT down-scaling

• cSiGe PFET

• In situ doped RSD

• 20nm BOX

• CPP=96nm

• MxP=80nm

12nm FD-SOI

• Dual-STI

• Dual CESL

• CPP=84nm

• MxP=64nm

Sub-10nm FD-SOI

• Tsi, EOT down-scaling

• Localised sSOI NFET

• 2nd Gen cSiGe channel PFET

• Gate-last ?

14LPP

+2

0%

10LPP

BB

BB

7LPP

• CPP=122nm

• MxP=90nm

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• Booster objective: finding different power-efficient

working points, running applications at best power-

efficient points

• Technique:

• Ultra-Wide-Voltage-Range power management methodology with sensors and adaptive back-biasing

• Gains:

• 10-20% performance boost

@ high voltage

• Up to 60-70% power gain

@ low voltage

FDSOI DESIGN ADVANTAGE : ULTRA-WIDE-VOLTAGE-RANGE

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RRAMNON VOLATILE MEMORIES

4

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Volatile

Non-volatile

STANDALONE EMBEDDED

SPECIFICATIONS:

SPEED

POWER CONSUMPTION

ENDURANCE

HIGH TEMPERATURE

COST

SCALING

MAIN RESEARCH FOCUS:

MATERIAL STACKS

SELECTOR

ARCHITECTURES

HW ACCELERATORS

IC DESIGN

Remote Secondary StorageCloud Storage

Local StorageFlash

Main MemoryDRAM

Cache(L1-L2-L3)

Register files

AluFlip-Flops

Very expensive(part of CPU)

Very expensive($150/MB)

Inexpensive($0.58/MB)

Very inexpensive($0.0025/MB)

Least expensive

Storage Class Memory

ADVANCED MEMORIES, NOVEL ARCHITECTURES @ LETI

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Large variety of materials available

GeSbTeSiOxTaOxZrO2AlOxVOx

HfAlxOyGeAsSbTe

Large variety of Memories available

pSTT-Magnetic RAMConductive Bridge RAM

Oxide Resistive RAMFerro-electric RAM

Phase – Change Memory

200/300 MM

INTEGRATION

DEFINITION OF TECHNOLOGY

SPECIFICATIONS

MODULE

DEVELOPMENT

TEST &

CHARACTERIZATION

DESIGN

ENABLEMENT

MODELING,

SIMULATION & NANO-

CHARACTERIZATION

MEMORY, A UNIQUE VALUE PROPOSITION @ LETI

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New embedded memories can be integrated with FDSOI to enlarge its range of applications:

• Microcontrollers (MCU), Micro Processor Unit (MPU)

• Secure applications

• AI at the edge, IOT chips

FDSOI AND NEW EMBEDDED MEMORIES

CEA-Leti: Front End integration (pre M1) of OxRAM cell in 28 FDSOI Samsung: dense STT-MRAM integration in 28 FDSOI

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• Introduction or Resistive Memories as

replacement for SRAM, Embedded Flash

and Standalone memory

• Several key advantages like :

• Increased density

• Lower power

• Better latency

• New architectures like neuromorphic and more generally In-Memory-Computing

STORE DATA WITH NON VOLATILE MEMORY

• One example: OxRAM based TCAM

(D. R. B. Ly, et al., “In-depth Characterization of Resistive Memory-Based Ternary Content Addressable Memories”, this IEDM)

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3D INTEGRATION

5

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Non Volatile MemoryStacking

Analog Computingwith Spikes

WITH 3D WE CAN REDUCE THE AMOUNT OF ENERGY PER OPERATION

Current Architecture

Memory Stacking

Green + NVM

In Memory ComputingLatest Silicon result @ LETI

show a x30 gain in power

80% of power

conception due to

data movement

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DESIGN PARTITIONING FLEXIBILITY BY 3D

SEVERAL OPTIONS

• Toolbox of 3D

technologies to improve

communications between

functional blocks

• Heterogeneous

integration to make

possible new

architectures both in HPC

(Digital-Memory) and

Embedded (Digital-

Memory-Analog-Sensors)

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• Parallel heterogeneous integration, the “chiplet” concept and

hardware realisation @ LETI : “INTACT” demonstrator

NEW CONCEPT FOR COMPUTING BASED ON CHIPLETS

Direct Hybrid

Bonding

Pitch <10µmWtW; CtW

TSV : Ø 10µm, Height 100µm

� Using 28nm FDSOI chiplets (x6 with 16 cores each)

• Low Power Compute Fabric• Wide Voltage Range (0.6V – 1.2V)• Body Biasing for logic boost & leakage ctrl

� With a 65nm Active Interposer• Power unit (Switched Cap DC-DC conv.)• Interconnect (Network-on-Chip)• Test, clocking, thermal sensors, etc

� Booting LINUX for running real applications

� ISSCC 2020 paper accepted

µ-bumps

Ø 10 µmPitch 20 µm

Inter-dies interconnect

Intra-dies interconnect

This work was funded thanks to the French national program“Programme d’Investissements d’Avenir, IRT Nanoelec” ANR-10-AIRT-05.

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3D STACKING FOR SMART IMAGER @ LETI

Hybrid Bonding of 2 dies L1@130 nm / L2@130 nm; Die size :

160 mm²

Image sensor:

• 192x256 @ 5500 fps or 768x1024 @ 60 fps

• 12 µm pixel, 75% fill factor,

192 processors (3072 PE):

• Processing : 72 GOPS, 11.7 MOPS/mW

• 1 k instructions / pixel @ 1000 fps

• Distributed memory

• Each processor can execute a different code in a set

Processor array dieBSI sensor die

HIGH PERFORMANCE MEASURED ON SILICON

x100 computing power

x10 energy efficiency

/15 processing latency

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• 3D integration is a natural extension of FDSOI to reach ultimate density and connectivity.

• Back bias can be maintained• New interconnect layers are introduced in the middle to alleviate routing congestion• Top and bottom layers are homogeneous (same type and structure of devices

CoolCUBE (MONOLITHIC 3D)

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5G and beyond

6

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• Short term (End 2019)

• Integrated demonstrator of 26GHz access link• Antenna/RF/Digital

• Grant experimental license from ARCEP at 26GHz

• Mid term (2 years)

• Develop Smart Active Antenna system• Antenna/Integrated RF and Digital

• Demonstrate fast and efficient beamtracking features• Propose innovative integrated modules, break silots

• Long term (5+years)

• Prepare Beyond 5G system• New frequency bands, new challenges and opportunities

• Move towards CMOS integration and R&D on new materials

5G PROGRAM AT A GLANCE @LETI

KPIs

■ 10Gbps – 1 Tbps■ kbit/s/Hz through SDMA■ Antenna/RF/Digital integration, m3 -> cm3

■ Remote Radio Unit power efficiency,50% -> 75%

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• 5G @Leti, main activities in various laboratories

5G PROGRAM @LETI EXPLOITING SOI TECHNOLOGIES

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AI

7

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THE NEED FOR AI CHIPS AT THE EDGE

Source: Tractica - Sept 2018

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WHO WANTS AN AI-CHIP ?

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A FULL OFFER FOR EDGE AI CHIPS DEVELOPMENT @ LETI & CEA

Software frameworks

Deep learning framework

HW exportsTrusted AI

Benchmarking

Use Cases

Security DefenseManufacturing

TransportMarketing

Automation

Hardware architectures

PNeuroDNeuro

HLS

RRAM synapses3D stackingMixed A/D designFDSOI 28nm

Deep learning research

Spike coding

Bio-inspired sensors

Unsupervised learning

CEA TECHNeuro computing

platform

Advanced

implementations

CEA TECH

EXPERTISE

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N2D2: NEURAL NETWORK DESIGN & DEPLOYMENT

• A platform for the design and exploration of Deep Neural Networks applications

• N2D2 is available at HTTPS://GITHUB.COM/CEA-LIST/N2D2/

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3DSPIKES

3D HD

LETI’S AI ROADMAP

Em

be

dd

ed

AI

AI

for

IoT

Ed

ge

AI

Clo

ud

AI

o Ultra low power

o Sensors with AI

o Focused application

2020

10

0W

10

W1

W1

mW

–1

00

mW

2025 2030

Spirit

Multicluster

SNN

Spiking Smart

sensor

DIGITAL

3D interposerDIGITAL

Learning at

the Edge

High-Perf

Inference

1000Tops/W100Tops/W10Tops/W

OxRAM

Fine-grain

In-Memory

Computing

Event-based

AI

Sensing-to-

decision design

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• The combination of FDSOI, 3D and new embedded memories open up new ways for implementation of AI solutions in energy efficient circuits,

• Two examples of dedicated chips in 28FDSOI (ST technology).

FDSOI AND AI TODAY : A REALITY DRIVEN BY INDUSTRY & ACADEMIA

• Neuro Accelerator, ST ISSCC 2018

• Deep Convolution NN

• 2.9TOPS/W

• Dynaps-SL (Uni. Zurich, NeuRAM3 H2020 project)

• Spiking NN

• <2pJ per synaptic event

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• Leti keeps providing the development of basics technologies to support the needs of data treatment for the mid and long term.

• Specific solutions are studied to provide benefits to specific applications as variation on common core elements

• CEA is a major player to support processes and technologies for Industry and ourpartners

CONCLUSIONS (1/2)

Photonic

New Memory

Technologies

Parallel 3D

Cu

SiO2

Cu

SiO2

Neuromorphic

Sequential 3D

Advanced CMOS

500 n

m500 n

m

PtNiO

AlCu

AlCu

Advanced

Architectures

Leti’s 360Fusion

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CONCLUSIONS (2/2)

12nm12nm

10nm10nm

Sub-10nmSub-10nm

Technology solutionsexist for 12nm and evensub-10nm nodes: no show-stopper identified at thedevice level

Letialready demonstrated FEOLtechnology boosters for sub-10nm FDSOI nodes

Emerging Applications (AI, 5G,W)can benefit from this FDSOI technologies,combined with 3D, RRAM and new computingparadigms

Leti, technology research institute

Commissariat à l’énergie atomique et aux énergies alternativesMinatec Campus | 17 rue des Martyrs | 38054 Grenoble Cedex | Francewww.leti-cea.com

Thanks for your attention

Questions are welcome

Leti, technology research institute

Commissariat à l’énergie atomique et aux énergies alternativesMinatec Campus | 17 rue des Martyrs | 38054 Grenoble Cedex | Francewww.leti-cea.com

Thanks for your attention

Questions are welcome

Leti, technology research institute

Commissariat à l’énergie atomique et aux énergies alternativesMinatec Campus | 17 rue des Martyrs | 38054 Grenoble Cedex | Francewww.leti-cea.com

Thanks for your attention

Questions are welcome