appendix page1 cisc design by ralph m. weber jr

Appendix

CISC Design

By Ralph M. Weber Jr.

Appendix

CISC Design Control Signals

Appendix

Table 3: Control SignalsControl Signal Table

Co

ntr

ol

Sig

na

ls

De

sc

rip

tio

n

Ac

tio

n

PC

MA

R

MD

R

MM

(WR

)

IR XR

AC

C

AL

U

HA

LT

We

igh

t

C0 MAR<--PC Load MAR with PC 1C1 WRITE M <--MDR(MAR) Write MDR into M at MAR 1 1C2 MDR <--READ M(MAR) Read M from MAR to MDR 1 1C3 PC<--PC+1 Increment PC 1 1C4 IR<-- MDR(OP) Load IR with Opcode 1 1C5 MAR<--MDR(ADR)+(XR*IR15) Load MAR with index address 1 1C6 MAR<--MDR(ADR) Load MAR with indirect address 1 1C7 ACC<--ACC+MDR(ADR) Load ACC and perform add 1 1 2C8 ACC<--ACC-MDR(ADR) Load ACC and perform sub 1 1 2C9 ACC<--MDR(ADR) Load ACC with address 1 1C10 MDR(ADR)<--ACC Load MDR with ACC 1 1C11 PC<--MDR(ADR) Load PC with address 1 1C12 XR<--MDR(ADR) Load XR with address 1 1C13 XR<--0 Reset XR 1 1C14 ACC<--0 Reset ACC 1 1C15 SHL ACC Left Shift ACC 1 1C16 SHR ACC Right Shift ACC 1 1C17 ACC<--!ACC Comp ACC 1 1C18 ACC<-- -ACC Negitive ACC 1 1C19 ACC<--ACC+1 Load ACC and add 1 1 1 2C20 ACC<--ACC-1 Load ACC and sub 1 1 1 2C21 XR<--XR+1 Load XR and add 1 1 1 2C22 XR<--XR-1 Load XR and sub 1 1 1 2C23 HALT Halt execution 1 1

Note: R - Reset, L- Load, S- SelectNote: all blanks are equal to zero.

Appendix

CISC Design Flowchart

Appendix

Figure 5: Flowchart 1

M(AR) <- PC

CPU Active

Begin

A

End

No

Yes

PC <- PC +1IR <- MDR(OP)

READ M

MDR(ADR) <- MDR(ADR) + (XR*X)

Decode IR

IR7, I = 0 No

YesREAD M

MDR(ADR) <- MDR(ADR)

B

Appendix

Figure 6: Flowchart 1a

A

M(AR) <- MDR(ADR)

READ M

ACC <- ACC + MDR(ADR)

M(AR) <- MDR(ADR)

READ M

ACC <- ACC - MDR(ADR)

ADD SUB

B

M(AR) <- MDR(ADR)

READ M

ACC <- MDR(ADR)

M(AR) <- MDR(ADR)

MDR(ADR) <- ACC

WRITE M

LOAD STORE

PC <- MDR(ADR)

PC <- MDR(ADR)

YES

JUMP JZ

A

JPOS JXZ

B

M(AR) <- MDR(ADR)

READ M

XR <- MDR(ADR)

M(AR) <- MDR(ADR)

READ M

ACC <- MDR

LDX LD

ACC <- 0 XR <- 0

CLR CLX

ACC =0NO

PC <- MDR(ADR)

YES

ACC>=0NO

PC <- MDR(ADR)

YES

XR=0NO

Appendix

Figure 7: Flowchart 1b

A

SHIFT LEFT ACC SHIFT RIGHT ACC

SHL SHR

B

ACC <- !ACC ACC <- -ACC

COMP NEG

ACC <- ACC + 1 ACC <- ACC - 1

INC DEC

A

XR <- XR +1 XR <- XR - 1

INX DCX

B

HALT

HALT

Appendix

CISC DesignConsole

Appendix

Figure 9: CISC Design of Console

User Console

32 switches

Load Button

48 LED

ERROR LED

32 SW

LOAD

Start Button

START

16 switches

16 SW

HALT LED

Reset Button

RESET

Appendix

Figure 10: Combinational Logic

O5

O1

O2

O3I4

I0

I1

I2

I5

Combinational Logic Unit

100 MHz

SPARE

SPARE

SPARE

SPARE

O0CLK

START

ER

C23

SPARE

RESET

I3SPARE

V

D Q

/Q

D F/F

1

HALT LED

ERROR LED

Appendix

CISC Design Main CPU

Appendix

Figure 12: Design of Main Computer

MM

PC

MDR

MAR

RD WR

ACC

CU

Main Computer Data Paths

ALU

MDR(OP)

MDR(ADR)

MDR(ADR)

ACO

ACO

IR

XR

MDR

16

16

3216

32

3232

32

32

32

16

16

16

16

16

SW

SW

32

XR=0

ACC=0 ACC>=0

ER

16

Appendix

Figure 13: Design of Main Computer

MM

PC

MDR

MAR

RD WR

IR

ACC

CU

Main Computer Control Signals

ALU

C0

Cn

...

C0, C5, C6

C3, C11

C1 C2

C2,C10

C4

C7, C8, C9,C14, C15, C16, C17, C18, C19, C20

XR

C12, C13, C21, C22

C7, C8, C18, C19, C20

Appendix

Figure 14: CISC Design of MDR

…

MDR

ID(15) X

O(1) O(2) O(3) O(4) O(5) O(6) O(7)O(0)

D(4)D(0) D(1) D(2) D(3) D(5) D(7) D(8) D(14)D(9) D(10)D(11)D(12)D(13) D(15)D(6)

X I

0 31…

O(0) O(7)D(0) … …

Appendix

Figure 15: MDR Detail Design

MDRi

MDR

8x1 Multiplexer

Y

I2 I4I0 I6I3 I5I1 I7

S2

S0

S1

0 0MMi 00 0ACCi 0

JK F/F

V

J K

Q /Q

V

X1488X3

Priority EncoderI6

O2

O0

GS

EO

O1

O2

O0

V

EO

O1

I7

I5

I3

I1

EI

I6

I4

I2

I0

I5

I3

I1

1

I4

I2

I0

I7

0

0

0

0

0

0

C10

C0

Appendix

O(6) O(5) O(4) O(3) O(2) O(1) O(0)O(7)

Figure 16: CISC Design of Opcode(s) Instruction Opcode(s)

ADD 0 1

SUB 0 2

LOAD 0 3

STORE 0 4

JUMP 0 5

JZ 0 6

JPOS 0 7

JXZ 0 8

LDX 0 9

LD 0 A

CLR 0 B

CLX 0 C

SHL 0 D

SHR 0 E

COMP 0 F

NEG 1 0

INC 1 1

DEC 1 2

INX 1 3

DCX 1 4

HALT 1 5

Appendix

Figure 17: CISC Design MAR & PC

MAR

A(n)

A(4)A(0) A(1) A(2) A(3) A(5) A(7) A(8) A(14)A(9) A(10)A(11)A(12)A(13) A(15)A(6)

0 15…

A(0) …

P(n)

P(4)P(0) P(1) P(2) P(3) P(5) P(7) P(8) P(14)P(9) P(10)P(11)P(12)P(13) P(15)P(6)

0 15…

P(0) …

PC

Appendix

Figure 18: MAR Detail Design

MARi

MAR

8x1 Multiplexer

Y


S2

S0

S1

0PCi 00 0Di 0

JK F/F

V

J K

Q /Q

V

X1488X3

Priority EncoderI6

O2

O0

GS

EO

O1

O2

O0

V

EO

O1

I7

I5

I3

I1

EI

I6

I4

I2

I0

I5

I3

I1

1

I4

I2

I0

I7

0

0

0

0

0

C6

C5

C0

DRi

X

XRi

Appendix

Figure 19: PC Detail Design

X1488X1

Priority Encoder

I7

I5

I3

I1

I6

I4

I2

I0

O2

O0

GS

EO

O1

V

I7

I5

I3

I1

EI

I6

I4

I2

I0 PC(A15-A0)

MDR(D15-D0)

PC

RESET

LOAD

CNTEN

D0 – D15 Q0 - Q15

16 Bit Counter

V

1

CLK

PC

MDR(ADR)

C11

START

C3

Appendix

Figure 20: CISC Design of XR & ACC

XR

R(n)

0 15

R(0) …

H(n)

0 31

H(0) …

ACC

Appendix

Figure 21: XR (i=0) Detail Design

XRi

XR(i=0)

8x1 Multiplexer

Y


S2

S0

S1

Si 0DRi 0Di 00 0

JK F/F

V

J K

Q /Q

V

X1488X3

Priority EncoderI6

O2

O0

GS

EO

O1

O2

O0

V

EO

O1

I7

I5

I3

I1

EI

I6

I4

I2

I0

I5

I3

I1

1

I4

I2

I0

I7

0

0

0

0

C22

C21

C13

C12

XRi

XR(1-31)XR=0

XR=0

Appendix


XRi

XR(i=30)

8x1 Multiplexer

Y


S2

S0

S1

Si 0DRi 0Di 00 0

JK F/F

V

J K

Q /Q

V

X1488X3

Priority EncoderI6

O2

O0

GS

EO

O1

O2

O0

V

EO

O1

I7

I5

I3

I1

EI

I6

I4

I2

I0

I5

I3

I1

1

I4

I2

I0

I7

0

0

0

0

C22

C21

C13

C12

Appendix


XRi

XR(i=31)

8x1 Multiplexer

Y


S2

S0

S1

Si 0DRi 0Di 00 0

JK F/F

V

J K

Q /Q

V

X1488X3

Priority EncoderI6

O2

O0

GS

EO

O1

O2

O0

V

EO

O1

I7

I5

I3

I1

EI

I6

I4

I2

I0

I5

I3

I1

1

I4

I2

I0

I7

0

0

0

0

C22

C21

C13

C12

Appendix

Figure 24: ACC (i=0) Detail Design

ACCi

ACC (i=0)

8x1 Multiplexer

Y


S2

S0

S1

MDRi 0Si !ACCi0 ACCi+1Di

JK F/F

V

J K

Q /Q

V

X1488X3

Priority EncoderI6

O2

O0

GS

EO

O1

O2

O0

V

EO

O1

I7

I5

I3

I1

EI

I6

I4

I2

I0

I5

I3

I1

1

I4

I2

I0

I7

C18

C17

C16

C15

C14

C9

C8

C20

C7

C19

ACCneg

ACCi

ACC(1-31)ACC=0

!ACCi

1 u2

x3

u1

x2

x1

ADD

Ci+1Ci = 0

ACC=0

Appendix


ACCi

ACC (i=30)

8x1 Multiplexer

Y


S2

S0

S1

MDRi ACCi-1Si !ACCi0 ACCi+1Di

JK F/F

V

J K

Q /Q

V

X1488X3

Priority EncoderI6

O2

O0

GS

EO

O1

O2

O0

V

EO

O1

I7

I5

I3

I1

EI

I6

I4

I2

I0

I5

I3

I1

1

I4

I2

I0

I7

C18

C17

C16

C15

C14

C9

C8

C20

C7

C19

ACCneg

!ACCi

0u2

x3

u1

x2

x1

ADD

Ci

Ci+1

Appendix


ACCi

ACC (i=31)

8x1 Multiplexer

Y


S2

S0

S1

MDRi ACCi-1Si !ACCi0 0Di

JK F/F

V

J K

Q /Q

V

X1488X3

Priority EncoderI6

O2

O0

GS

EO

O1

O2

O0

V

EO

O1

I7

I5

I3

I1

EI

I6

I4

I2

I0

I5

I3

I1

1

I4

I2

I0

I7

C18

C17

C16

C15

C14

C9

C8

C20

C7

C19

ACCneg

ACC(i) ACC>=0

!ACCi

0 x3

u1x2

x1

ADD

Ci

ACC>=0

Appendix

Figure 27: CISC Design of IR

IR

I(n)

I(4)I(0) I(1) I(2) I(3) I(5) I(7) I(8) I(14)I(9) I(10) I(11) I(12) I(13) I(15)I(6)

0 15…

I(0) …

Appendix

Figure 28: IR Detail Design

IRi

IR

8x1 Multiplexer

Y


S2

S0

S1

0 0Dri 00 00 0

JK F/F

V

J K

Q /Q

V

X1488X3

Priority EncoderI6

O2

O0

GS

EO

O1

O2

O0

V

EO

O1

I7

I5

I3

I1

EI

I6

I4

I2

I0

I5

I3

I1

1

I4

I2

I0

I7

0

0

0

0

0

0

0

C4

Appendix

Figure 29: ALU Detail Design

ALU

ALU

2x1 Multiplexer

I1

Y

S0

I0

2x1 Multiplexer

I1

Y

S0

I0

ADD/SUB

I1

Y

S0

I0

/32

/32

/16

/32

/1

ACC

C22

C21

0

0

C20

C19

C8

C7

X1488X3

Priority Encoder

O2

O0

GS

EO

O1

M1

A/D

V

M2

I7

I5

I3

I1

EI

I6

I4

I2

I0

1

XR

DR

1

A/D

M1 M2 ER

RESET

RESET

Appendix

Table 30: ALU Tables

ALU Table for SelectInputs Outputs Note

ALU ALU S0 ALU_O00 0 ADD1 1 SUB

ALU Table for Operation LoadInputs Outputs Note

ALU ALU M1 ALU_O00 0 ACC1 1 XR

ALU Table for Operation LoadInputs Outputs Note

ALU ALU M0 ALU_O00 0 MDR(ADR)1 1 1

ALU Table for Operation LoadNote

ALU ALU M0 ALU M1 ALU S00 0 0 0 ACC, MDR(ADR)1 0 0 1 ACC, MDR(ADR)2 0 1 0 ACC, 13 0 1 1 ACC,14 1 0 0 SPARE5 1 0 1 SPARE6 1 1 0 XR,17 1 1 1 XR,1

Appendix

CISC Design Input Equations

See text in body of report

Appendix

CISC Design Micro Control Unit

Appendix

Figure 33: Design of Micro Control Unit

EEPROMmPC

mMDR

RD

Micro Control Unit (Data Flow)

IR

mMDR

ControlSignalfor CPU

Cn

16

1616

32

9

Appendix

Figure 34: Design of Micro Control Unit

EEPROMmPC

mMDR

RD

Micro Control Unit (Control signals)

CLK

CLK

CLK

START

Appendix

Figure 35: CISC Design of EEPROM

Micro Instruction( Fetch

& Execute)

EEPROM

FETCH

LOAD

…

HALT

Indirection TableGO to HALT

GO to LOAD

GO to …GO to …

Appendix

Figure 36: CISC Design mPC

p(n)

0 8…

p(0) …

mPC

Appendix

Figure 37: mPC Detail Design

X1488X1

Priority Encoder

I7

I5

I3

I1

I6

I4

I2

I0

O2

O0

GS

EO

O1

O2

V

I7

I5

I3

I1

EI

I6

I4

I2

I0

/9

mPC(p8-p0)

mMDR(A8-A0)

IR(O4-O0) + 000011111

4X1 Multiplexer

I1 I2

Y

S0

S1

I0 I4

0

0 0

mPC

Set Q6

SB

RESET

LOAD

CNTEN

D0 – D8 Q0 – Q8

9 Bit Counter

V

1

CLK

mPC

IR

mMDR(adr)

I= 0

mMDR(op5)

mMDR(op4)

mMDR(op3)

XR=0

mMDR(op2)

ACC>=0

mMDR(op1)

ACC=0

mMDR(op0)

mPC+1

START

mMDR(I/E)

Appendix

Figure 38: CISC Design mMDR

m(n)

0 31…

m(0) …

mMDR

Appendix

Figure 39: mMDR Detail Design

mMDR

mMDR

CLK

1

MM

32 bit Register

> CLK

EN

D0 – D31 Q0 -Q31

Appendix

Figure 40: CISC Design of Control Unit mMDR (External)

…

Control Unit

C(0)I/E

31 0…

C(30)

Appendix

Table 41: External InstructionsSee next page

Appendix

Figure 42: CISC Design of Control Unit mMDR (Internal)

…

Control Unit

o(7) a(0)I/E

31 0…

o(0) a(8)… Not used

Appendix

Table 43: Internal InstructionsSee next page

Appendix

CISC Design User Program

See next page

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