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    Indian Institute of Science

    Bangalore

    DesignComputer

    &

    T

    e

    s

    t

    Laboratory

    [email protected]

    Advance Computer Architecture 1

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    rocessor rc ec ure

    Processor Architecture CISC

    RISC

    Advance Computer Architecture 2DesignCo

    mputer

    &

    Tes

    Laboratory

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    Processor Architecture

    From

    memoryPI

    Control Signals

    Datapath

    Controlle

    Status Signals

    PO To memory

    Advance Computer Architecture 3DesignCo

    mputer

    &

    Tes

    Laboratory

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    ns ruc on e

    Should be complete

    ne s ou e a e o cons ruc a mac ne eve program oevaluate any function

    Should be efficient

    Frequently required functions can be completed quickly usingrelatively few instructions

    Should be regular Should contain expected opcodes and addressing modes

    Advance Computer Architecture 4

    Compatible with existing machinesDesignCo

    mputer

    &

    Tes

    Laboratory

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    ns ruc on e

    -

    Instruction Format

    Addressing

    Register Specification

    Effective Address

    Advance Computer Architecture 5

    DesignComputer

    &

    Tes

    Laboratory

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    Micro-coded Implementation

    Clock-Phase Generator Bus Controller

    Control Store State Sequencerns ruc onDecoder

    Control Word Decoder

    Controller

    ProgramCounter

    R0 R1 Rn Shifter ALU

    Advance Computer Architecture 6DesignCo

    mputer

    &

    Tes

    Laboratory

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    PLA Implementation

    Clock-Phase Generator Bus Controller

    PLAns ruc onDecoder

    Control Word Decoder

    Controller

    ProgramCounter

    R0 R1 Rn Shifter ALU

    Advance Computer Architecture 7DesignCo

    mputer

    &

    Tes

    Laboratory

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    Random Logic

    Implementation

    Clock-Phase Generator Bus Controller

    Random Logic

    Controller

    ProgramCounter

    R0 R1 Rn Shifter ALU

    Advance Computer Architecture 8DesignCo

    mputer

    &

    Tes

    Laboratory

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    Micro-coded

    Implementation

    Clock-Phase Generator Bus Controller

    Control Instruction Instruction

    Store

    InstructionEncoded Control Word Fields

    Control Word Decoderre e c

    Register

    Decoded Datapath Control

    PC R0 R1 Rn Shifter ALUDataReg.

    AddressOut Reg.

    InternalABus

    Internal B Bus

    Advance Computer Architecture 9DesignCo

    mputer

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    Tes

    Laboratory

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    ns ruc on

    5A R1 B2 D2

    ,

    The second operand is added in the first

    0 8 12 16 31

    The sum is placed in the first operand location

    The operand and the sum are treated as 16-bit signed binary integers

    he first operand is in the register specified by the R1 field

    The second operand is in the memory address is calculated by adding

    Advance Computer Architecture 10

    register specified by the B2 field

    DesignComputer

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    Tes

    Laboratory

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    xecu on eps

    Steps for ADD instruction Execution

    1. Fetch the first half word

    2. Find ADD control word sequence

    3. Fetch the remainin instruction word

    4. Calculate the operand address

    .6. Add

    Advance Computer Architecture 11

    7. Store the resultDesign

    Computer

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    Tes

    Laboratory

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    xecu on eps

    . e c e rema n ng ns ruc on wor

    2. Calculate the operand address

    . e c e operan

    4. Add

    .

    6. Update the program counter

    .

    8. Find the address of the next instructions control wordsequence

    Advance Computer Architecture 12

    9. Branch to the next instructions control wordDesign

    Computer

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    Tes

    Laboratory

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    xecu on eps

    .

    One state to second half of the ADD instruction

    2. Calculate the operand address

    One state to add D2 displacement and the content of the B2 register

    3. Fetch the operand One state to fetch the data half word (put the address on the pads and wait

    for the operand half-word)

    4. Add

    One state to add the operands

    5. Store the result

    Advance Computer Architecture 13

    One state to store the result in Register R1

    DesignComputer

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    Tes

    Laboratory

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    xecu on eps

    . p a e e program coun er

    One state to increament PC

    One state to save the incremented value

    2. Fetch the first half word for the next instruction

    One state to put the PC value on the pads and wait for the first half of the

    3. Find the address of the next instructions control wordsequence

    One state to put the next instruction into the instruction decoder

    4. Branch to the next instructions control word

    Advance Computer Architecture 14

    DesignComputer

    &

    Tes

    Laboratory

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    Processor - Block Diagram

    -Generator

    Next State

    Reset Power- n Logic Interrupt LogicBus Controller

    Store

    ControlDecoder

    Branch Control

    unit

    Control Word Decoder

    InstructionPrefetchRegister

    Encoded Control Word Fields

    PC R0 R1 Rn Shifter ALUDataRe .

    AddressOut Re .

    InternalABus

    eco e atapat ontro

    Advance Computer Architecture 15

    Datapath

    DesignComputer

    &

    Tes

    Laboratory

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    Advance Computer Architecture 16Design

    Computer

    &

    Tes

    Laboratory