cisc design

7/30/2019 CISC Design

1/16

Indian Institute of Science

Bangalore

DesignComputer

&

T

e

s

t

Laboratory

[email protected]

Advance Computer Architecture 1


2/16

rocessor rc ec ure

Processor Architecture CISC

RISC

Advance Computer Architecture 2DesignCo

mputer

&

Tes

Laboratory


3/16

Processor Architecture

From

memoryPI

Control Signals

Datapath

Controlle

Status Signals

PO To memory


mputer

&

Tes

Laboratory


4/16

ns ruc on e

Should be complete

ne s ou e a e o cons ruc a mac ne eve program oevaluate any function

Should be efficient

Frequently required functions can be completed quickly usingrelatively few instructions

Should be regular Should contain expected opcodes and addressing modes


Compatible with existing machinesDesignCo

mputer

&

Tes

Laboratory


5/16

ns ruc on e

-

Instruction Format

Addressing

Register Specification

Effective Address


DesignComputer

&

Tes

Laboratory


6/16

Micro-coded Implementation

Clock-Phase Generator Bus Controller

Control Store State Sequencerns ruc onDecoder

Control Word Decoder

Controller

ProgramCounter

R0 R1 Rn Shifter ALU


mputer

&

Tes

Laboratory


7/16

PLA Implementation


PLAns ruc onDecoder


Controller

ProgramCounter



mputer

&

Tes

Laboratory


8/16

Random Logic

Implementation


Random Logic

Controller

ProgramCounter



mputer

&

Tes

Laboratory


9/16

Micro-coded

Implementation


Control Instruction Instruction

Store

InstructionEncoded Control Word Fields

Control Word Decoderre e c

Register

Decoded Datapath Control

PC R0 R1 Rn Shifter ALUDataReg.

AddressOut Reg.

InternalABus

Internal B Bus


mputer

&

Tes

Laboratory


10/16

ns ruc on

5A R1 B2 D2

,

The second operand is added in the first

0 8 12 16 31

The sum is placed in the first operand location

The operand and the sum are treated as 16-bit signed binary integers

he first operand is in the register specified by the R1 field

The second operand is in the memory address is calculated by adding


register specified by the B2 field

DesignComputer

&

Tes

Laboratory


11/16

xecu on eps

Steps for ADD instruction Execution

1. Fetch the first half word

2. Find ADD control word sequence

3. Fetch the remainin instruction word

4. Calculate the operand address

.6. Add


7. Store the resultDesign

Computer

&

Tes

Laboratory


12/16

xecu on eps

. e c e rema n ng ns ruc on wor


. e c e operan

4. Add

.

6. Update the program counter

.

8. Find the address of the next instructions control wordsequence


9. Branch to the next instructions control wordDesign

Computer

&

Tes

Laboratory


13/16

xecu on eps

.

One state to second half of the ADD instruction


One state to add D2 displacement and the content of the B2 register

3. Fetch the operand One state to fetch the data half word (put the address on the pads and wait

for the operand half-word)

4. Add

One state to add the operands

5. Store the result


One state to store the result in Register R1

DesignComputer

&

Tes

Laboratory


14/16

xecu on eps

. p a e e program coun er

One state to increament PC

One state to save the incremented value

2. Fetch the first half word for the next instruction

One state to put the PC value on the pads and wait for the first half of the

3. Find the address of the next instructions control wordsequence

One state to put the next instruction into the instruction decoder

4. Branch to the next instructions control word


DesignComputer

&

Tes

Laboratory


15/16

Processor - Block Diagram

-Generator

Next State

Reset Power- n Logic Interrupt LogicBus Controller

Store

ControlDecoder

Branch Control

unit


InstructionPrefetchRegister

Encoded Control Word Fields

PC R0 R1 Rn Shifter ALUDataRe .

AddressOut Re .

InternalABus

eco e atapat ontro


Datapath

DesignComputer

&

Tes

Laboratory


16/16

Advance Computer Architecture 16Design

Computer

&

Tes

Laboratory

cisc design

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