analog layout design

1 30 April 2011

Introduction to Analog Layout

Design

Dr. S. L. Pinjare

Nitte Meenakshi Institute of Technology

Workshop on Advanced VLSI Laboratory

Cambridge Institute of Technology, Bangalore

2 30 April 2011

Analog VLSI Design

• Implementation of analog circuits and systems using

integrated circuit technology.

• Unique Features of Analog IC Design

– Geometry

• an important part of the design

– Usually implemented as a mixed analog-digital circuit

• Typically Analog is 20% and digital 80% of the chip area

– Designed at the circuit level

– Customized design

– Analog requires 80% of the design time

– Passes for success: 2-3 for analog, 1 for digital.


3 30 April 2011

Analog Design Flow

• Electrical Design

• Physical Design

• Fabrication and Testing

• Product


4 30 April 2011

Analog Design Flow

Electrical Design

Physical

Design

Idea Concept

Define the Design

Implementation

Simulation

Redesign Comparison with the

Design Specification

Fabrication

Testing and Product

Development


5 30 April 2011

Analog Design Flow

Electrical Design

Physical

Design

Idea Concept

Define the Design

Implementation

Simulation



Physical Implementation-Layout

Physical Verification-DRC,ERC,LVS,Antenna

Parasitic Extraction and Back Annotation

Fabrication

Testing and Product

Development


6 30 April 2011

Analog Design Flow

Electrical Design

Physical

Design

Idea Concept

Define the Design

Implementation

Simulation



Fabrication Fabrication

Testing and Product

Development





7 30 April 2011

Analog Design Flow

Electrical Design

Physical

Design

Idea Concept

Define the Design

Implementation

Simulation



Fabrication Fabrication

Testing Testing and Product

Development PRODUCT





8 30 April 2011

Skills Required for Analog IC Design

• In general, analog circuits are more complex than

digital.

– Requires an ability to use multiple concepts simultaneously.

– Be able to make appropriate simplifications and assumptions.

– Need to have good knowledge of both modeling and

technology.

– Be able to use simulation correctly.

• (Usage of a simulator)x(Common sense)=Constant

• Simulators are only as good as the models and the knowledge of those

models.

– “all models are wrong, some are useful“

• Be able to learn from failure.


9 30 April 2011 Nitte Meenakshi Institute of Technology

Analog layout Issues

• Issues that are important in digital circuits are still

important in analog layout.

– Eg. Parasitic aware layout.

• Minimize series resistance

– slows down switching speed plus introduces unwanted noise.

• Minimize parasitic capacitance

– slows down switching speed

– Increases power dissipation(Capacitance switching)

• Extra load capacitance

– Need to increase bias current to maintain bandwidth and/or slew

rate.

– Can lead to instability in high gain feedback systems.

10 30 April 2011


• Noise is important in all analog circuits because it limits

dynamic range.

• In general there are two types of noise,

– Random noise and

– Environmental noise.


11 30 April 2011


• Random noise refers to noise generated by resistors and

active devices in an integrated circuit;

• MULTI-GATE FINGER LAYOUT

– reduces the gate resistance of the poly-silicon and the

neutral body region, which are both random noise

sources.

• Generous use of SUBSTRATE PLUGS

– will help to reduce the resistance of the neutral body

region, and thus will minimize the noise contributed by

this resistance.


12 30 April 2011


• Environmental noise – Crosstalk; Ground bounce etc.

– Generally appears as a common-mode signal.

• Use ‘fully-differential’ circuit design,

– Substrate noise occurs when a large amount digital circuits are present on a chip. The switching of a large number of circuits discharges large dynamic currents to the substrate, which cause the substrate voltage to ‘bounce’.

• The modulation of the substrate voltage can then couple into analog circuits via the body effect or parasitic capacitances.

• SUBSTRATE PLUGGING

– minimizes substrate noise because it provides a low impedance path to ground for the noise current.


13 30 April 2011


• Matching components

• In analog electronics it is often necessary to have

matched pairs of devices with identical electrical

properties, e.g. input transistors of a differential stage,

and current mirror

– In theory two device with the same size have the same

electrical properties.

• In reality there is always process variations

• Matching:

– Layout techniques to minimize the errors introduced by

process variations.


14 30 April 2011

Analog Design components

• Active devices

– Transistors

• N-mos and P-mos

• Passives

– Resistors

– Capacitors

– Inductors

• Implemented using existing layers and masks

– Possibly adding a few extra layers


15 30 April 2011

Analog Design Layout considerations

• Design rules

– Allowance Errors in patterning and etching

• Minimum width

• Minimum spacing

• Minimum enclosure

• Minimum extension

• Process variability

– Parameter variation across the chip


16 30 April 2011

Design rules

• Minimum width

– The minimum width of polygon defines the limits of a fabrication process.

– A violation of the minimum width rules potentially results in an open

circuit in the offending layer.

• An open circuit may be created during fabrication.

• A narrow path may be created during fabrication

– large currents passing through a narrow path cause the path to act

like a fuse.


17 30 April 2011

Design rules

• Minimum spacing:

– To avoid an unwanted short circuit between two polygons

during fabrication,

• S1 > Smin, where Smin is set by process.


18 30 April 2011

Design rules

• Minimum enclosure:

– Apply to polygons on different layers.

– Misalignment between polygons may result in either

unwanted open or short circuit connections.


19 30 April 2011

Design rules

• Minimum extension:

– Some geometries must extend beyond the edge of others by a

minimum value.

• Eg. Gate poly must have a minimum extension beyond the

active area to ensure proper transistor action at the edge.


20 30 April 2011

Design Rules

• Example of the design rules applying to the POLY layer

C3.4 POLY:

Gate Structures and resistors are defined by the poly layer. Minimum design rules

are used for the polylayer. i.e. this is the minimum feature size for this process.

• A ≥ 1.5 µm,(minimum polywidth /Length).

• B ≥ 1.5 µm,(minimum poly to poly distance).

• C ≥ 1.5 µm,(minimum poly-over-oxide overlap).


21 30 April 2011

Unit Matching

• Two electrically equivalent components.

• Draw them identically

– Both item and surrounding

– A and B have same shape in area and perimeter

– Identical item?

– Do they have the same surrounding?


22 30 April 2011

Unit Matching

• Two electrically equivalent components.

• Draw them identically

– Both item and surrounding

– A and B have same shape in area and perimeter

– Identical item?

– Do they have the same surrounding?

• No

– Use Dummies to have identical surroundings


23 30 April 2011

Common-centroid layout

• Process variations can locally be approximated with a

linear gradient.

(a): A1 + A2 < B1 + B2

(b): A1 + A2 = B1 + B2 (common-centroid)


24 30 April 2011

Resistors

• All materials have a resistivity

• Typical resistivities

– Metal layer : 0.1 Ohm/square

– n/p-plus contacts and polysilicon: 10-100 Ohm/square

– n-well: 1000 Ohm/square

– low doped poly silicon: 10 k Ohm/square

• more well defined than n-well, i.e. higher accuracy


25 30 April 2011

Poly-Resistors

• Poly Resistors

– Silicidated poly resistors: 1 − 10 Ohm/sq.

• ≈±30%

– Non-silicidated poly resistors: 50-1000 Ohms per unit area .

• Small parasitic capacitances to substrate.

• Superior linearity.

• High cost due to the extra mask needed to block silicide

layer.

• ≈±20%


26 30 April 2011

Diffusion Resistors

• 1k Ohm/sq

– N-well

• Large parasitic capacitance between n-well and substrate.

• Resistance is strongly terminal voltage-dependent and

highly nonlinear.

– Depletion width varies with terminal voltages.The

cross-section area varies with terminal voltages

• Large error : ≈±40%

• noisy as all disturbances/noise from substrate can be

coupled directly onto the resistors


27 30 April 2011

Resistor Layout

• Standard Resistors: Avoid 90 degree angle. 45 degree is

recommended

Recommended resistor

layout

1. Resistance at the corners cannot

be estimated accurately

2. Current flow at the corner is not

uniform


28 30 April 2011

Resistor Layout

• Dummy resistors are added to

minimizes the effect of

process variation


29 30 April 2011

Shielded Resistors

• Shielding resistors

– Connected to a constant voltage

source

• Prevent self-coupling of the

resistor R/inter-coupling

with others.

• Widely used in analog/RF

design.

• Caution

– a mutual capacitance between

the resistor and its shield exist.

Layout of shielded resistors

(S = shielding resistors)


30 30 April 2011

Layout of Large Resistors

• Use n-well resistors

– have a large sheet resistance.

• Enclosed by a substrate shielding ring, also known as guard ring,

to isolate the resistors from neighboring devices.


31 30 April 2011

Layout of Matched Resistors

• Inter-Digitized Layout

– minimizes the effect of process variation in x-direction.

• Dummy resistors are added to ensure both resistors have

the exactly same environment.


32 30 April 2011

Matched Resistors with Temperature Consideration

• Keep away from power devices


33 30 April 2011

Resistor layout guidelines-Matched resistors

• Use same material

• Identical geometry, same orientation

• Close proximity, interdigitate arrayed resistors

• Use dummy elements

• Place resistors in Low stress area

• Place resistors away from power devices

• Use electrostatic shielding


34 30 April 2011

Capacitors

• There are naturally capacitors between each layer of

metal, poly silicon or silicon

• Dielectrics between different metal layers have a

thickness of 0.5-1 micron, which gives a rather large

area for a given capacitance.

• Key Parameters

– Linearity

– Parasitic capacitance to substrate

– Series resistance - resistance of capacitor plates

– Capacitance per unit area

• Larger specific capacitance (capacitance per unit area)

gives smaller area


35 30 April 2011

Types of IC Capacitors

• Poly-diffusion capacitors

– Nonlinear bottom-plate parasitic capacitance.≈20% of inter-plate capacitance.

– .6-.8 fF/µm2(≈±5%). Matching 0.2%

• MOS capacitors

– Stable capacitance in strong inversion

– Non-negligible channel resistance lowers the quality factor (Q) of the capacitor

– 0.6 - 0.8 fF/µm2; (≈±5%). Matching 0.5%

• Poly-poly capacitors

– Not available in standard CMOS processes

– 0.3 - 0.5 fF/µm2; (≈±10%). Matching 0.5%

• Metal-poly capacitors

– Capacitance is small, area consuming.

– 0.03-0.05 fF/µm2. (≈±25%). Matching 0.5%

• Metal-metal capacitors

– Capacitance is small, area consuming

– 0.02-0.04 fF/µm2; (≈±25%). Matching 0.1%


36 30 April 2011

NON-IDEAL EFFECTS- UNDER-CUT

• Non-uniform undercut &/or edge

fringing field effects change the

value of designed capacitors.

• The area and perimeter ratio is

preserved if we use layout using

unit capacitors.

Case 1

Case 2

Ideal case: no undercut

Case 1 Case 2

Area 1:4 1:4

Perimeter 1:2 1:4

Typical case: 0.05 undercut

Case 1 Case 2

Area 1:4.46 1:4

P erimeter 1:2.1 1:4


37 30 April 2011

NON-IDEAL EFFECTS-Corner Rounding

• Etching always causes corner

rounding to some extent.

• This means that

– 90° corners will be eroded and

– 270° corners will be have

incomplete removal of material

• In order to overcome this

effect use an equal number of

90° & 270° corners


38 30 April 2011

Layout of MOS Capacitors

• Single finger structure

– Large source/substrate & drain/substrate capacitances

– Large gate series resistance

Minimize Gate Series Resistance & Channel Resistance


39 30 April 2011

Layout of MOS Capacitors

• Minimize Gate Series Resistance & Channel Resistance

• Use Multi-Finger Structure

Multi-finger structure minimizes source/substrate &

drain/substrate parasitic capacitances.


40 30 April 2011

Layout of Matched Capacitors

• Minimize the Effect of

Oxide Thickness in both

x and y-directions.

– Common Centroid

Structure.

– Dummy capacitors are

needed to ensure the same

environment for C1 and

C2.


41 30 April 2011

Layout of Matched Capacitors

• C1 and C2 are 2-poly capacitors.

• n-well is employed as a charge

collector to shield the interaction

between the bottom plate and

substrate.

• n-well is biased at multiple

points and connected to a

constant voltage source.


42 30 April 2011

Layout of MOS Transistors

• Criteria for MOS Transistor Layout

– Minimize gate series resistance.

– Minimize source/drain resistances.

– Minimize source/substrate & drain/substrate parasitic

capacitances.


43 30 April 2011


• Large gate series resistance

– 7.8±2.5Ohm/sq for typical 0.18μ

CMOS processes.

• Large distributed resistance of

source/drain

– 6.8±2.5Ohm/sq for n+ and

7.2±2.5Ohm/sq for p+ in typical

0.18μ CMOS processes.

• Large source/substrate and drain/substrate

parasitic capacitances.

• Non-uniform gate/source/drain voltages.

• Non-uniform current flow

– M1 carries the most current and Mn

carries the least current).

Most of the current will be

shrunk to this side


44 30 April 2011


• Minimize Source/Drain Resistances – Multiple contacts at source/drain

• Better contact at source/drain → high reliability & smaller contact resistance (R = Rc/N, where N=number of contacts).

– Smaller source/drain resistances (series resistance is negligible but lateral resistance still exists).

– Large source/substrate and drain/substrate parasitic capacitances.

– Large gate series resistance- Gate is too long.

• Contacts are not allowed on the gate above the channel (high temperature required to form contacts may destroy the thin gate oxide).

Current is spread


45 30 April 2011


Folding reduces gate

resistance No of fingers:

Gate resistance < 0.1 to .5(1/gm)

Results in increase of parasitic capacitance

Poly contact at both ends


46 30 April 2011


• Minimize Source/Substrate and Drain/Substrate Parasitic

Capacitances

– Shared sources/drains.

– Reduced silicon area.

Another layout


47 30 April 2011

Antenna Effect

There will be charge accumulation on Metal1 during plasma

etching (of metal1) causing damage to thin gate oxide (Large

metal area)

Avoids antenna effect


48 30 April 2011

Layout of a Cascode circuit

a.

b. c.


49 30 April 2011

Layout of Wide transistors

• Wide transistors need to be split

• Parallel connection of n elements (n = 4 for this example)

• Contact space is shared among transistors

• Parasitic capacitances are reduced (important for high speed )

Note that parasitic capacitors are

lesser at the drain


50 30 April 2011

Effect of wiring resistance


51 30 April 2011

Layout of Matched Transistors

• Matched transistors are used extensively in both analog

and digital CMOS circuits.


52 30 April 2011

Photo-lithographic invariance (PLI)

• Lithography effects different in different direction

• C and D are better


53 30 April 2011


• Effect of shadowing – S/D implant often has an angle.

– Drain/Source can be mirrored


54 30 April 2011


• Effect of shadowing :

– Gate aligned

– Parallel gate:

• Two drains have

different surroundings

• Two sources have

different surroundings

Orientation is important in analog

circuits for matching purposes


55 30 April 2011


• Add dummy

transistors to

improve

symmetry

• Presence of Metal line over

M2 destroys symmetry • Replicate Metal line over

M1 improves symmetry


56 30 April 2011


• Gradient along x-axis destroys symmetry


57 30 April 2011

Matching - Summary

• To achieve both common-centroid and PLI matched

transistors has to be split into 4 fingers.


58 30 April 2011

Matched Transistors

• Matched transistors require elaborated layout techniques

• Use inter-digitized layout style

• Averages the process variations among transistors

• Common terminal is like a serpentine

• Uneven total drain area between M1 and M2.

– This is undesirable for ac conditions: capacitors and other parameters may not be equal

• A more robust approach is needed (Use dummies if needed)


59 30 April 2011

Common Centroid Layouts


60 30 April 2011

Common Centroid Layouts

• Split into parallel connections of even parts

• Half of them will have the drain at the right side and half at the left

• Be careful how you route the common terminal


61 30 April 2011

Differential Amplifier


62 30 April 2011


63 30 April 2011

Summary

• Use large area to reduce random error

• Common Centroid layout to reduce linear gradient

errors

• Use unit element arrays

• Interdigitize for matching

• Use of symmetry (photolithographic invariance)

• Dummy device for similar vicinity

• Guard rings for isolation


64 30 April 2011

References

• A. Hastings, The Art of Analog Layout, Prentice-

Hall,2002.

• B. Razavi, Design of Analog CMOS Integrated Circuits,

McGraw-Hill, 2001.


65 30 April 2011

Thank You


66 30 April 2011

Simulation

• To fully describe the function of a MOS transistor the

fundamental electro-magnetic equations are set up in 2D/3D.

• Coupled non-linear partial deferential equations take long time to

solve.

• Compact models are desired.

– Simple mathematical relations that describes the relation between currents

and voltages.

• There are 3 main types of models (for electrical devices and in

general).

– Physical model parameters have physical meaning

– Empirical parameters have no physical meaning (fitting parameters)

– Table based measured data + interpolation functions


67 30 April 2011

Simulation

• Devices are characterized for a parameter window

where the model becomes valid.

• Validity outside defined parameter window:

– Physical: Good validity.

– Empirical: Have difficulties outside the window and can in

some cases give preposterous results.

– Table based Same or worse than empirical models.

• Physical models with empirical fitting parameters are

common (semi-empirical).


68 30 April 2011

SPICE

• Simulation Program with Integrated Circuit Emphasis

• There are two sides of SPICE:

– The simulator

– The models

• The simulator

– A circuit is described with nodes and elements between nodes.

– For linear circuits the matrix is solved using nodal admittance

analysis.

– Non-linear circuits are solved using iterative methods.

– The basic simulation types are OP, DC, AC and transient


69 30 April 2011

SPICE simulations

• OP Operating Point analysis.

– Solves the currents and voltages in a circuit at one bias condition.

• DC

– Same as OP but does it for one or more swept parameters, e.g. IDS vs.

VDS

• AC

– Linearizes all elements at the bias point. Then a sinusodial signal is

applied on one or more inputs and the frequency is swept.

• Note: since the circuit is linearized no saturation effects will occur

using AC.

• Transient

– One or more time varying signals (e.g. sinusodial, pulses, square waves)

are applied and the time is swept. This simulation does not linearize the

circuit so here saturation effects are present.


70 30 April 2011

Latchup

Latchup may begin when Vout drops below GND due to a noise spike or an

improper circuit hookup (Vout is the base of the lateral NPN Q2). If sufficient

current flows through Rsub to turn on Q2 (I Rsub > 0.7 V ), this will draw

current through Rwell. If the voltage drop across Rwell is high enough, Q1

will also turn on, and a self-sustaining low resistance path between the power

rails is formed. If the gains are such that b1 x b2 > 1, latchup may occur. Once

latchup has begun, the only way to stop it is to reduce the current below a

critical level, usually by removing power from the circuit.


71 30 April 2011

SPICE netlist

*** Top Level Netlist ***

M1 5 5 2 2 CMOSNB L=5u W=15u

M2 6 5 2 2 CMOSNB L=5u W=15u

R1 4 5 380k

VDD 3 0 DC 2.5v AC 0 0

Vout 1 0 DC 0

VSS 2 0 DC -2.5v AC 0 0

*** Control Statements ***

.DC VOUT -2.4 2.5 .1

.PRINT DC ALL

**** Spice models and macro models ****

.MODEL CMOSNB NMOS LEVEL=4 VFB=-9.73E-01

+LVFB=3.67E-01, WVFB=-4.72E-02, PHI=7.46E-01

+LPHI=-1.92E-24, WPHI=8.064E-24


72 30 April 2011

SPICE models

• The first MOS-models came in the begining of the 70's.

– The first model was called Level 1 MOS model.

– The model had 10 parameters (4 process and 6 electrical)

– (TPG), TOX, NSUB and XJ from process

– UO, VTO and LAMBDA , CGSO, CGDO, CGBO from

electrical

– With a few minor differences the model is described by the

equations

.model Name_model NMOS Level=1

+TPG=1 TOX=10-7 NSUB=1E16 XJ=1E-6

+ UO=600 VTO=1.5 LAMBDA=0.01

+CGSO=1E-16 CGDO=1E-16 CGBO=1E-17


73 30 April 2011

Level 1 MOS model


74 30 April 2011

SPICE models history

• Level 1, L ~> 5 micron, 1970

• Level 2, L ~> 2 micron, 1980

• Level 3, L ~> 1micron, 1981

– Many empirical parameters, numerically better,

– better short channel description.

– Difficulties in finding parameter sets that cover a large

window of lengths.


75 30 April 2011


• 2nd generation

– BSIM1, L ~> 0.8 micron, 1987

– Berkeley Short Channel IGFET Model 1

– New knowledge about short channel effects. Many fitting

parameters for improved scaling

– BSIM2, L ~> 0.35 micron, 1990

– Improved model continuity, specifically output conductance

and sub-threshold current. Scaling still a problem. Binning

introduced.


76 30 April 2011


• 3rd generation

– BSIM3, L ~> 0.1 micron, 1994

– Total re-write. The idea was to have a simple model with few physical parameters.

– Result: Many versions. Many empirical parameters.

– Difficult to extract parameters.

• Philips MOS Model 9 and 11

– Industry approach, With few empirical parameters.

• EKV (Enz-Krummenacher-Vittoz)

– With few empirical parameters, more physical than MM9 and MM11.

• 4th Generation Model

– BSIM4

• PSP (Penn State University and Philips)

• The latest and most advanced model developed by merging the best features of the two surface potential-based models: SP and MM11.


77 30 April 2011

Sources of Power-Supply Noise

• The fast rising voltage results in

current drawn from the power supply

leading to frequency-dependent IR

(voltage) drops in the VDD and VSS

traces of the printed circuit board

(PCB) or metal interconnect. This

phenomenon is called ground bounce

on the VSS side.

• The ground bounce is related to the

parasitic inductance of the package

pins of the integrated circuit (IC),

device ground, and system ground.

• The dynamic current can transform

into noise by contributing an amount

of voltage equal to V between the

system ground and device ground


78 30 April 2011

Sources of Power-Supply Noise

• Since various components may share the VDD and VSS planes or

busses as a source of power, any large voltage fluctuations on the

PCB may violate the voltage noise rating of these components.

• Such noise, if not reduced, can produce logical errors and other

undesirable effects.

• The problem is more pronounced if the noise is coupled to the

analog portion of a mixed-signal integrated circuit as it can lead

to jitter, distortion, and reduced performance of the analog

components.

• It is important to properly separate the digital and analog powers

supplies to minimize the noise levels as much as possible in a

mixed-signal environment.
