cadence analog/ mixed-signal design methodology · the cadence® analog/mixed-signal (ams) design...

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The Cadence® Analog/Mixed-Signal (AMS) Design Methodology employs advanced Cadence Virtuoso® custom design technologies and leverages silicon-accurate design flows to help design teams create differentiated silicon faster and with less risk. It delivers verified and packaged methodologies demonstrated on a real-world mixed-signal design. The Cadence AMS Design Methodology combines the best of top-down (behavioral and mixed-level approaches) with bottom-up (transistor-level design and abstraction) design techniques to achieve predictable, high-quality results for complex mixed-signal designs.

CADENCE ANALOG/MIXED-SIGNAL DESIGN METHODOLOGY

AMS DESIGN METHODOLOGYThe Cadence AMS Design Methodology delivers an extensive design and data flow guide, from design specification through design manufacturing, across the different functions of a design team. It is based on executable design tasks and recommended use models for fast, silicon-accurate mixed-signal design that ensures first-pass silicon success. The AMS Design Methodology addresses the analog-driven mixed-signal design process front to back by executing well-defined flows that demonstrate a meet-in-the-middle approach, in which all design flows are running in parallel to minimize design iterations, maximize project resource utilization, and enhance design quality.

The AMS Design Methodology addresses the entire design process and comprises five major flows:

1. Design environment and infrastructure

2. Top-down functional verification

3. AMS IP block creation and reuse

4. AMS IP export and integration

5. Top-down physical design

Top-down functional verification

AMS IP block creation and reuse

Top-down physical design

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Figure 1: The Cadence AMS Design Methodology consists of five main flows

2www.cadence.com CADENCE ANALOG/MIXED-SIGNAL DESIGN METHODOLOGY

The five flows are further divided into modules of logically related design tasks, which are illustrated and documented with in-context scenarios. The different scenarios are demonstrated on a silicon-implemented and verified real-life design, namely an Ethernet physical layer macro (PHY) and a sigma-delta fractional-N PLL frequency synthesizer macro for WLAN applications. The Ethernet PHY contains 20k analog devices and 30k digital gates including typical analog, digital, and mixed-signal blocks such as flash ADC, VGA, equalizer, and clock recovery circuit. The fractional-N PLL is a 2.4GHz synthesizer that contains 20k devices and includes a 5GHz LC VCO, a high-speed divider, on-chip regulators, and a calibration mechanism for loop filtering and VCO.

Both Ethernet PHY and frac-N PLL are implemented on a 90nm generic process design kit (GPDK), which has virtually all the aspects of an actual design kit. The design blocks have all the necessary views for complete design, including symbols, schematics, constraints, behavioral models, abstracts, layout, and extracted views, as well as configurations, testbenches, and simulation states. A design team can use the reference design as a basis to enter a new design domain, understand a wide range of new Virtuoso technologies, acquire new methodologies, and map selected elements onto their own design environment.

Top-Down Functional Design

Top-Down Physical Design

Design DataInput

Design DataOutput

DesignSpecs

1A

1B

TargetCDK

(90nm)

1CSystem-Level

Models and Sims

2AMS Block

Validation Strategy

3AMS Block Design

Partitioning

4Sub-Blocks

Specifications

5A

5B

5C

8AAnalog Block

Circuit Design andOptimization

7

AMS Block EarlyFloorplanning

15

AMS Block Assembly

11AMS Block Refinement

Floorplanning

8BDigital Design

Synthesis

8CBlock IP

Qualification

14Block Physical Integration Preparation

12A

Analog PhysicalDesign

12BDigital Block

Physical Design

12CBlock IP Layout

Integration

12DAnalog Block

Layout Migration5E

Analog BlockBehavioral Design

Analog BlockCircuit Design

Analog BlockCircuit Migration

Block IP

6AMS Block FunctionalConcept

Validation

9AMS Block Functional

Performance Validation


Post-Layout Validation


Signoff Validation

17AMS BlockPreparation

for SoCIntegration

1DThird-Party

IP

1ELegacy

IP

Block PhysicalEstimation

10A

Block IP PhysicalImport

10B

5DDigital Hierarchical

RTL Design

Bottom-up Functional and Physical Design

Figure 2: The combination of top-down (behavioral/mixed-level) and bottom-up (transistor-level design/abstraction) techniques ensures high-quality results

ModulatorControl

Multi-ModulusDivider

1.2V Regulator (HF) RCCalibration

Control

VCOCalibration

Control1.2V Regulator (LF)

LoopFilter

PFD &CP

LPF VCO

∆∑Modulator

ATB

dvdd/dgnd

dvdd/dgnd dvdd/dgnd

dvdd/dgnd

1.2V (LF)

1.2V (LF) 1.2V (HF) 1.2V (HF)1.2V (HF)

I & QDivideby 2

1.2V (HF)

10BASE-TReceiver

10BASE-TXReceiver

10BASE-TDriver

100BASE-TXDriver

4B/5BEncoder

MLT-3DedoderScrambler

Manchester EncoderDigital Waveshaping

Auto-negotiation

CollisionCarrier Sense

10BASE-T PLL

100BASE-TX PLL

MLT-3Decoder

Descrambler

4B/5BDecoder

Digital

MII

Analog

ETHERNET PHY Transceiver Macro

60k Gate

Rx

Tx

Clk

30k Device

Polarity CorrectionSquelch Link Detect

VGA ControlDigital Equalizer/SlicerTiming/BLW Control

Clock RecoveryManchester Decoder

Figure 3: The Cadence AMS Design Methodology is demonstrated on a real-world mixed-signal design


FEATURES

DESIGN ENVIRONMENT AND INFRASTRUCTURE

Any design process takes place in a certain environment including different projects, CAD tools, process design kits (PDKs), and users on different hardware platforms and operating systems. It is very important to create a consistent design environment to ensure the quality of the design and the credibility of the results.

This part of the Cadence AMS Design Methodology gives the foundation to set up a design environment using tested and proved methods and technologies, including incremental tool access, project directory structure, how to set up and control PDKs, and how to automate project and flow setup using the Design Environment and Configuration Manager.

The data exchange between the design house and the foundry is explained, detailing required datasets from the foundry and how to qualify them against the defined AMS flows. Special attention is given to the PDK—how to automatically check its content using the Data Surveyor and how to use the Incremental Technology Database (ITDB) to customize and enhance the PDK

TOP-DOWN FUNCTIONAL VERIFICATION

A comprehensive functional verification flow is presented, spanning all levels of abstraction and all design stages, from planning to post-layout device-level signoff verification. First, an introduction to the concept of design partitioning and simulation planning is given. Next, behavioral modeling guidelines and testbench strategies are presented.

A consistent testbench structure is used over all later stages of verification, starting with concept validation using behavioral model representation in AMS simulation, and system validation using Simulink/AMS co-simulation. Next is performance validation using mixed-level-transistor plus behavioral-level simulation on Virtuoso AMS Designer Simulator with SDF backannotated to the digital part.

Finally, a post-layout and signoff verification is prepared to include both analog extracted parasitics and SDF backannotation for the most accurate timing estimation using Virtuoso AMS-Ultra Simulator. An IDDQ analysis is performed using full extracted transistor-level DC simulation with the Virtuoso UltraSim Full-Chip Simulator along with top-level EM IR drop analysis.

/projects/

Designlibraries

Workinglibraries

.cdsinit .cds.lib

hdl.var.csdenvassura_tech.lib

display.drf

ProjectDocuments

ProjectA/ ProjectB/ ProjectC/

deslibs/

user1/ user2/

doc/

Figure 4: AMS design environment and infrastructure Figure 5: AMS top-down functional verification


AMS IP BLOCK CREATION AND REUSE

A thorough approach to creation of both analog and digital blocks is presented using productivity-oriented Virtuoso technology. The constraints concept and management is used to amend the schematic with the required information to automatically create its layout. Furthermore, constraints can be inferred from pre-defined circuit structures using the Circuit Prospector Assistant.

New layout techniques like design-rule–driven (DRD), module generator (Modgen), and constraint-driven editing are shown in action through a dedicated assisted layout module. A new approach to simulation is shown through the specification-oriented simulation platform (Virtuoso Analog Design Environment) with its numerous productivity enhancement features including simulation history, check points manager, parameterization flow, design specifications, and parasitic estimation flow. The high-capacity Virtuoso Analog Design Environment optimization engine is used for local and global optimization on the block level, over corners, and as a yield optimizer with Monte Carlo and sensitivity analyses.

Later, Virtuoso Layout Optimizer is used to boost the yield on the back end. A tutorial introduction to analog-driven digital implementation using the Virtuoso Digital Implementation Option shows a typical digital layout flow including planning, prototyping, placement, routing, timing optimization, clock tree synthesis, SDF generation, parasitic extraction, and parasitic closure.

AMS IP EXPORT AND INTEGRATION

The IP flow is a comprehensive guide for analog and digital IP handling, from top-level integration to extensive characterization and packaging. On the exporting side, a complete step-by-step scenario of characterizing and modeling an analog IP in Verilog®-AMS is presented, taking an N-bit flash ADC as an example. Automated testbench extraction is discussed; generic behavioral model planning, coding, and debugging is illustrated. The model includes advanced features like noise, aperture time, INL, and DNL parameters. The layout abstract is generated using the Virtuoso Abstract Generator. The timing information (.lib) file for top-level digital integration is generated using Virtuoso Spectre® MDL language and verified by importing to the Cadence Encounter® platform. Finally, packaging of all generated views for publishing is discussed and implemented using Vulcan technology.

Figure 6: AMS IP block creation and reuse

Figure 7: AMS IP export and integration

Selection of viewsto be created

Target PDK

Target DFH librarywhere generated

DFH will be located

Repository directorywhere non-DFH

outputs will be stored

Processing scratch rundirectory for various

log files andtemporary data

Definition of powerand ground nodes

used at several stagesof view creation (RCX,CeltiC, VoltageStorm)

Inherited connectionsdefinition forglobal nodes

List of cell found invarious inputs data andthe target repositorylibrary if it already existsEach entry represents acell and columnsrepresents views thatneed to be created andto be re-used


On the importing and integration side, feasibility of IP integration employing multi-technology simulation (MTS) is exemplified, followed by actual import using Vulcan technology. Legacy cdb file import into the Virtuoso OpenAccess (OA) database is shown. Importing of digital IP in an analog context is also presented.

TOP-DOWN PHYSICAL DESIGN

The physical design flow introduces a true top-down approach to chip layout using state-of-the-art Virtuoso technologies. Special emphasis is given to early floorplanning to get information about the critical parasitics to feed back to the verification flow. This is possible through a Virtuoso Floorplanner, a Physical Hierarchy Configurator, and an Abstract Generator, along with several floorplanning techniques like connectivity analysis, area estimation, pushdown block shaping, and pin optimization. The flow is illustrated on the PLL.

The analog-oriented physical assembly and routing is described using both Virtuosos Chip Assembly Router and Virtuoso Space-Based Router, both accepting design constraints. The flow is demonstrated by top-level routing of the Ethernet PHY and the PLL macro using advanced analog routing techniques like critical signal, differential signal, shielded signal, bundle, and supply routing. After routing, chip finishing is applied, including metal density and antenna checks, metal filling, and guard rings.

The assembled layout is then verified using Cadence Assura® verification technology with dedicated scenarios for Design Rule Checking (DRC), Layout Versus Schematic (LVS) checking, and Parasitic Extraction (RCX) applied to the Ethernet PHY. A comprehensive guide to practical Assura features like flat and hierarchical, black-box or selected area checking, different netlisting, and extracted parasitic formats is illustrated.

EXECUTABLE SCENARIOS

DESIGN ENVIRONMENT AND INFRASTRUCTURE FLOW

• AMSdesignflowoverview

• Foundryenablement

• Projectenvironmentsetup

• AutomatedprojectsetupwiththeDesignEnvironmentandConfiguration Manager

• ReferenceDataSurveyor

• ITDBimplementation

TOP-DOWN FUNCTIONAL VERIFICATION FLOW

• Designpartitioningandsimulationplanning

• Conceptvalidation

• AMS/Simulinkco-simulation

• AMSfunctionalverification

• Signofffunctionalverification

• IDDQsimulation

• EMIRdropanalysiswithDSPFstitching

AMS IP BLOCK CREATION AND REUSE FLOW

• Constraint-drivenanalogblockcreation

• Analogblockdesignsimulation

• Analogblockdesignoptimization

• Interactiveassistedanaloglayout

• Electricalyieldoptimization

• LayoutyieldoptimizationwithVirtuosoLayoutOptimizer

• Digitalblockimplementation

AMS IP EXPORT AND INTEGRATION FLOW

• AnalogIPcharacterization,frontend

• AnalogIPcharacterization,backend

• IPimportfeasibilitystudyusingMTS

• IPImportusingVulcanmethodology

• IPimportforVirtuosomethodologyFigure 8: AMS top-down physical design

© 2009 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Assura, Encounter, Spectre, Verilog, and Virtuoso are registered trademarks and SoC Encounter is a trademark of Cadence Design Systems, Inc. All others are properties of their respective holders.

21053 06/09 MK/MVC/DM/PDF

• VirtuosointegrationofdigitalIP

• DigitalIPcharacterization

• IPpackagingforpublishingandreuse

TOP-DOWN PHYSICAL DESIGN FLOW

• Hierarchicalfloorplanning

• Top-levelassemblywithVirtuosoChipAssemblyRouter

• Top-levelassemblywithVirtuosoSpace-BasedRouter

• Chipfinishing

• PhysicalverificationAssuraDRC

• PhysicalverificationwithAssuraLVS

• ParasiticextractionwithAssuraRCX

For more information contact Cadence sales at:

+1.408.943.1234

or log on to:

www.cadence.com/ contact_us

PRODUCT INTEGRATION• VirtuosoMulti-ModeSimulation

• VirtuosoSpectreCircuitSimulator

• VirtuosoAMSDesignerSimulator

• VirtuosoUltraSimFull-ChipSimulator

• VirtuosoAnalogDesignEnvironment(ADE)

• VirtuosoSchematicEditor

• VirtuosoLayoutSuite

• VirtuosoLayoutMigrate

• VirtuosoAnalogVoltageStormOption

• VirtuosoAnalogElectronStormOption

• AssuraDesignRuleChecker(DRC)

• AssuraLayoutvs.Schematic(LVS)Verifier

• AssuraParasiticExtraction(RCX)

• SoCEncounter™ RTL-to-GDSII System