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A Python-Based Layout-Aware Analog DesignMethodology For Nanometric Technologies

Stephanie Youssef, Farakh Javid, Damien Dupuis, Ramy Iskander,Marie-Minerve Louërat

To cite this version:Stephanie Youssef, Farakh Javid, Damien Dupuis, Ramy Iskander, Marie-Minerve Louërat. A Python-Based Layout-Aware Analog Design Methodology For Nanometric Technologies. IEEE 6th Interna-tional Design and Test Workshop (IDT), Dec 2011, Beyrouth, Lebanon. pp.62-67. �hal-00749906�

A Python-Based Layout-Aware Analog Design

Methodology For Nanometric Technologies.

Stephanie Youssef, Farakh Javid, Damien Dupuis, Ramy Iskander and Marie-Minerve Louerat

University Pierre et Marie Curie (UPMC), LIP6 Laboratory, 4, Place Jussieu, 75005 Paris, France

Email : stephanie.youssef@lip6.fr

Abstract—This paper presents a methodology for procedurallayout-aware design for nanometric technologies. A Python-basedlayout generation tool generates different layout styles for thesame basic analog building blocks. Moreover, layout dependentparasitic parameters such as stress effects are easily computedand compared for different layout styles. The procedural layoutdescription is written using a Python API that ensures layoutportability over different technologies. A main focus is on howthe layout generation tool addresses both geometric and parasitic-aware electrical synthesis. This is made possible through aninternal loop that links circularly both the sizing phase and thelayout generation phase. The proposed design methodology assiststhe analog designer in exploring electrical and physical trade-offs.At the end, we present synthesis and characterization results thatprove the effectiveness and speed of the proposed methodology.

I. INTRODUCTION

The demanding of low-power design and a reduced time

to market are the key of success for microelectronics industry.

There are many CAD tools in the digital domain that continue

to improve and ensure the security of the future of the digital

designers. In analog domain this is more complex. The main

obstacle is that unlike the digital circuits, analog circuits are

very sensitive to small variations and the performance may be

affected easily. This is why most of analog designers tradi-

tionally size manually their circuits and perform a full custom

layout which is laborious and error-prone. Another important

point is that with the migration to deep-sub-micron (DSM)

technologies, providing less area, less power consumption

and higher speed integrated circuits, two important constraints

related to the layout of the circuit have to be taken into

consideration:

a) The problem of analog device matching: Due to the

manufacturing process, it is hard to accurately control large

transistors’ widths. Transistor folding technique is commonly

used to reduce parasitic capacitance and gate resistance [1], [2]

allowing more accurate geometries and providing better elec-

trical performance. Interdigitation and mirror styles are usually

used to equally distribute process gradients along the device.

b) The Shallow Trench Isolation (STI): The DSM tech-

nologies use Shallow Trench Isolation (STI) for its accurate

dimension control when compared with LOCOS isolation [3].

STI is implemented in the form of trenches etched into the

wafer and filled with silicon dioxide to isolate the active area

of the transistors. Although STI provides some degree of latch-

up protection [4], this isolation technique induces mechanical

stress on the transistor and hence degrades its performance [5].

As shown in [6] and [7], this mechanical stress is highly

dependent on the layout style being used. To reduce the impact

of mechanical stress, the layout must be designed so that all

the transistors of the device are affected in the same way.

To keep a hard link between the electrical and the physical

view, the analog designer needs to have a precise estimation

of the impact of the layout on transistor characterization. This

makes the design more complex to be performed using the

manually traditional flow.

The automation of fundamental analog design steps, by

providing a two way-communication between the electrical

and the physical views, is extremely relevant for the success of

a project. Several works, such as [8], [9], [10] and [11], target

the automation of the layout generation of analog circuits.

To our knowledge, very few number of tools provide the

designer with a fast and accurate way to realize different

layouts for the same analogue atomic function. A remarkable

progress has been made by CIRANOVA [12] which develops

parametrized cells in Python Language, known as PyCells. Py-

Cells deliver physical views in OpenAccess [13] which is Ca-

dence standard and interoperable database. Many EDA startups

have invested in developing OpenAccess native applications.

OpenAccess is currently being pushed as a standard database

for the EDA industry. OpenAccess assures interoperability,

speed, usability. Yet, interoperability standards still need to

be agreed upon for this to be true.

In this paper, we will focus on developing a library of

analog basic building blocks called devices that supports

different layout styles (interdigitated, mirror, M2 module and

2D common centroid). We propose a methodology that allows

to size and bias a device and generate different layout styles

seamlessly. The idea is to well characterize the electrical and

the physical parameters of the device to meet functional and

robustness constraints [14]. Based on [15], sizing and biasing

operators are integrated in a loop with very fast nanometric

layout generation tool that allows to describe device layouts

in Python. The sizing operators propose sizes to the layout

generation tool. This in turn realizes the layout for a given

style. Then it computes physical sizes, stress effects as well

as layout dependent parameters. These are then fed back to the

sizing operator to be taken into account in the next iteration.

We show that the flow is very simple and achieves satisfactory

results in a matter of seconds. The advantage of the proposed

flow is to couple seamlessly and in a procedural manner both

transistor sizing and nanometric layout generation, with strong

The distances provided by the stack are :

• DMCI: distance from the middle diffusion contact till the

isolation edge.

• DMCG: distance from the middle diffusion contact till

the gate edge.

• DGG: distance between two successive gates. This is

equal to 2 × DMCG.

• DGI: distance from the edge of the end gate to the

isolation edge. This is equal to DMCI + DMCG.

Each distance has a method to query it in the stack object.

C. Layout Dependent Parameter Computation Methods

A dedicated Python API has been developed to describe

the device layout. In addition to the methods describing the

layout, three special methods have been developed to compute

the layout dependent parameters of the MOS transistor model.

The first one computes the area and perimeter of the source

and drain zones, the second one computes the stress effect

parameters as introduced in BSIM4 [16] and the third one

computes the capacitance of the routing wires.

D. Stress effect parameter computation

1) The stress effects for a transistor: In the BSIM4

model [16] the stress effect parameters are SA, SB, SD as

shown in Fig. 3.

• SA: Distance from the first left gate edge at the left end

of the stack till the isolation edge at the left end of the

stack. This is computed using:

SA = DGI + NBdummy × (Ldummy + DGG) (1)

where NBDummy is the number of dummies and

Ldummy is the dummy transistor length.

• SB: Distance from the first right gate edge at the right

end of the stack till the isolation edge at the right end of

the stack. This is computed using:

SB = DGI + NBDummy × (Ldummy + DGG) (2)

where NBDummy is the number of dummies and

Ldummy is the dummy transistor length.

• SD: Distance between two successive gates. This is set

equal to DGG.

Fig. 3. The stress effect parameters for the transistor.

W

L

W

L

Ids

Ids

����

M2M1

VIN+ VIN−

Fig. 4. Differential Pair Schematic View.

2) The stress effects for a Differential Pair: When consid-

ering the effects of mechanical stress on a differential pair, the

analysis differs significantly from the standalone transistor. For

the case of a standalone transistor, all the fingers belong to the

same device. On the other hand, a differential pair requires the

matching of two different transistors. The calculation of the

stress effects parameters becomes more complicated as it deals

with matched fingers from different transistors. In this case, the

calculation of stress parameters for a differential pair depends

on the layout style chosen for the differential pair. Fig. 5 shows

a differential pair consisting of transistors T1 and T2. In the

following, we discuss the stress effects calculations for the

layout styles: mirror and interdigitation.

Fig. 5. The stress effect parameters for the mirror style.

The stress effect parameters for differential pair can be

calculated as the transistor device by treating each transistor

(T1 and T2) separately using the equations (3)-(6).

InvSA,T1 =

(NFS−1)∑

i=0

δi

SA + 0.5 · Ldrawn + i · (SD + Ldrawn)

(3)

InvSB,T1 =

(NFS−1)∑

i=0

δi

SB + 0.5Ldrawn + i · (SD + Ldrawn)

(4)

SAeff =1

InvSA

(5)

SBeff =1

InvSB

(6)

We have improved the BSIM4 model to take into account

that the calculations of one transistor change according to

the position of its fingers. Note that the summation is carried

out on the range from 0 to NFS − 1. The presence of the

fingers of the other transistor alternating to the calculated

transistor’s fingers creates what we called holes . This requires

the introduction of a new parameter δ in the initial formula of

BSIM4. The parameter δ takes the value of 1 when pointing to

a finger of the transistor considered, and the value of 0 when

pointing to a finger of the other transistors.

The stress effects affect model parameters such as the

effective mobility µeff , the velocity saturation Vsat and the

Did intrinsic

target values ?

performances achieved+_

Sizing & Biasing

OPVS(Veg,Vb) W , Ve s

Choose Veg, Vd, Vg, Vb

Temp, Ids , L, gm0 target

START

END

∆I = I I

Style, W , L , Me ph

Parameters

yes

no

Layout Characterization

ph

e ph

ph

Ids, gm, gds, Cgs, Cgd, Cgb

W , L , Layout Dependent

OPIDS(W , L ,V , Layout Dependent Parameters) s

ds ds ds

Layout Generation

Fig. 6. Sizing and layout generation design flow

threshold voltage Vth [17], [18], [19]. To reflect the influence

of SAeff and SBeff , the parameter ”α” is defined as follows:

α =1

12SAeff

+ 12SBeff

(7)

Notice how stress effects, quantified by 1/α decrease by

increasing NF.

E. The design flow

Figure 6 illustrates how the operators and the layout method

are used to implement a device while respecting specifications.

In the first step, given the temperature, the biasing current

IDS , the overdrive gate voltage VEG, the drain voltage VD,

the gate voltage VG, the bulk voltage VB and the transistor

length L, the operator OPVS is used to compute the electrical

width We, the source voltage VS and the threshold voltage

VTH . The width We, length Le, number of fingers M and

layout style are given to the layout generator. Once the layout

is generated, the actual physical width Wph and length Lph

as well as the layout dependent parameters (diffusion zone,

stress and routing) are available. An accurate characterization,

including the actual physical realization, is performed using

the OPIDS operator that provides the actual IDS and the small

signal parameters for the purpose verification.

Here, we choose to take the gm as a specification for the

case of the differential pair. If the gm value does not meet the

specification, a loop is set to adjust the biasing current till the

specifications are achieved. After convergence, the final layout

is then realized.

Note that in the flow, all parameters varies, except the layout

style and the number of fingers that are kept invariant in this

loop.

III. RESULTS

A. Layout generation tool

In Fig. 7 we show the graphical user interface for the

layout generation tool CHAMS/Pharos. The upper left widget,

labeled Device Explorer shows the different layout parameters

set by the designer. The lower left message console prints the

values of all the layout dependent parameters. The script editor

in the lower right side of the GUI allows editing and executing

Python code.

Once the generation of the layout of the device is performed,

and thanks to the layout dependent parameter computation

methods, we have immediately the generic curves of the layout

dependent parameters versus NF as shown in Fig.8 and Fig.9:

a) Mirror style: Fig. 8 illustrates the generated curve 1/αversus NF for NMOS differential pair in mirror style in 65nm

technology with W = 6µm and L = 0.15µm.

Fig. 8. The stress effect 1/α parameter versus NF of the Mirror style.

b) Interdigitated style: Fig. 9 illustrates the generated

curve 1/α versus NF for NMOS differential pair in inter-

digitated style in 65nm technology with W = 6µm and L =

0.15µm. We can observe in Fig. 9 that, for the interdigitated

Fig. 9. The stress effect 1/α parameter versus NF of the interdigitated style.

technique, the stress effect affects the two transistors the same

way. While, for the mirror technique in Fig. 8, T1 transistor,

placed at the extremities of the stack, suffers a more significant

stress effect than transistor T2. This is due to the fact that

T1 is closer to the STI. So, the interdigitated technique in

the nanometer technology is more preferable unlike the older

technologies that prefer the mirror techniques.

B. Case study: Design of a Differential Pair

The goal is to design a differential pair in a CMOS 65nm

technology with a specified gm equals to 0.37 mS. The

assumption: VEG,VD, VG, VB and the transistor length L (set

Fig. 7. CHAMS/Pharos layout generation tool environment

Fig. 10. Differential Pair (interdigitated layout style) 65nm

Fig. 11. Differential Pair (M2 module layout style) 65nm

to 3.Lmin), are known. The design is performed for 4 different

layout styles with 4 fingers.

The results of the execution of the loop in Fig. 6 is

presented in the case of the four layout styles, Table II for

the interdigitated style, Table III for the mirror, Table IV

for the M2-module style and Table V for the 2D common-

centroid. The Iter parameter is the number of iteration in the

loop, Wph is the transistor width, IDS is the drain current

biasing the transistor, gm is the transistor transconductance

and SAeff , SBeff and 1/α are the stress parameters defined

by the BSIM4 model. The corresponding layouts are presented

in Fig. 10 (interdigitated), Fig. 11 (M2 module), Fig. 12 (2D

common-centroid) and Fig. 13 (mirror) respectively.

Fig. 12. Differential Pair (2D common centroid layout style) 65nm

Fig. 13. Differential Pair (mirror layout style) 65nm

Let us examine Table V for the differential pair with 2D

Common Centroid style . After all the loop iterations to get

the required gm, we can get many information about the

electrical and the physical parameters such as the electrical

intrinsic capacitances: Cgs = 2.39fF , Cds = 1.16fF ,

Cgd = 0.558fF , Cgb = 0.37fF , etc ... Also the physical

parasitic routing capacitances: Cgph= 0.0581fF ,Cdph

=0.0937fF ,Csph

= 0.03.89fF , etc ... related to the net gate

TABLE IIRESULTS 65NM INTERDIGITATED (T2 TRANSISTOR)

Iter Wph IDS gm SAeff SBeff 1/α(µm) (µA) (mS) (µm) (µm) (µm−1)

1 0.9 29.37 0.245 2.22 0.81 0.842

2 0.93 29.98 0.25 2.22 0.81 0.842

27 1.43 43.64 0.364 2.22 0.81 0.842

28 1.45 44.19 0.369 2.22 0.81 0.842

TABLE IIIRESULTS 65NM MIRROR (T2 TRANSISTOR)

Iter Wph IDS gm SAeff SBeff 1/α(µm) (µA) (mS) (µm) (µm) (µm−1)

1 0.9 29.60 0.247 1.99 1.99 0.5025

2 0.93 30.30 0.253 1.99 1.99 0.5025

26 1.41 43.62 0.363 1.99 1.99 0.5025

27 1.43 44.18 0.368 1.99 1.99 0.5025

TABLE IVRESULTS 65NM M2 (T2 TRANSISTOR)

Iter Wph IDS gm SAeff SBeff 1/α(µm) (µA) (mS) (µm) (µm) (µm−1)

1 0.9 28.24 0.236 0.48 0.48 2.08

2 0.94 29.07 0.243 0.48 0.48 2.08

29 1.485 43.18 0.362 0.48 0.48 2.08

30 1.505 43.74 0.366 0.48 0.48 2.08

TABLE VRESULTS 65NM 2D-COMMONCENTROID (T2 TRANSISTOR)

Iter Wph IDS gm SAeff SBeff 1/α(µm) (µA) (mS) (µm) (µm) (µm−1)

1 0.9 28.92 0.241 1.59 0.48 1.356

2 0.93 29.52 0.247 1.59 0.48 1.356

28 1.45 43.43 0.363 1.59 0.48 1.356

29 1.47 43.96 0.368 1.59 0.48 1.356

’G’, drain ’D’ and source ’S’ respectively. We can calculate

similarly the transition frequency defined as:

Ft =gm

2Π(Cgs + Cgd + Cgb + Cgph+ Csph

)= 17.6GHz

The overall computation time for the optimization loop is

around 6s (1s for the sizing, 5s for layout generation). The

average number of iterations is less than 30.

We conclude from the tables that the target gm can be

achieved under the influence of stress effect for the different

layout styles. This has to be compromised with matching

requirements in order to choose the final layout style.

IV. CONCLUSION

In this paper, a new method for developing smart

parametrized generators for analogue devices has been pre-

sented. The interaction between the transistor sizing and the

layout generation of the device has been illustrated in the

case of the differential pair. Four different layout styles have

been compared. The tight coupling between the transistor

sizing and the layout generation has been used to accurately

characterize a design. The proposed method allows the de-

signer to select the most convenient device layout style for

given specifications. The results showed the efficiency of the

proposed method. As a future work, the proposed method

will be extended to allow a seamless coupling between circuit

level sizing and layout generation, taking into account intrinsic

device performance.

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