analog layout 20111028

Analog LayoutAdvisor: Ke-Horng Chen Student: Yu-Huei Lee 2011.10.28

MixedSignalandPowerICLab NCTU,LAB912

Outline

Layout of MOS Transistor Layout of Resistor Layout of Capacitor OPA Layout


Layout styles of MOS Transistor Schematic viewVDD

Layout view

CMOS cross section view


Layout styles of MOS Transistor


Layout styles of MOS TransistorContact Resistance

Metal1 Rc N+ Poly (b) Equivalent circuitMixedSignalandPowerICLab NCTU,LAB912

Layout styles of MOS Transistor Gate Etching Effect

1 W 2 I d oCOX Vgs Vt 2 LMixedSignalandPowerICLab NCTU,LAB912

Layout styles of MOS Transistor Gate Etching Effect

Compensation of Boundary dependent etching with dummy elementsMixedSignalandPowerICLab NCTU,LAB912

Layout styles of MOS Transistor Gate Etching EffectIref Iout

Dummy

M1

M2

Dummy


Layout styles of MOS Transistor D G SS G D

D 16/1 G S 4/1 4/1 4/1 4/1

D

G

S

G

D

G

S

G

D

MOSMOSLW NMixedSignalandPowerICLab NCTU,LAB912


MOSSourceDrain SourceDrain


Layout styles of MOS Transistor Gradient EffectM1 M2

GradientMixedSignalandPowerICLab NCTU,LAB912

Layout styles of MOS Transistor Gradient Effect


Layout styles of MOS Transistor One Dimensional Common-Centroid Arrays


Layout styles of MOS Transistor Two Dimensional Common-Centroid Arrays


Layout styles of MOS Transistor Common Centroid MOS M1a M2a M2b M1b

a

1Cox M1a M2a

2Cox M1b

3Cox M2b

4Cox

b

1Cox

2Cox

3Cox

4Cox


Layout styles of MOS Transistor Common Centroid

1/2M1

1/2M2

1/2M2

1/2M1


Layout styles of MOS Transistor Common Centroid

bM1M1 M2

M2

S

D

S

D

S

D

S

D

M1

M2

M2

M1

M2

M1

S

D

S

D

S

D

S

D

S

D

S

D

a

cMixedSignalandPowerICLab NCTU,LAB912

d





Layout styles of MOS Transistor Differential pair

b

a


c


Out_P Out_N




Layout styles of MOS Transistor A Wide Digital Transistor Layout

G

SMixedSignalandPowerICLab NCTU,LAB912

G

Outline

Layout styles of MOS Transistor Layout of Resistor Layout of Capacitor OPA Layout


Layout of Resistor Resistance Estimation:

L R Rs ( )ohms W

t : thickness L: conductor length W: conductor width Rs: sheet resistance

R Rs (

4L )ohms 4W L Rs ( )ohms W


Layout of Resistor Process Parameters:*File: lvs35 . *************** Define Resistor ****************************************** ELEMENT RES[M1] MT1RES MT1 ;define metal resistor PARAMETER RES[M1] 0.083 . . ELEMENT RES[M4] MT4RES MT4 ;define metal resistor PARAMETER RES[M4] 0.051 ELEMENT RES[WR] RWELL NXWELL ;define n_well resistor PARAMETER RES[WR] 1050 ELEMENT RES[P1] RESPN CPOLY ;define ploy1 resistor PARAMETER RES[P1] 8.0 ELEMENT RES[PR] RESPP CPOLY ;define p+ploy1 resistor PARAMETER RES[PR] 8.0 ELEMENT RES[P2] RESP2 C2POLY ;define ploy2 resistor PARAMETER RES[P2] 50.0 ELEMENT RES[PD] RESDP PDIFF ;define pimp-DIFF resistor PARAMETER RES[PD] 150 ELEMENT RES[ND] RESDN NDIFF ;define nimp-DIFF resistor PARAMETER RES[ND] 80.0

R = Rs (L/W) ohmsMixedSignalandPowerICLab NCTU,LAB912

Layout of Resistor


Layout of Resistor


Layout of Resistor

NWELLSubstrate


Layout of Resistor


Layout of Resistor


Layout of Resistor Resistor Dummy & ShieldingDummyDummyDummy

Metal 2

Res

Res

Res

Res

Res

Res

DummyMixedSignalandPowerICLab NCTU,LAB912

Dummy

Metal 3

Layout of Resistor


Layout of Resistor


Layout of Resistor


Layout of Resistor


Outline



Layout of Capacitor


Layout of Capacitor


Layout of Capacitor


Layout of Capacitor


Layout of Capacitor


Layout of Capacitor


Layout of Capacitor Process Parameters:*File: lvs35 ********** Define Capacitor ******************************************** ELEMENT CAP[PC] CAPPL CPOLY C2POLY ;define poly cap. PARAMETER CAP[PC] 8.9E-16 7.3E-18 AND CDUMMY METAL1 MCAP1 AND MCAP1 METAL2 MCAP2 AND MCAP2 POLY1 MCAP3 ;define cap. region ELEMENT CAP[MC] MCAP3 MT1 MT2 ;define metal cap. PARAMETER CAP[MC] 9.0E-17 5.34E-17

Capacitance Estimation:

C


Layout of Capacitor Why Using Unit Capacitor?


Layout of Capacitor 45


Layout of Capacitor32 32 32 32 32 32 32 32 16 32 32 16 16 32 32 16 8 8 8 16 32 32 16 4 4 8 16 32 32 16 2 1 2 16 32 32 16 4 4 8 16 32 32 16 8 8 8 16 32 32 16 32 32 16 16 32 32 32 32 32 32 32 32


Layout of Capacitor


Outline



OPA Layout


OPA Layout


OPA LayoutVDD VDD

M1 M2

M3 M4

R2 OUT M5

IP

Q1

Q2

IN Q3

Q4

R1


The CMOS Differential Amplifiers with Active Load


OPA LayoutVDD

VBG M1 BP M4 M5 M6 COLLECT

R1

IN

M2

M3 C1

Q3

R2 Q1 Q2

M7

R3

R4


OPA Layout


OPA Layout


Thank you for your attention


analog layout 20111028

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